Go Back
FEB_1002 21.01.25 18:10:50
TextEdit.txt
18:10:50:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
18:10:50:ST3_Shared:INFO: FEB-ASIC
18:10:50:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
18:10:50:febtest:INFO: Testing FEB with SN 1002
18:10:51:smx_tester:INFO: Scanning setup
18:10:51:elinks:INFO: Disabling clock on downlink 0
18:10:51:elinks:INFO: Disabling clock on downlink 1
18:10:51:elinks:INFO: Disabling clock on downlink 2
18:10:51:elinks:INFO: Disabling clock on downlink 3
18:10:51:elinks:INFO: Disabling clock on downlink 4
18:10:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
18:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 1
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 2
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 3
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 4
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 5
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 6
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 7
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 8
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 9
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 10
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 11
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 12
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 13
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 14
18:10:51:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 15
18:10:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
18:10:51:elinks:INFO: Disabling clock on downlink 0
18:10:51:elinks:INFO: Disabling clock on downlink 1
18:10:51:elinks:INFO: Disabling clock on downlink 2
18:10:51:elinks:INFO: Disabling clock on downlink 3
18:10:51:elinks:INFO: Disabling clock on downlink 4
18:10:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
18:10:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
18:10:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
18:10:52:elinks:INFO: Disabling clock on downlink 0
18:10:52:elinks:INFO: Disabling clock on downlink 1
18:10:52:elinks:INFO: Disabling clock on downlink 2
18:10:52:elinks:INFO: Disabling clock on downlink 3
18:10:52:elinks:INFO: Disabling clock on downlink 4
18:10:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
18:10:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
18:10:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
18:10:52:elinks:INFO: Disabling clock on downlink 0
18:10:52:elinks:INFO: Disabling clock on downlink 1
18:10:52:elinks:INFO: Disabling clock on downlink 2
18:10:52:elinks:INFO: Disabling clock on downlink 3
18:10:52:elinks:INFO: Disabling clock on downlink 4
18:10:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
18:10:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
18:10:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
18:10:52:elinks:INFO: Disabling clock on downlink 0
18:10:52:elinks:INFO: Disabling clock on downlink 1
18:10:52:elinks:INFO: Disabling clock on downlink 2
18:10:52:elinks:INFO: Disabling clock on downlink 3
18:10:52:elinks:INFO: Disabling clock on downlink 4
18:10:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
18:10:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
18:10:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
18:10:52:setup_element:INFO: Scanning clock phase
18:10:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
18:10:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
18:10:52:setup_element:INFO: Clock phase scan results for group 0, downlink 0
18:10:52:setup_element:INFO: Eye window for uplink 0 : XX____________________________________________________________________________XX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 1 : XX____________________________________________________________________________XX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 2 : XXX_________________________________________________________________________XXXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 3 : XXX_________________________________________________________________________XXXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 4 : XXX_________________________________________________________________________XXXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 5 : XXX_________________________________________________________________________XXXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 6 : XX_________________________________________________________________________XXXXX
Clock Delay: 38
18:10:52:setup_element:INFO: Eye window for uplink 7 : XX_________________________________________________________________________XXXXX
Clock Delay: 38
18:10:52:setup_element:INFO: Eye window for uplink 8 : XXX__________________________________________________________________________XXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 9 : XXX__________________________________________________________________________XXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 10: XX__________________________________________________________________________XXXX
Clock Delay: 38
18:10:52:setup_element:INFO: Eye window for uplink 11: XX__________________________________________________________________________XXXX
Clock Delay: 38
18:10:52:setup_element:INFO: Eye window for uplink 12: XXX__________________________________________________________________________XXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 13: XXX__________________________________________________________________________XXX
Clock Delay: 39
18:10:52:setup_element:INFO: Eye window for uplink 14: XXXX_________________________________________________________________________XXX
Clock Delay: 40
18:10:52:setup_element:INFO: Eye window for uplink 15: XXXX_________________________________________________________________________XXX
Clock Delay: 40
18:10:52:setup_element:INFO: Setting the clock phase to 39 for group 0, downlink 0
==============================================OOO==============================================
18:10:52:setup_element:INFO: Scanning data phases
18:10:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
18:10:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
18:10:58:setup_element:INFO: Data phase scan results for group 0, downlink 0
18:10:58:setup_element:INFO: Eye window for uplink 0 : _________________________XXXXXX_________
Data delay found: 7
18:10:58:setup_element:INFO: Eye window for uplink 1 : _______________________XXXXXX___________
Data delay found: 5
18:10:58:setup_element:INFO: Eye window for uplink 2 : __________________________XXXXXX________
Data delay found: 8
18:10:58:setup_element:INFO: Eye window for uplink 3 : ___________________________XXXXX________
Data delay found: 9
18:10:58:setup_element:INFO: Eye window for uplink 4 : ___________________________XXXXXX_______
Data delay found: 9
18:10:58:setup_element:INFO: Eye window for uplink 5 : __________________________XXXXXX________
Data delay found: 8
18:10:58:setup_element:INFO: Eye window for uplink 6 : _______________________XXXX_____________
Data delay found: 4
18:10:58:setup_element:INFO: Eye window for uplink 7 : _____________________XXXXX______________
Data delay found: 3
18:10:58:setup_element:INFO: Eye window for uplink 8 : ________________________________XXXXX___
Data delay found: 14
18:10:58:setup_element:INFO: Eye window for uplink 9 : X_________________________________XXXXXX
Data delay found: 17
18:10:58:setup_element:INFO: Eye window for uplink 10: XXXX________________________________XXXX
Data delay found: 19
18:10:58:setup_element:INFO: Eye window for uplink 11: XXXX__________________________________XX
Data delay found: 20
18:10:58:setup_element:INFO: Eye window for uplink 12: _XXXXXX_________________________________
Data delay found: 23
18:10:58:setup_element:INFO: Eye window for uplink 13: __XXXXX_________________________________
Data delay found: 24
18:10:58:setup_element:INFO: Eye window for uplink 14: ______XXXXX_____________________________
Data delay found: 28
18:10:58:setup_element:INFO: Eye window for uplink 15: _______XXXXXX___________________________
Data delay found: 29
18:10:58:setup_element:INFO: Setting the data phase to 7 for uplink 0
18:10:58:setup_element:INFO: Setting the data phase to 5 for uplink 1
18:10:58:setup_element:INFO: Setting the data phase to 8 for uplink 2
18:10:58:setup_element:INFO: Setting the data phase to 9 for uplink 3
18:10:58:setup_element:INFO: Setting the data phase to 9 for uplink 4
18:10:58:setup_element:INFO: Setting the data phase to 8 for uplink 5
18:10:58:setup_element:INFO: Setting the data phase to 4 for uplink 6
18:10:58:setup_element:INFO: Setting the data phase to 3 for uplink 7
18:10:58:setup_element:INFO: Setting the data phase to 14 for uplink 8
18:10:58:setup_element:INFO: Setting the data phase to 17 for uplink 9
18:10:58:setup_element:INFO: Setting the data phase to 19 for uplink 10
18:10:58:setup_element:INFO: Setting the data phase to 20 for uplink 11
18:10:58:setup_element:INFO: Setting the data phase to 23 for uplink 12
18:10:58:setup_element:INFO: Setting the data phase to 24 for uplink 13
18:10:58:setup_element:INFO: Setting the data phase to 28 for uplink 14
18:10:58:setup_element:INFO: Setting the data phase to 29 for uplink 15
==============================================OOO==============================================
18:10:58:setup_element:INFO: Beginning SMX ASICs map scan
18:10:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
18:10:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
18:10:58:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
18:10:58:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
18:10:58:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
18:10:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 14
18:10:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 15
18:10:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 7
18:10:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 6
18:10:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 12
18:10:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 13
18:10:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 5
18:10:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 4
18:10:59:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 10
18:10:59:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 11
18:10:59:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 3
18:10:59:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 2
18:10:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 8
18:10:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 9
18:10:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 1
18:10:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 0
18:11:00:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 14), (1, 15)
ASIC address 0x1: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x2: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x3: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x4: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x5: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x6: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x7: (ASIC uplink, uplink): (0, 1), (1, 0)
Clock Phase Characteristic:
Optimal Phase: 39
Window Length: 71
Eye Windows:
Uplink 0: XX____________________________________________________________________________XX
Uplink 1: XX____________________________________________________________________________XX
Uplink 2: XXX_________________________________________________________________________XXXX
Uplink 3: XXX_________________________________________________________________________XXXX
Uplink 4: XXX_________________________________________________________________________XXXX
Uplink 5: XXX_________________________________________________________________________XXXX
Uplink 6: XX_________________________________________________________________________XXXXX
Uplink 7: XX_________________________________________________________________________XXXXX
Uplink 8: XXX__________________________________________________________________________XXX
Uplink 9: XXX__________________________________________________________________________XXX
Uplink 10: XX__________________________________________________________________________XXXX
Uplink 11: XX__________________________________________________________________________XXXX
Uplink 12: XXX__________________________________________________________________________XXX
Uplink 13: XXX__________________________________________________________________________XXX
Uplink 14: XXXX_________________________________________________________________________XXX
Uplink 15: XXXX_________________________________________________________________________XXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 1:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 2:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 4:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 5:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 6:
Optimal Phase: 4
Window Length: 36
Eye Window: _______________________XXXX_____________
Uplink 7:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 8:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 9:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 10:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
Uplink 11:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 12:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
Uplink 13:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 14:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 15:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
==============================================OOO==============================================
18:11:00:setup_element:INFO: Performing Elink synchronization
18:11:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
18:11:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
18:11:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
18:11:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
==============================================OOO==============================================
18:11:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
18:11:00:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 0 | 0 | [14] | 2 | [(0, 14), (1, 15)]
1 | [0] | 0 | 0 | [7] | 2 | [(0, 7), (1, 6)]
2 | [0] | 0 | 0 | [12] | 2 | [(0, 12), (1, 13)]
3 | [0] | 0 | 0 | [5] | 2 | [(0, 5), (1, 4)]
4 | [0] | 0 | 0 | [10] | 2 | [(0, 10), (1, 11)]
5 | [0] | 0 | 0 | [3] | 2 | [(0, 3), (1, 2)]
6 | [0] | 0 | 0 | [8] | 2 | [(0, 8), (1, 9)]
7 | [0] | 0 | 0 | [1] | 2 | [(0, 1), (1, 0)]
|_________________________________________________________________________|
18:11:01:febtest:INFO: Init all SMX (CSA): 30
18:11:14:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
18:11:14:febtest:INFO: 14-00 | XA-000-08-002-000-003-151-13 | 50.4 | 1100.2
18:11:14:febtest:INFO: 07-01 | XA-000-08-002-000-003-149-13 | 25.1 | 1195.1
18:11:15:febtest:INFO: 12-02 | XA-000-08-002-000-003-152-13 | 37.7 | 1153.7
18:11:15:febtest:INFO: 05-03 | XA-000-08-002-000-003-139-10 | 37.7 | 1159.7
18:11:15:febtest:INFO: 10-04 | XA-000-08-002-000-003-148-13 | 37.7 | 1153.7
18:11:15:febtest:INFO: 03-05 | XA-000-08-002-000-003-138-10 | 37.7 | 1159.7
18:11:15:febtest:INFO: 08-06 | -000-00-000-000-000-000-00 | 37.7 | 1153.7
18:11:16:febtest:INFO: 01-07 | XA-000-08-002-000-003-147-13 | 31.4 | 1189.2
18:11:17:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
18:11:17:febtest:WARNING: Chip address is 0!!!
18:11:17:febtest:ERROR: addres 0
18:11:24:ST3_smx:INFO: chip: 14-0 50.430383 C 1112.140140 mV
18:11:24:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:24:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:24:ST3_smx:INFO: Electrons
18:11:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:11:31:ST3_smx:INFO: ----> Checking Analog response
18:11:31:ST3_smx:INFO: ----> Checking broken channels
18:11:31:ST3_smx:INFO: Total # broken ch: 0
18:11:31:ST3_smx:INFO: List FAST: []
18:11:31:ST3_smx:INFO: List SLOW: []
18:11:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:31:ST3_smx:INFO: Holes
18:11:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:11:38:ST3_smx:INFO: ----> Checking Analog response
18:11:38:ST3_smx:INFO: ----> Checking broken channels
18:11:39:ST3_smx:INFO: Total # broken ch: 0
18:11:39:ST3_smx:INFO: List FAST: []
18:11:39:ST3_smx:INFO: List SLOW: []
18:11:40:ST3_smx:INFO: chip: 7-1 25.062742 C 1206.851500 mV
18:11:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:40:ST3_smx:INFO: Electrons
18:11:40:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:11:47:ST3_smx:INFO: ----> Checking Analog response
18:11:47:ST3_smx:INFO: ----> Checking broken channels
18:11:47:ST3_smx:INFO: Total # broken ch: 0
18:11:47:ST3_smx:INFO: List FAST: []
18:11:47:ST3_smx:INFO: List SLOW: []
18:11:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:47:ST3_smx:INFO: Holes
18:11:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:11:54:ST3_smx:INFO: ----> Checking Analog response
18:11:54:ST3_smx:INFO: ----> Checking broken channels
18:11:55:ST3_smx:INFO: Total # broken ch: 0
18:11:55:ST3_smx:INFO: List FAST: []
18:11:55:ST3_smx:INFO: List SLOW: []
18:11:56:ST3_smx:INFO: chip: 12-2 37.726682 C 1165.571835 mV
18:11:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:11:56:ST3_smx:INFO: Electrons
18:11:56:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:03:ST3_smx:INFO: ----> Checking Analog response
18:12:03:ST3_smx:INFO: ----> Checking broken channels
18:12:04:ST3_smx:INFO: Total # broken ch: 0
18:12:04:ST3_smx:INFO: List FAST: []
18:12:04:ST3_smx:INFO: List SLOW: []
18:12:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:04:ST3_smx:INFO: Holes
18:12:04:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:11:ST3_smx:INFO: ----> Checking Analog response
18:12:11:ST3_smx:INFO: ----> Checking broken channels
18:12:11:ST3_smx:INFO: Total # broken ch: 0
18:12:11:ST3_smx:INFO: List FAST: []
18:12:11:ST3_smx:INFO: List SLOW: []
18:12:13:ST3_smx:INFO: chip: 5-3 37.726682 C 1171.483840 mV
18:12:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:13:ST3_smx:INFO: Electrons
18:12:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:20:ST3_smx:INFO: ----> Checking Analog response
18:12:20:ST3_smx:INFO: ----> Checking broken channels
18:12:20:ST3_smx:INFO: Total # broken ch: 0
18:12:20:ST3_smx:INFO: List FAST: []
18:12:20:ST3_smx:INFO: List SLOW: []
18:12:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:20:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:20:ST3_smx:INFO: Holes
18:12:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:27:ST3_smx:INFO: ----> Checking Analog response
18:12:27:ST3_smx:INFO: ----> Checking broken channels
18:12:27:ST3_smx:INFO: Total # broken ch: 0
18:12:27:ST3_smx:INFO: List FAST: []
18:12:27:ST3_smx:INFO: List SLOW: []
18:12:29:ST3_smx:INFO: chip: 10-4 37.726682 C 1165.571835 mV
18:12:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:29:ST3_smx:INFO: Electrons
18:12:29:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:36:ST3_smx:INFO: ----> Checking Analog response
18:12:36:ST3_smx:INFO: ----> Checking broken channels
18:12:36:ST3_smx:INFO: Total # broken ch: 0
18:12:36:ST3_smx:INFO: List FAST: []
18:12:36:ST3_smx:INFO: List SLOW: []
18:12:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:36:ST3_smx:INFO: Holes
18:12:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:43:ST3_smx:INFO: ----> Checking Analog response
18:12:43:ST3_smx:INFO: ----> Checking broken channels
18:12:43:ST3_smx:INFO: Total # broken ch: 0
18:12:43:ST3_smx:INFO: List FAST: []
18:12:43:ST3_smx:INFO: List SLOW: []
18:12:44:ST3_smx:INFO: chip: 3-5 37.726682 C 1171.483840 mV
18:12:44:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:44:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:44:ST3_smx:INFO: Electrons
18:12:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:51:ST3_smx:INFO: ----> Checking Analog response
18:12:51:ST3_smx:INFO: ----> Checking broken channels
18:12:52:ST3_smx:INFO: Total # broken ch: 0
18:12:52:ST3_smx:INFO: List FAST: []
18:12:52:ST3_smx:INFO: List SLOW: []
18:12:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:12:52:ST3_smx:INFO: Holes
18:12:52:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:12:59:ST3_smx:INFO: ----> Checking Analog response
18:12:59:ST3_smx:INFO: ----> Checking broken channels
18:12:59:ST3_smx:INFO: Total # broken ch: 0
18:12:59:ST3_smx:INFO: List FAST: []
18:12:59:ST3_smx:INFO: List SLOW: []
18:13:01:ST3_smx:INFO: chip: 8-6 40.898880 C 1159.654860 mV
18:13:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:01:ST3_smx:INFO: Electrons
18:13:01:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:13:08:ST3_smx:INFO: ----> Checking Analog response
18:13:08:ST3_smx:INFO: ----> Checking broken channels
18:13:08:ST3_smx:INFO: Total # broken ch: 0
18:13:08:ST3_smx:INFO: List FAST: []
18:13:08:ST3_smx:INFO: List SLOW: []
18:13:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:08:ST3_smx:INFO: Holes
18:13:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:13:15:ST3_smx:INFO: ----> Checking Analog response
18:13:15:ST3_smx:INFO: ----> Checking broken channels
18:13:16:ST3_smx:INFO: Total # broken ch: 0
18:13:16:ST3_smx:INFO: List FAST: []
18:13:16:ST3_smx:INFO: List SLOW: []
18:13:17:ST3_smx:INFO: chip: 1-7 34.556970 C 1200.969315 mV
18:13:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:17:ST3_smx:INFO: Electrons
18:13:17:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:13:24:ST3_smx:INFO: ----> Checking Analog response
18:13:24:ST3_smx:INFO: ----> Checking broken channels
18:13:24:ST3_smx:INFO: Total # broken ch: 0
18:13:24:ST3_smx:INFO: List FAST: []
18:13:24:ST3_smx:INFO: List SLOW: []
18:13:24:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:24:ST3_discr_histo:WARNING: Not enough entries for fit!!!
18:13:24:ST3_smx:INFO: Holes
18:13:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
18:13:32:ST3_smx:INFO: ----> Checking Analog response
18:13:32:ST3_smx:INFO: ----> Checking broken channels
18:13:32:ST3_smx:INFO: Total # broken ch: 0
18:13:32:ST3_smx:INFO: List FAST: []
18:13:32:ST3_smx:INFO: List SLOW: []
18:13:32:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
18:13:32:febtest:INFO: 14-00 | XA-000-08-002-000-003-151-13 | 53.6 | 1130.0
18:13:32:febtest:INFO: 07-01 | XA-000-08-002-000-003-149-13 | 28.2 | 1224.5
18:13:33:febtest:INFO: 12-02 | XA-000-08-002-000-003-152-13 | 40.9 | 1183.3
18:13:33:febtest:INFO: 05-03 | XA-000-08-002-000-003-139-10 | 40.9 | 1189.2
18:13:33:febtest:INFO: 10-04 | XA-000-08-002-000-003-148-13 | 40.9 | 1183.3
18:13:33:febtest:INFO: 03-05 | XA-000-08-002-000-003-138-10 | 40.9 | 1189.2
18:13:33:febtest:INFO: 08-06 | -000-00-000-000-000-000-00 | 44.1 | 1177.4
18:13:34:febtest:INFO: 01-07 | XA-000-08-002-000-003-147-13 | 37.7 | 1218.6
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 25_01_21-18_10_50
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : TEST_SETUP_3
------------------------------------------------------------
| FEB_SN : 1002| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
MODULE_NAME
------------------------------------------------------------
VI_before_Init : ['2.800', '1.5080', '2.200', '2.4150', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.800', '2.0060', '2.200', '2.4380', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.800', '2.0130', '2.200', '0.5284', '0.000', '0.0000', '0.000', '0.0000']