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FEB_1002 10.07.23 15:45:58
TextEdit.txt
15:45:11:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,106569,HW50020003/SW2.62
15:45:14:ST3_Shared:INFO: Listo of operators:Robert V.;
15:45:15:ST3_Shared:INFO: Listo of operators:Robert V.; Irakli K.;
15:45:20:febtest:INFO: FEB8.2 selected
15:45:53:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:45:58:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:45:58:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:45:58:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:45:59:febtest:INFO: Tsting FEB with SN 1002
15:46:02:smx_tester:INFO: Scanning setup
15:46:02:elinks:INFO: Disabling clock on downlink 0
15:46:02:elinks:INFO: Disabling clock on downlink 1
15:46:02:elinks:INFO: Disabling clock on downlink 2
15:46:02:elinks:INFO: Disabling clock on downlink 3
15:46:02:elinks:INFO: Disabling clock on downlink 4
15:46:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:46:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:02:elinks:INFO: Disabling clock on downlink 0
15:46:02:elinks:INFO: Disabling clock on downlink 1
15:46:02:elinks:INFO: Disabling clock on downlink 2
15:46:02:elinks:INFO: Disabling clock on downlink 3
15:46:02:elinks:INFO: Disabling clock on downlink 4
15:46:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:02:elinks:INFO: Disabling clock on downlink 0
15:46:02:elinks:INFO: Disabling clock on downlink 1
15:46:02:elinks:INFO: Disabling clock on downlink 2
15:46:02:elinks:INFO: Disabling clock on downlink 3
15:46:02:elinks:INFO: Disabling clock on downlink 4
15:46:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:02:elinks:INFO: Disabling clock on downlink 0
15:46:02:elinks:INFO: Disabling clock on downlink 1
15:46:02:elinks:INFO: Disabling clock on downlink 2
15:46:02:elinks:INFO: Disabling clock on downlink 3
15:46:02:elinks:INFO: Disabling clock on downlink 4
15:46:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
15:46:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
15:46:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:02:elinks:INFO: Disabling clock on downlink 0
15:46:02:elinks:INFO: Disabling clock on downlink 1
15:46:02:elinks:INFO: Disabling clock on downlink 2
15:46:02:elinks:INFO: Disabling clock on downlink 3
15:46:02:elinks:INFO: Disabling clock on downlink 4
15:46:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:46:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:02:setup_element:INFO: Scanning clock phase
15:46:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:46:03:setup_element:INFO: Clock phase scan results for group 0, downlink 3
15:46:03:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:46:03:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:46:03:setup_element:INFO: Eye window for uplink 18: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
15:46:03:setup_element:INFO: Eye window for uplink 19: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
15:46:03:setup_element:INFO: Eye window for uplink 20: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:46:03:setup_element:INFO: Eye window for uplink 21: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:46:03:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXX______
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXX______
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
15:46:03:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
15:46:03:setup_element:INFO: Eye window for uplink 26: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 27: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 28: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 29: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXX______
Clock Delay: 30
15:46:03:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXX______
Clock Delay: 30
15:46:03:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 3
15:46:03:setup_element:INFO: Scanning data phases
15:46:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:46:08:setup_element:INFO: Data phase scan results for group 0, downlink 3
15:46:08:setup_element:INFO: Eye window for uplink 16: ________________XXXXX___________________
Data delay found: 38
15:46:08:setup_element:INFO: Eye window for uplink 17: ____________XXXX________________________
Data delay found: 33
15:46:08:setup_element:INFO: Eye window for uplink 18: __________XXXXXX________________________
Data delay found: 32
15:46:08:setup_element:INFO: Eye window for uplink 19: ________XXXXX___________________________
Data delay found: 30
15:46:08:setup_element:INFO: Eye window for uplink 20: _______XXXXX____________________________
Data delay found: 29
15:46:08:setup_element:INFO: Eye window for uplink 21: _____XXXXX______________________________
Data delay found: 27
15:46:08:setup_element:INFO: Eye window for uplink 22: ____XXXX________________________________
Data delay found: 25
15:46:08:setup_element:INFO: Eye window for uplink 23: _XXXXX__________________________________
Data delay found: 23
15:46:08:setup_element:INFO: Eye window for uplink 24: _________________________________XXXXX__
Data delay found: 15
15:46:08:setup_element:INFO: Eye window for uplink 25: XXX__________________________________XXX
Data delay found: 19
15:46:08:setup_element:INFO: Eye window for uplink 26: __________________________________XXXXX_
Data delay found: 16
15:46:08:setup_element:INFO: Eye window for uplink 27: XXXXX_________________________________XX
Data delay found: 21
15:46:08:setup_element:INFO: Eye window for uplink 28: X__________________________________XXXXX
Data delay found: 17
15:46:08:setup_element:INFO: Eye window for uplink 29: XXX__________________________________XXX
Data delay found: 19
15:46:08:setup_element:INFO: Eye window for uplink 30: __________________________________XXXXX_
Data delay found: 16
15:46:08:setup_element:INFO: Eye window for uplink 31: ________________________________XXXXX___
Data delay found: 14
15:46:08:setup_element:INFO: Setting the data phase to 38 for uplink 16
15:46:08:setup_element:INFO: Setting the data phase to 33 for uplink 17
15:46:08:setup_element:INFO: Setting the data phase to 32 for uplink 18
15:46:08:setup_element:INFO: Setting the data phase to 30 for uplink 19
15:46:08:setup_element:INFO: Setting the data phase to 29 for uplink 20
15:46:08:setup_element:INFO: Setting the data phase to 27 for uplink 21
15:46:08:setup_element:INFO: Setting the data phase to 25 for uplink 22
15:46:08:setup_element:INFO: Setting the data phase to 23 for uplink 23
15:46:08:setup_element:INFO: Setting the data phase to 15 for uplink 24
15:46:08:setup_element:INFO: Setting the data phase to 19 for uplink 25
15:46:08:setup_element:INFO: Setting the data phase to 16 for uplink 26
15:46:08:setup_element:INFO: Setting the data phase to 21 for uplink 27
15:46:08:setup_element:INFO: Setting the data phase to 17 for uplink 28
15:46:08:setup_element:INFO: Setting the data phase to 19 for uplink 29
15:46:08:setup_element:INFO: Setting the data phase to 16 for uplink 30
15:46:08:setup_element:INFO: Setting the data phase to 14 for uplink 31
15:46:08:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 68
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXX___
Uplink 17: _____________________________________________________________________XXXXXXXX___
Uplink 18: ____________________________________________________________________XXXXXXXX____
Uplink 19: ____________________________________________________________________XXXXXXXX____
Uplink 20: ____________________________________________________________________XXXXXXX_____
Uplink 21: ____________________________________________________________________XXXXXXX_____
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 24: _________________________________________________________________XXXXXXXXX______
Uplink 25: _________________________________________________________________XXXXXXXXX______
Uplink 26: ___________________________________________________________________XXXXXXXX_____
Uplink 27: ___________________________________________________________________XXXXXXXX_____
Uplink 28: ___________________________________________________________________XXXXXXXX_____
Uplink 29: ___________________________________________________________________XXXXXXXX_____
Uplink 30: ____________________________________________________________________XXXXXX______
Uplink 31: ____________________________________________________________________XXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 19:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 20:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 21:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 22:
Optimal Phase: 25
Window Length: 36
Eye Window: ____XXXX________________________________
Uplink 23:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 24:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 25:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 26:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 27:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 28:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 29:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 30:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 31:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
]
15:46:08:setup_element:INFO: Beginning SMX ASICs map scan
15:46:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:46:08:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
15:46:08:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
15:46:08:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:46:09:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
15:46:09:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
15:46:09:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
15:46:09:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
15:46:09:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
15:46:09:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
15:46:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
15:46:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
15:46:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
15:46:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
15:46:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
15:46:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
15:46:10:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
15:46:10:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
15:46:10:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
15:46:10:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
15:46:11:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 68
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXX___
Uplink 17: _____________________________________________________________________XXXXXXXX___
Uplink 18: ____________________________________________________________________XXXXXXXX____
Uplink 19: ____________________________________________________________________XXXXXXXX____
Uplink 20: ____________________________________________________________________XXXXXXX_____
Uplink 21: ____________________________________________________________________XXXXXXX_____
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 24: _________________________________________________________________XXXXXXXXX______
Uplink 25: _________________________________________________________________XXXXXXXXX______
Uplink 26: ___________________________________________________________________XXXXXXXX_____
Uplink 27: ___________________________________________________________________XXXXXXXX_____
Uplink 28: ___________________________________________________________________XXXXXXXX_____
Uplink 29: ___________________________________________________________________XXXXXXXX_____
Uplink 30: ____________________________________________________________________XXXXXX______
Uplink 31: ____________________________________________________________________XXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 19:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 20:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 21:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 22:
Optimal Phase: 25
Window Length: 36
Eye Window: ____XXXX________________________________
Uplink 23:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 24:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 25:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 26:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 27:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 28:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 29:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 30:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 31:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
15:46:11:setup_element:INFO: Performing Elink synchronization
15:46:11:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:11:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:46:11:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
15:46:11:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
15:46:11:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
15:46:11:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:46:11:ST3_emu:INFO: Number of chips: 8
15:46:11:ST3_emu:INFO: Chip address: 0x0
15:46:11:ST3_emu:INFO: Chip address: 0x1
15:46:11:ST3_emu:INFO: Chip address: 0x2
15:46:11:ST3_emu:INFO: Chip address: 0x3
15:46:11:ST3_emu:INFO: Chip address: 0x4
15:46:11:ST3_emu:INFO: Chip address: 0x5
15:46:11:ST3_emu:INFO: Chip address: 0x6
15:46:11:ST3_emu:INFO: Chip address: 0x7
15:46:13:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:13:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 37.7 | 1135.9
15:46:14:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 9.3 | 1247.9
15:46:14:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 3.0 | 1253.7
15:46:14:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 25.1 | 1189.2
15:46:14:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 12.4 | 1224.5
15:46:15:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 15.6 | 1230.3
15:46:15:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1177.4
15:46:15:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 3.0 | 1271.2
15:46:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:19:ST3_smx:INFO: chip: 0-0 31.389742 C 1147.806000 mV
15:46:19:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:19:ST3_smx:INFO: Electrons
15:46:19:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:21:ST3_smx:INFO: ----> Checking Analog response
15:46:21:ST3_smx:INFO: ----> Checking broken channels
15:46:22:ST3_smx:INFO: Total # broken ch: 0
15:46:22:ST3_smx:INFO: List FAST: []
15:46:22:ST3_smx:INFO: List SLOW: []
15:46:22:ST3_smx:INFO: Holes
15:46:22:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:24:ST3_smx:INFO: ----> Checking Analog response
15:46:24:ST3_smx:INFO: ----> Checking broken channels
15:46:24:ST3_smx:INFO: Total # broken ch: 0
15:46:24:ST3_smx:INFO: List FAST: []
15:46:24:ST3_smx:INFO: List SLOW: []
15:46:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:24:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:46:24:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 9.3 | 1242.0
15:46:24:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 6.1 | 1247.9
15:46:25:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 28.2 | 1189.2
15:46:25:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 12.4 | 1224.5
15:46:25:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 15.6 | 1230.3
15:46:25:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1171.5
15:46:26:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:46:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:30:ST3_smx:INFO: chip: 0-1 9.288730 C 1236.187875 mV
15:46:30:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:30:ST3_smx:INFO: Electrons
15:46:30:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:33:ST3_smx:INFO: ----> Checking Analog response
15:46:33:ST3_smx:INFO: ----> Checking broken channels
15:46:33:ST3_smx:INFO: Total # broken ch: 0
15:46:33:ST3_smx:INFO: List FAST: []
15:46:33:ST3_smx:INFO: List SLOW: []
15:46:33:ST3_smx:INFO: Holes
15:46:33:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:35:ST3_smx:INFO: ----> Checking Analog response
15:46:35:ST3_smx:INFO: ----> Checking broken channels
15:46:35:ST3_smx:INFO: Total # broken ch: 0
15:46:35:ST3_smx:INFO: List FAST: []
15:46:35:ST3_smx:INFO: List SLOW: []
15:46:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:36:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:46:36:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 12.4 | 1230.3
15:46:36:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 6.1 | 1247.9
15:46:36:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 28.2 | 1189.2
15:46:36:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 12.4 | 1224.5
15:46:37:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 15.6 | 1230.3
15:46:37:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1177.4
15:46:37:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:46:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:42:ST3_smx:INFO: chip: 0-2 15.590880 C 1206.851500 mV
15:46:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:42:ST3_smx:INFO: Electrons
15:46:42:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:44:ST3_smx:INFO: ----> Checking Analog response
15:46:44:ST3_smx:INFO: ----> Checking broken channels
15:46:44:ST3_smx:INFO: Total # broken ch: 0
15:46:44:ST3_smx:INFO: List FAST: []
15:46:44:ST3_smx:INFO: List SLOW: []
15:46:44:ST3_smx:INFO: Holes
15:46:44:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:46:ST3_smx:INFO: ----> Checking Analog response
15:46:46:ST3_smx:INFO: ----> Checking broken channels
15:46:47:ST3_smx:INFO: Total # broken ch: 0
15:46:47:ST3_smx:INFO: List FAST: []
15:46:47:ST3_smx:INFO: List SLOW: []
15:46:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:47:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1153.7
15:46:47:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 9.3 | 1236.2
15:46:47:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 15.6 | 1206.9
15:46:48:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 25.1 | 1189.2
15:46:48:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 12.4 | 1224.5
15:46:48:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 15.6 | 1230.3
15:46:48:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1177.4
15:46:48:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:46:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:54:ST3_smx:INFO: chip: 0-3 18.745682 C 1206.851500 mV
15:46:54:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:46:54:ST3_smx:INFO: Electrons
15:46:54:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:56:ST3_smx:INFO: ----> Checking Analog response
15:46:56:ST3_smx:INFO: ----> Checking broken channels
15:46:56:ST3_smx:INFO: Total # broken ch: 0
15:46:56:ST3_smx:INFO: List FAST: []
15:46:56:ST3_smx:INFO: List SLOW: []
15:46:56:ST3_smx:INFO: Holes
15:46:56:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:46:58:ST3_smx:INFO: ----> Checking Analog response
15:46:58:ST3_smx:INFO: ----> Checking broken channels
15:46:58:ST3_smx:INFO: Total # broken ch: 0
15:46:58:ST3_smx:INFO: List FAST: []
15:46:58:ST3_smx:INFO: List SLOW: []
15:46:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:58:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:46:59:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 12.4 | 1230.3
15:46:59:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 18.7 | 1201.0
15:46:59:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 21.9 | 1201.0
15:46:59:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 15.6 | 1224.5
15:46:59:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 15.6 | 1230.3
15:47:00:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1177.4
15:47:00:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:47:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:06:ST3_smx:INFO: chip: 0-4 18.745682 C 1200.969315 mV
15:47:06:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:06:ST3_smx:INFO: Electrons
15:47:06:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:09:ST3_smx:INFO: ----> Checking Analog response
15:47:09:ST3_smx:INFO: ----> Checking broken channels
15:47:10:ST3_smx:INFO: Total # broken ch: 0
15:47:10:ST3_smx:INFO: List FAST: []
15:47:10:ST3_smx:INFO: List SLOW: []
15:47:10:ST3_smx:INFO: Holes
15:47:10:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:12:ST3_smx:INFO: ----> Checking Analog response
15:47:12:ST3_smx:INFO: ----> Checking broken channels
15:47:12:ST3_smx:INFO: Total # broken ch: 0
15:47:12:ST3_smx:INFO: List FAST: []
15:47:12:ST3_smx:INFO: List SLOW: []
15:47:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:13:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:47:13:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 12.4 | 1236.2
15:47:13:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 18.7 | 1206.9
15:47:13:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 21.9 | 1206.9
15:47:14:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 18.7 | 1195.1
15:47:14:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 15.6 | 1230.3
15:47:14:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1177.4
15:47:14:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:47:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:20:ST3_smx:INFO: chip: 0-5 15.590880 C 1212.728715 mV
15:47:20:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:20:ST3_smx:INFO: Electrons
15:47:20:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:22:ST3_smx:INFO: ----> Checking Analog response
15:47:22:ST3_smx:INFO: ----> Checking broken channels
15:47:22:ST3_smx:INFO: Total # broken ch: 0
15:47:22:ST3_smx:INFO: List FAST: []
15:47:22:ST3_smx:INFO: List SLOW: []
15:47:22:ST3_smx:INFO: Holes
15:47:22:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:24:ST3_smx:INFO: ----> Checking Analog response
15:47:24:ST3_smx:INFO: ----> Checking broken channels
15:47:25:ST3_smx:INFO: Total # broken ch: 0
15:47:25:ST3_smx:INFO: List FAST: []
15:47:25:ST3_smx:INFO: List SLOW: []
15:47:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:25:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:47:25:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 9.3 | 1236.2
15:47:25:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 15.6 | 1206.9
15:47:26:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 18.7 | 1206.9
15:47:26:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 18.7 | 1195.1
15:47:26:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 18.7 | 1206.9
15:47:26:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 28.2 | 1177.4
15:47:26:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:47:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:33:ST3_smx:INFO: chip: 0-6 18.745682 C 1195.082160 mV
15:47:33:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:33:ST3_smx:INFO: Electrons
15:47:33:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:35:ST3_smx:INFO: ----> Checking Analog response
15:47:35:ST3_smx:INFO: ----> Checking broken channels
15:47:35:ST3_smx:INFO: Total # broken ch: 0
15:47:35:ST3_smx:INFO: List FAST: []
15:47:35:ST3_smx:INFO: List SLOW: []
15:47:35:ST3_smx:INFO: Holes
15:47:35:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:38:ST3_smx:INFO: ----> Checking Analog response
15:47:38:ST3_smx:INFO: ----> Checking broken channels
15:47:38:ST3_smx:INFO: Total # broken ch: 0
15:47:38:ST3_smx:INFO: List FAST: []
15:47:38:ST3_smx:INFO: List SLOW: []
15:47:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:38:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:47:39:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 12.4 | 1230.3
15:47:39:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 18.7 | 1201.0
15:47:39:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 21.9 | 1201.0
15:47:39:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 21.9 | 1195.1
15:47:39:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 18.7 | 1206.9
15:47:39:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 21.9 | 1189.2
15:47:40:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 6.1 | 1265.4
15:47:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:45:ST3_smx:INFO: chip: 0-7 12.438562 C 1236.187875 mV
15:47:45:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:47:45:ST3_smx:INFO: Electrons
15:47:45:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:47:ST3_smx:INFO: ----> Checking Analog response
15:47:47:ST3_smx:INFO: ----> Checking broken channels
15:47:48:ST3_smx:INFO: Total # broken ch: 0
15:47:48:ST3_smx:INFO: List FAST: []
15:47:48:ST3_smx:INFO: List SLOW: []
15:47:48:ST3_smx:INFO: Holes
15:47:48:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
15:47:50:ST3_smx:INFO: ----> Checking Analog response
15:47:50:ST3_smx:INFO: ----> Checking broken channels
15:47:50:ST3_smx:INFO: Total # broken ch: 0
15:47:50:ST3_smx:INFO: List FAST: []
15:47:50:ST3_smx:INFO: List SLOW: []
15:47:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:50:febtest:INFO: 0-0 | XA-000-08-002-000-003-151-13 | 31.4 | 1147.8
15:47:50:febtest:INFO: 0-1 | XA-000-08-002-000-003-149-13 | 9.3 | 1230.3
15:47:51:febtest:INFO: 0-2 | XA-000-08-002-000-003-152-13 | 18.7 | 1201.0
15:47:51:febtest:INFO: 0-3 | XA-000-08-002-000-003-139-10 | 21.9 | 1201.0
15:47:51:febtest:INFO: 0-4 | XA-000-08-002-000-003-148-13 | 18.7 | 1195.1
15:47:51:febtest:INFO: 0-5 | XA-000-08-002-000-003-138-10 | 18.7 | 1206.9
15:47:51:febtest:INFO: 0-6 | -000-00-000-000-000-000-00 | 21.9 | 1195.1
15:47:52:febtest:INFO: 0-7 | XA-000-08-002-000-003-147-13 | 12.4 | 1230.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_10-15_45_58', 'OPERATOR': 'Robert V.; Irakli K.; ', 'PROJECT': 'Test', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-003-147-13', 'FUSED_ID': 6359364699116550461, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['0.000', '0.0000', '2.499', '1.6390', '2.199', '2.4430', '7.000', '1.5290'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 110, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:48:15:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_1002/A//TestDate_2023_07_10-15_45_58/