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FEB_1004 21.07.23 10:52:26
Info
10:52:03:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:52:03:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
10:52:08:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:52:08:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
10:52:11:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:52:11:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
10:52:14:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:52:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:52:26:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:52:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:52:26:febtest:INFO: Tsting FEB with SN 1004
10:52:27:smx_tester:INFO: Scanning setup
10:52:27:elinks:INFO: Disabling clock on downlink 0
10:52:27:elinks:INFO: Disabling clock on downlink 1
10:52:27:elinks:INFO: Disabling clock on downlink 2
10:52:27:elinks:INFO: Disabling clock on downlink 3
10:52:27:elinks:INFO: Disabling clock on downlink 4
10:52:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:52:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:52:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:52:27:elinks:INFO: Disabling clock on downlink 0
10:52:27:elinks:INFO: Disabling clock on downlink 1
10:52:27:elinks:INFO: Disabling clock on downlink 2
10:52:27:elinks:INFO: Disabling clock on downlink 3
10:52:27:elinks:INFO: Disabling clock on downlink 4
10:52:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:52:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:52:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:52:27:elinks:INFO: Disabling clock on downlink 0
10:52:27:elinks:INFO: Disabling clock on downlink 1
10:52:27:elinks:INFO: Disabling clock on downlink 2
10:52:27:elinks:INFO: Disabling clock on downlink 3
10:52:27:elinks:INFO: Disabling clock on downlink 4
10:52:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:52:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:52:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:52:28:elinks:INFO: Disabling clock on downlink 0
10:52:28:elinks:INFO: Disabling clock on downlink 1
10:52:28:elinks:INFO: Disabling clock on downlink 2
10:52:28:elinks:INFO: Disabling clock on downlink 3
10:52:28:elinks:INFO: Disabling clock on downlink 4
10:52:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:52:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
10:52:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
10:52:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:52:28:elinks:INFO: Disabling clock on downlink 0
10:52:28:elinks:INFO: Disabling clock on downlink 1
10:52:28:elinks:INFO: Disabling clock on downlink 2
10:52:28:elinks:INFO: Disabling clock on downlink 3
10:52:28:elinks:INFO: Disabling clock on downlink 4
10:52:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:52:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:52:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:52:28:setup_element:INFO: Scanning clock phase
10:52:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:52:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
10:52:28:setup_element:INFO: Clock phase scan results for group 0, downlink 3
10:52:28:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
10:52:28:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
10:52:28:setup_element:INFO: Eye window for uplink 26: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
10:52:28:setup_element:INFO: Eye window for uplink 27: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
10:52:28:setup_element:INFO: Eye window for uplink 28: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
10:52:28:setup_element:INFO: Eye window for uplink 29: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
10:52:28:setup_element:INFO: Eye window for uplink 30: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
10:52:28:setup_element:INFO: Eye window for uplink 31: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
10:52:28:setup_element:INFO: Setting the clock phase to 29 for group 0, downlink 3
10:52:28:setup_element:INFO: Scanning data phases
10:52:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:52:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
10:52:34:setup_element:INFO: Data phase scan results for group 0, downlink 3
10:52:34:setup_element:INFO: Eye window for uplink 24: XXX__________________________________XXX
Data delay found: 19
10:52:34:setup_element:INFO: Eye window for uplink 25: _XXXXX__________________________________
Data delay found: 23
10:52:34:setup_element:INFO: Eye window for uplink 26: X___________________________________XXXX
Data delay found: 18
10:52:34:setup_element:INFO: Eye window for uplink 27: XXXXX__________________________________X
Data delay found: 21
10:52:34:setup_element:INFO: Eye window for uplink 28: XXX___________________________________XX
Data delay found: 20
10:52:34:setup_element:INFO: Eye window for uplink 29: XXXXXX__________________________________
Data delay found: 22
10:52:34:setup_element:INFO: Eye window for uplink 30: XXX__________________________________XXX
Data delay found: 19
10:52:34:setup_element:INFO: Eye window for uplink 31: XX_________________________________XXXXX
Data delay found: 18
10:52:34:setup_element:INFO: Setting the data phase to 19 for uplink 24
10:52:34:setup_element:INFO: Setting the data phase to 23 for uplink 25
10:52:34:setup_element:INFO: Setting the data phase to 18 for uplink 26
10:52:34:setup_element:INFO: Setting the data phase to 21 for uplink 27
10:52:34:setup_element:INFO: Setting the data phase to 20 for uplink 28
10:52:34:setup_element:INFO: Setting the data phase to 22 for uplink 29
10:52:34:setup_element:INFO: Setting the data phase to 19 for uplink 30
10:52:34:setup_element:INFO: Setting the data phase to 18 for uplink 31
10:52:34:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 71
Eye Windows:
Uplink 24: _________________________________________________________________XXXXXXXX_______
Uplink 25: _________________________________________________________________XXXXXXXX_______
Uplink 26: _________________________________________________________________XXXXXXXXX______
Uplink 27: _________________________________________________________________XXXXXXXXX______
Uplink 28: __________________________________________________________________XXXXXXX_______
Uplink 29: __________________________________________________________________XXXXXXX_______
Uplink 30: __________________________________________________________________XXXXXXXX______
Uplink 31: __________________________________________________________________XXXXXXXX______
Data phase characteristics:
Uplink 24:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 25:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 26:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 27:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 28:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 29:
Optimal Phase: 22
Window Length: 34
Eye Window: XXXXXX__________________________________
Uplink 30:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 31:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
]
10:52:34:setup_element:INFO: Beginning SMX ASICs map scan
10:52:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:52:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
10:52:34:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
10:52:34:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
10:52:34:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
10:52:34:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
10:52:34:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
10:52:34:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
10:52:34:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
10:52:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
10:52:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
10:52:35:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
10:52:35:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
10:52:36:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 71
Eye Windows:
Uplink 24: _________________________________________________________________XXXXXXXX_______
Uplink 25: _________________________________________________________________XXXXXXXX_______
Uplink 26: _________________________________________________________________XXXXXXXXX______
Uplink 27: _________________________________________________________________XXXXXXXXX______
Uplink 28: __________________________________________________________________XXXXXXX_______
Uplink 29: __________________________________________________________________XXXXXXX_______
Uplink 30: __________________________________________________________________XXXXXXXX______
Uplink 31: __________________________________________________________________XXXXXXXX______
Data phase characteristics:
Uplink 24:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 25:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 26:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 27:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 28:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 29:
Optimal Phase: 22
Window Length: 34
Eye Window: XXXXXX__________________________________
Uplink 30:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 31:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
10:52:36:setup_element:INFO: Performing Elink synchronization
10:52:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:52:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
10:52:36:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
10:52:36:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
10:52:36:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
10:52:36:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
10:52:37:ST3_emu:INFO: Number of chips: 4
10:52:37:ST3_emu:INFO: Chip address: 0x1
10:52:37:ST3_emu:INFO: Chip address: 0x3
10:52:37:ST3_emu:INFO: Chip address: 0x5
10:52:37:ST3_emu:INFO: Chip address: 0x7
10:52:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:37:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 37.7 | 1189.2
10:52:37:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 40.9 | 1177.4
10:52:38:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 40.9 | 1183.3
10:52:38:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1282.9
10:52:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:42:ST3_smx:INFO: chip: 0-1 34.556970 C 1177.390875 mV
10:52:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:52:42:ST3_smx:INFO: Electrons
10:52:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:52:44:ST3_smx:INFO: ----> Checking Analog response
10:52:44:ST3_smx:INFO: ----> Checking broken channels
10:52:44:ST3_smx:INFO: Total # broken ch: 7
10:52:44:ST3_smx:INFO: List FAST: [1, 3, 69, 89]
10:52:44:ST3_smx:INFO: List SLOW: [1, 3, 99]
10:52:44:ST3_smx:INFO: Holes
10:52:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:52:46:ST3_smx:INFO: ----> Checking Analog response
10:52:46:ST3_smx:INFO: ----> Checking broken channels
10:52:46:ST3_smx:INFO: Total # broken ch: 7
10:52:46:ST3_smx:INFO: List FAST: [1, 3, 69, 89]
10:52:46:ST3_smx:INFO: List SLOW: [1, 3, 99]
10:52:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:47:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 37.7 | 1177.4
10:52:47:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 40.9 | 1177.4
10:52:47:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1183.3
10:52:47:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1282.9
10:52:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:52:51:ST3_smx:INFO: chip: 0-3 34.556970 C 1183.292940 mV
10:52:51:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:52:51:ST3_smx:INFO: Electrons
10:52:51:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:52:53:ST3_smx:INFO: ----> Checking Analog response
10:52:53:ST3_smx:INFO: ----> Checking broken channels
10:52:54:ST3_smx:INFO: Total # broken ch: 0
10:52:54:ST3_smx:INFO: List FAST: []
10:52:54:ST3_smx:INFO: List SLOW: []
10:52:54:ST3_smx:INFO: Holes
10:52:54:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:52:55:ST3_smx:INFO: ----> Checking Analog response
10:52:55:ST3_smx:INFO: ----> Checking broken channels
10:52:56:ST3_smx:INFO: Total # broken ch: 0
10:52:56:ST3_smx:INFO: List FAST: []
10:52:56:ST3_smx:INFO: List SLOW: []
10:52:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:52:56:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 37.7 | 1177.4
10:52:56:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1183.3
10:52:56:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1177.4
10:52:57:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1282.9
10:52:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:53:01:ST3_smx:INFO: chip: 0-5 40.898880 C 1165.571835 mV
10:53:01:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:53:01:ST3_smx:INFO: Electrons
10:53:01:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:53:03:ST3_smx:INFO: ----> Checking Analog response
10:53:03:ST3_smx:INFO: ----> Checking broken channels
10:53:03:ST3_smx:INFO: Total # broken ch: 0
10:53:03:ST3_smx:INFO: List FAST: []
10:53:03:ST3_smx:INFO: List SLOW: []
10:53:03:ST3_smx:INFO: Holes
10:53:03:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:53:05:ST3_smx:INFO: ----> Checking Analog response
10:53:05:ST3_smx:INFO: ----> Checking broken channels
10:53:05:ST3_smx:INFO: Total # broken ch: 0
10:53:05:ST3_smx:INFO: List FAST: []
10:53:05:ST3_smx:INFO: List SLOW: []
10:53:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:53:06:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 34.6 | 1177.4
10:53:06:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
10:53:06:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 40.9 | 1159.7
10:53:06:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1282.9
10:53:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:53:10:ST3_smx:INFO: chip: 0-7 15.590880 C 1242.040240 mV
10:53:10:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:53:10:ST3_smx:INFO: Electrons
10:53:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:53:12:ST3_smx:INFO: ----> Checking Analog response
10:53:12:ST3_smx:INFO: ----> Checking broken channels
10:53:13:ST3_smx:INFO: Total # broken ch: 1
10:53:13:ST3_smx:INFO: List FAST: [4]
10:53:13:ST3_smx:INFO: List SLOW: []
10:53:13:ST3_smx:INFO: Holes
10:53:13:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
10:53:15:ST3_smx:INFO: ----> Checking Analog response
10:53:15:ST3_smx:INFO: ----> Checking broken channels
10:53:15:ST3_smx:INFO: Total # broken ch: 1
10:53:15:ST3_smx:INFO: List FAST: [4]
10:53:15:ST3_smx:INFO: List SLOW: []
10:53:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:53:15:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 34.6 | 1171.5
10:53:15:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
10:53:16:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 44.1 | 1159.7
10:53:16:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 18.7 | 1236.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_21-10_52_26', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-139-12', 'FUSED_ID': 6359364699116566716, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 1, 'N_BROKEN_FAST': '[4]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 1, 'P_BROKEN_FAST': '[4]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.450', '0.7840', '1.851', '1.3030', '7.000', '1.5250', '7.001', '1.5250'], 'VI_aInit': ['2.450', '2.0190', '1.850', '1.4640', '7.000', '1.5380', '7.000', '1.5380'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
10:53:22:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1004/A//TestDate_2023_07_21-10_52_26/