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FEB_1004 24.07.23 13:22:59
TextEdit.txt
13:22:41:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
13:22:42:febtest:INFO: FEB8.2 selected
13:22:42:febtest:INFO: FEB8.2 selected
13:22:46:ST3_Shared:INFO: Listo of operators:Robert V.;
13:22:46:ST3_Shared:INFO: Listo of operators:Alois Alzheimer
13:22:46:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
13:22:47:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Robert V.;
13:22:58:smx_tester:INFO: Setting Elink clock mode to 160 MHz
13:22:59:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:22:59:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
13:22:59:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:23:00:febtest:INFO: Tsting FEB with SN 1004
13:23:01:smx_tester:INFO: Scanning setup
13:23:01:elinks:INFO: Disabling clock on downlink 0
13:23:01:elinks:INFO: Disabling clock on downlink 1
13:23:01:elinks:INFO: Disabling clock on downlink 2
13:23:01:elinks:INFO: Disabling clock on downlink 3
13:23:01:elinks:INFO: Disabling clock on downlink 4
13:23:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:23:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:23:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:23:01:elinks:INFO: Disabling clock on downlink 0
13:23:01:elinks:INFO: Disabling clock on downlink 1
13:23:01:elinks:INFO: Disabling clock on downlink 2
13:23:01:elinks:INFO: Disabling clock on downlink 3
13:23:01:elinks:INFO: Disabling clock on downlink 4
13:23:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:23:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:23:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:23:01:elinks:INFO: Disabling clock on downlink 0
13:23:01:elinks:INFO: Disabling clock on downlink 1
13:23:01:elinks:INFO: Disabling clock on downlink 2
13:23:01:elinks:INFO: Disabling clock on downlink 3
13:23:01:elinks:INFO: Disabling clock on downlink 4
13:23:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:23:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:23:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:23:01:elinks:INFO: Disabling clock on downlink 0
13:23:01:elinks:INFO: Disabling clock on downlink 1
13:23:01:elinks:INFO: Disabling clock on downlink 2
13:23:01:elinks:INFO: Disabling clock on downlink 3
13:23:01:elinks:INFO: Disabling clock on downlink 4
13:23:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:23:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
13:23:02:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
13:23:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:23:02:elinks:INFO: Disabling clock on downlink 0
13:23:02:elinks:INFO: Disabling clock on downlink 1
13:23:02:elinks:INFO: Disabling clock on downlink 2
13:23:02:elinks:INFO: Disabling clock on downlink 3
13:23:02:elinks:INFO: Disabling clock on downlink 4
13:23:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:23:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:23:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:23:02:setup_element:INFO: Scanning clock phase
13:23:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:23:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:23:02:setup_element:INFO: Clock phase scan results for group 0, downlink 3
13:23:02:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
13:23:02:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
13:23:02:setup_element:INFO: Eye window for uplink 18: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
13:23:02:setup_element:INFO: Eye window for uplink 19: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
13:23:02:setup_element:INFO: Eye window for uplink 20: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
13:23:02:setup_element:INFO: Eye window for uplink 21: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
13:23:02:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXX____
Clock Delay: 32
13:23:02:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXX____
Clock Delay: 32
13:23:02:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:23:02:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:23:02:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:23:02:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:23:02:setup_element:INFO: Eye window for uplink 28: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:23:02:setup_element:INFO: Eye window for uplink 29: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:23:02:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
13:23:02:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
13:23:02:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 3
13:23:02:setup_element:INFO: Scanning data phases
13:23:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:23:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:23:08:setup_element:INFO: Data phase scan results for group 0, downlink 3
13:23:08:setup_element:INFO: Eye window for uplink 16: __________________XXXX__________________
Data delay found: 39
13:23:08:setup_element:INFO: Eye window for uplink 17: _____________XXXXX______________________
Data delay found: 35
13:23:08:setup_element:INFO: Eye window for uplink 18: ______________XXXXX_____________________
Data delay found: 36
13:23:08:setup_element:INFO: Eye window for uplink 19: ___________XXXXX________________________
Data delay found: 33
13:23:08:setup_element:INFO: Eye window for uplink 20: _________XXXX___________________________
Data delay found: 30
13:23:08:setup_element:INFO: Eye window for uplink 21: _______XXXXXX___________________________
Data delay found: 29
13:23:08:setup_element:INFO: Eye window for uplink 22: ________XXXX____________________________
Data delay found: 29
13:23:08:setup_element:INFO: Eye window for uplink 23: _____XXXX_______________________________
Data delay found: 26
13:23:08:setup_element:INFO: Eye window for uplink 24: __________________________________XXXXXX
Data delay found: 16
13:23:08:setup_element:INFO: Eye window for uplink 25: XXX___________________________________XX
Data delay found: 20
13:23:08:setup_element:INFO: Eye window for uplink 26: _________________________________XXXXX__
Data delay found: 15
13:23:08:setup_element:INFO: Eye window for uplink 27: XXX__________________________________XXX
Data delay found: 19
13:23:08:setup_element:INFO: Eye window for uplink 28: __________________________________XXXXX_
Data delay found: 16
13:23:08:setup_element:INFO: Eye window for uplink 29: XX__________________________________XXXX
Data delay found: 18
13:23:08:setup_element:INFO: Eye window for uplink 30: ___________________________________XXXXX
Data delay found: 17
13:23:08:setup_element:INFO: Eye window for uplink 31: _________________________________XXXXX__
Data delay found: 15
13:23:08:setup_element:INFO: Setting the data phase to 39 for uplink 16
13:23:08:setup_element:INFO: Setting the data phase to 35 for uplink 17
13:23:08:setup_element:INFO: Setting the data phase to 36 for uplink 18
13:23:08:setup_element:INFO: Setting the data phase to 33 for uplink 19
13:23:08:setup_element:INFO: Setting the data phase to 30 for uplink 20
13:23:08:setup_element:INFO: Setting the data phase to 29 for uplink 21
13:23:08:setup_element:INFO: Setting the data phase to 29 for uplink 22
13:23:08:setup_element:INFO: Setting the data phase to 26 for uplink 23
13:23:08:setup_element:INFO: Setting the data phase to 16 for uplink 24
13:23:08:setup_element:INFO: Setting the data phase to 20 for uplink 25
13:23:08:setup_element:INFO: Setting the data phase to 15 for uplink 26
13:23:08:setup_element:INFO: Setting the data phase to 19 for uplink 27
13:23:08:setup_element:INFO: Setting the data phase to 16 for uplink 28
13:23:08:setup_element:INFO: Setting the data phase to 18 for uplink 29
13:23:08:setup_element:INFO: Setting the data phase to 17 for uplink 30
13:23:08:setup_element:INFO: Setting the data phase to 15 for uplink 31
13:23:08:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: ____________________________________________________________________XXXXXXX_____
Uplink 19: ____________________________________________________________________XXXXXXX_____
Uplink 20: ___________________________________________________________________XXXXXXX______
Uplink 21: ___________________________________________________________________XXXXXXX______
Uplink 22: ______________________________________________________________________XXXXXX____
Uplink 23: ______________________________________________________________________XXXXXX____
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: __________________________________________________________________XXXXXXXX______
Uplink 29: __________________________________________________________________XXXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 39
Window Length: 36
Eye Window: __________________XXXX__________________
Uplink 17:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 18:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 19:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 20:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 21:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 22:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 23:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 24:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 28:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 29:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 30:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 31:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
]
13:23:08:setup_element:INFO: Beginning SMX ASICs map scan
13:23:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:23:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:23:08:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
13:23:08:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
13:23:08:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:23:08:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
13:23:08:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
13:23:08:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
13:23:08:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
13:23:08:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
13:23:08:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
13:23:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
13:23:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
13:23:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
13:23:09:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
13:23:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
13:23:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
13:23:09:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
13:23:09:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
13:23:09:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
13:23:09:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
13:23:11:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: ____________________________________________________________________XXXXXXX_____
Uplink 19: ____________________________________________________________________XXXXXXX_____
Uplink 20: ___________________________________________________________________XXXXXXX______
Uplink 21: ___________________________________________________________________XXXXXXX______
Uplink 22: ______________________________________________________________________XXXXXX____
Uplink 23: ______________________________________________________________________XXXXXX____
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: __________________________________________________________________XXXXXXXX______
Uplink 29: __________________________________________________________________XXXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 39
Window Length: 36
Eye Window: __________________XXXX__________________
Uplink 17:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 18:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 19:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 20:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 21:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 22:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 23:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 24:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 28:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 29:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 30:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 31:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
13:23:11:setup_element:INFO: Performing Elink synchronization
13:23:11:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:23:11:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:23:11:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
13:23:11:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
13:23:11:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
13:23:11:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:23:11:ST3_emu:INFO: Number of chips: 8
13:23:11:ST3_emu:INFO: Chip address: 0x0
13:23:11:ST3_emu:INFO: Chip address: 0x1
13:23:11:ST3_emu:INFO: Chip address: 0x2
13:23:11:ST3_emu:INFO: Chip address: 0x3
13:23:11:ST3_emu:INFO: Chip address: 0x4
13:23:11:ST3_emu:INFO: Chip address: 0x5
13:23:11:ST3_emu:INFO: Chip address: 0x6
13:23:11:ST3_emu:INFO: Chip address: 0x7
13:23:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:23:12:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 44.1 | 1141.9
13:23:12:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 31.4 | 1189.2
13:23:12:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 15.6 | 1242.0
13:23:13:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 37.7 | 1177.4
13:23:13:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 18.7 | 1242.0
13:23:13:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1183.3
13:23:13:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 40.9 | 1153.7
13:23:14:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 6.1 | 1288.7
13:23:14:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:23:18:ST3_smx:INFO: chip: 0-0 44.073563 C 1129.995435 mV
13:23:18:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:23:18:ST3_smx:INFO: Electrons
13:23:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:20:ST3_smx:INFO: ----> Checking Analog response
13:23:20:ST3_smx:INFO: ----> Checking broken channels
13:23:20:ST3_smx:INFO: Total # broken ch: 2
13:23:20:ST3_smx:INFO: List FAST: [78, 94]
13:23:20:ST3_smx:INFO: List SLOW: []
13:23:20:ST3_smx:INFO: Holes
13:23:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:22:ST3_smx:INFO: ----> Checking Analog response
13:23:22:ST3_smx:INFO: ----> Checking broken channels
13:23:23:ST3_smx:INFO: Total # broken ch: 2
13:23:23:ST3_smx:INFO: List FAST: [78, 94]
13:23:23:ST3_smx:INFO: List SLOW: []
13:23:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:23:23:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1130.0
13:23:23:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 31.4 | 1189.2
13:23:23:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 15.6 | 1242.0
13:23:24:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 37.7 | 1171.5
13:23:24:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 15.6 | 1242.0
13:23:24:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1183.3
13:23:24:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 40.9 | 1153.7
13:23:24:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 6.1 | 1288.7
13:23:25:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:23:29:ST3_smx:INFO: chip: 0-1 31.389742 C 1177.390875 mV
13:23:29:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:23:29:ST3_smx:INFO: Electrons
13:23:29:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:31:ST3_smx:INFO: ----> Checking Analog response
13:23:31:ST3_smx:INFO: ----> Checking broken channels
13:23:31:ST3_smx:INFO: Total # broken ch: 4
13:23:31:ST3_smx:INFO: List FAST: [17, 33, 69, 85]
13:23:31:ST3_smx:INFO: List SLOW: []
13:23:31:ST3_smx:INFO: Holes
13:23:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:33:ST3_smx:INFO: ----> Checking Analog response
13:23:33:ST3_smx:INFO: ----> Checking broken channels
13:23:34:ST3_smx:INFO: Total # broken ch: 4
13:23:34:ST3_smx:INFO: List FAST: [17, 33, 69, 85]
13:23:34:ST3_smx:INFO: List SLOW: []
13:23:34:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:23:34:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1130.0
13:23:34:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 31.4 | 1177.4
13:23:34:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 15.6 | 1242.0
13:23:35:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 37.7 | 1171.5
13:23:35:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 18.7 | 1242.0
13:23:35:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1177.4
13:23:35:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 40.9 | 1153.7
13:23:36:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 6.1 | 1288.7
13:23:36:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:23:40:ST3_smx:INFO: chip: 0-2 18.745682 C 1224.468235 mV
13:23:40:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:23:40:ST3_smx:INFO: Electrons
13:23:40:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:42:ST3_smx:INFO: ----> Checking Analog response
13:23:42:ST3_smx:INFO: ----> Checking broken channels
13:23:42:ST3_smx:INFO: Total # broken ch: 2
13:23:42:ST3_smx:INFO: List FAST: [18]
13:23:42:ST3_smx:INFO: List SLOW: [13]
13:23:42:ST3_smx:INFO: Holes
13:23:42:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:44:ST3_smx:INFO: ----> Checking Analog response
13:23:44:ST3_smx:INFO: ----> Checking broken channels
13:23:45:ST3_smx:INFO: Total # broken ch: 2
13:23:45:ST3_smx:INFO: List FAST: [18]
13:23:45:ST3_smx:INFO: List SLOW: [13]
13:23:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:23:45:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1130.0
13:23:45:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 31.4 | 1177.4
13:23:45:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 21.9 | 1218.6
13:23:46:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 37.7 | 1171.5
13:23:46:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 18.7 | 1242.0
13:23:46:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1177.4
13:23:46:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 40.9 | 1153.7
13:23:46:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 6.1 | 1288.7
13:23:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:23:51:ST3_smx:INFO: chip: 0-3 31.389742 C 1183.292940 mV
13:23:51:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:23:51:ST3_smx:INFO: Electrons
13:23:51:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:53:ST3_smx:INFO: ----> Checking Analog response
13:23:53:ST3_smx:INFO: ----> Checking broken channels
13:23:53:ST3_smx:INFO: Total # broken ch: 5
13:23:53:ST3_smx:INFO: List FAST: [1, 96, 112, 116]
13:23:53:ST3_smx:INFO: List SLOW: [1]
13:23:53:ST3_smx:INFO: Holes
13:23:53:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:23:55:ST3_smx:INFO: ----> Checking Analog response
13:23:55:ST3_smx:INFO: ----> Checking broken channels
13:23:55:ST3_smx:INFO: Total # broken ch: 5
13:23:55:ST3_smx:INFO: List FAST: [1, 96, 112, 116]
13:23:55:ST3_smx:INFO: List SLOW: [1]
13:23:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:23:56:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1130.0
13:23:56:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 31.4 | 1171.5
13:23:56:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 21.9 | 1218.6
13:23:56:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
13:23:56:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 18.7 | 1242.0
13:23:57:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1177.4
13:23:57:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 40.9 | 1153.7
13:23:57:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 6.1 | 1288.7
13:23:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:24:01:ST3_smx:INFO: chip: 0-4 28.225000 C 1195.082160 mV
13:24:01:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:24:01:ST3_smx:INFO: Electrons
13:24:01:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:03:ST3_smx:INFO: ----> Checking Analog response
13:24:03:ST3_smx:INFO: ----> Checking broken channels
13:24:03:ST3_smx:INFO: Total # broken ch: 2
13:24:03:ST3_smx:INFO: List FAST: [12, 106]
13:24:03:ST3_smx:INFO: List SLOW: []
13:24:03:ST3_smx:INFO: Holes
13:24:03:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:05:ST3_smx:INFO: ----> Checking Analog response
13:24:05:ST3_smx:INFO: ----> Checking broken channels
13:24:06:ST3_smx:INFO: Total # broken ch: 2
13:24:06:ST3_smx:INFO: List FAST: [12, 106]
13:24:06:ST3_smx:INFO: List SLOW: []
13:24:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:24:06:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1124.0
13:24:06:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 34.6 | 1177.4
13:24:06:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 21.9 | 1212.7
13:24:07:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
13:24:07:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 28.2 | 1183.3
13:24:07:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 37.7 | 1177.4
13:24:07:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 40.9 | 1153.7
13:24:08:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1282.9
13:24:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:24:11:ST3_smx:INFO: chip: 0-5 40.898880 C 1159.654860 mV
13:24:11:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:24:11:ST3_smx:INFO: Electrons
13:24:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:13:ST3_smx:INFO: ----> Checking Analog response
13:24:13:ST3_smx:INFO: ----> Checking broken channels
13:24:14:ST3_smx:INFO: Total # broken ch: 1
13:24:14:ST3_smx:INFO: List FAST: [102]
13:24:14:ST3_smx:INFO: List SLOW: []
13:24:14:ST3_smx:INFO: Holes
13:24:14:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:16:ST3_smx:INFO: ----> Checking Analog response
13:24:16:ST3_smx:INFO: ----> Checking broken channels
13:24:16:ST3_smx:INFO: Total # broken ch: 1
13:24:16:ST3_smx:INFO: List FAST: [102]
13:24:16:ST3_smx:INFO: List SLOW: []
13:24:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:24:16:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1124.0
13:24:16:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 34.6 | 1171.5
13:24:17:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 21.9 | 1218.6
13:24:17:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
13:24:17:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 31.4 | 1189.2
13:24:17:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 40.9 | 1159.7
13:24:18:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 44.1 | 1153.7
13:24:18:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1288.7
13:24:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:24:22:ST3_smx:INFO: chip: 0-6 34.556970 C 1171.483840 mV
13:24:22:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:24:22:ST3_smx:INFO: Electrons
13:24:22:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:24:ST3_smx:INFO: ----> Checking Analog response
13:24:24:ST3_smx:INFO: ----> Checking broken channels
13:24:24:ST3_smx:INFO: Total # broken ch: 3
13:24:24:ST3_smx:INFO: List FAST: [13, 52]
13:24:24:ST3_smx:INFO: List SLOW: [13]
13:24:24:ST3_smx:INFO: Holes
13:24:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:26:ST3_smx:INFO: ----> Checking Analog response
13:24:26:ST3_smx:INFO: ----> Checking broken channels
13:24:26:ST3_smx:INFO: Total # broken ch: 3
13:24:26:ST3_smx:INFO: List FAST: [13, 52]
13:24:26:ST3_smx:INFO: List SLOW: [13]
13:24:26:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:24:26:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1124.0
13:24:26:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 34.6 | 1171.5
13:24:27:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 21.9 | 1212.7
13:24:27:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
13:24:27:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 28.2 | 1189.2
13:24:27:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 44.1 | 1159.7
13:24:28:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 37.7 | 1165.6
13:24:28:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 9.3 | 1288.7
13:24:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:24:32:ST3_smx:INFO: chip: 0-7 15.590880 C 1242.040240 mV
13:24:32:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
13:24:32:ST3_smx:INFO: Electrons
13:24:32:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:34:ST3_smx:INFO: ----> Checking Analog response
13:24:34:ST3_smx:INFO: ----> Checking broken channels
13:24:34:ST3_smx:INFO: Total # broken ch: 1
13:24:34:ST3_smx:INFO: List FAST: [20]
13:24:34:ST3_smx:INFO: List SLOW: []
13:24:34:ST3_smx:INFO: Holes
13:24:34:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
13:24:36:ST3_smx:INFO: ----> Checking Analog response
13:24:36:ST3_smx:INFO: ----> Checking broken channels
13:24:36:ST3_smx:INFO: Total # broken ch: 1
13:24:36:ST3_smx:INFO: List FAST: [20]
13:24:36:ST3_smx:INFO: List SLOW: []
13:24:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:24:37:febtest:INFO: 0-0 | XA-000-08-002-000-007-145-11 | 47.3 | 1124.0
13:24:37:febtest:INFO: 0-1 | XA-000-08-002-000-007-135-12 | 34.6 | 1171.5
13:24:37:febtest:INFO: 0-2 | XA-000-08-002-000-008-077-07 | 21.9 | 1218.6
13:24:37:febtest:INFO: 0-3 | XA-000-08-002-000-007-133-12 | 34.6 | 1177.4
13:24:38:febtest:INFO: 0-4 | XA-000-08-002-000-007-149-11 | 28.2 | 1189.2
13:24:38:febtest:INFO: 0-5 | XA-000-08-002-000-007-141-12 | 44.1 | 1159.7
13:24:38:febtest:INFO: 0-6 | XA-000-08-002-000-008-083-00 | 37.7 | 1165.6
13:24:38:febtest:INFO: 0-7 | XA-000-08-002-000-007-139-12 | 18.7 | 1236.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_07_24-13_22_59', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-139-12', 'FUSED_ID': 6359364699116566716, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 1, 'N_BROKEN_FAST': '[20]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 1, 'P_BROKEN_FAST': '[20]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.5510', '1.846', '2.5930', '7.000', '1.5270', '7.000', '1.5270'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
13:25:00:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1004/A//TestDate_2023_07_24-13_22_59/