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FEB_1005 03.08.23 15:13:26
Info
15:13:25:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:13:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:13:26:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:13:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:13:27:febtest:INFO: Tsting FEB with SN 1005
15:13:28:smx_tester:INFO: Scanning setup
15:13:28:elinks:INFO: Disabling clock on downlink 0
15:13:28:elinks:INFO: Disabling clock on downlink 1
15:13:28:elinks:INFO: Disabling clock on downlink 2
15:13:28:elinks:INFO: Disabling clock on downlink 3
15:13:28:elinks:INFO: Disabling clock on downlink 4
15:13:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:13:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:13:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:13:28:elinks:INFO: Disabling clock on downlink 0
15:13:28:elinks:INFO: Disabling clock on downlink 1
15:13:28:elinks:INFO: Disabling clock on downlink 2
15:13:28:elinks:INFO: Disabling clock on downlink 3
15:13:28:elinks:INFO: Disabling clock on downlink 4
15:13:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:13:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:13:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:13:28:elinks:INFO: Disabling clock on downlink 0
15:13:28:elinks:INFO: Disabling clock on downlink 1
15:13:28:elinks:INFO: Disabling clock on downlink 2
15:13:28:elinks:INFO: Disabling clock on downlink 3
15:13:28:elinks:INFO: Disabling clock on downlink 4
15:13:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:13:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:13:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:13:28:elinks:INFO: Disabling clock on downlink 0
15:13:28:elinks:INFO: Disabling clock on downlink 1
15:13:28:elinks:INFO: Disabling clock on downlink 2
15:13:28:elinks:INFO: Disabling clock on downlink 3
15:13:28:elinks:INFO: Disabling clock on downlink 4
15:13:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:13:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
15:13:29:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
15:13:29:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:13:29:elinks:INFO: Disabling clock on downlink 0
15:13:29:elinks:INFO: Disabling clock on downlink 1
15:13:29:elinks:INFO: Disabling clock on downlink 2
15:13:29:elinks:INFO: Disabling clock on downlink 3
15:13:29:elinks:INFO: Disabling clock on downlink 4
15:13:29:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:13:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:13:29:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:13:29:setup_element:INFO: Scanning clock phase
15:13:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:13:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:13:29:setup_element:INFO: Clock phase scan results for group 0, downlink 3
15:13:29:setup_element:INFO: Eye window for uplink 16: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 17: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 18: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:13:29:setup_element:INFO: Eye window for uplink 19: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:13:29:setup_element:INFO: Eye window for uplink 20: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:13:29:setup_element:INFO: Eye window for uplink 21: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:13:29:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:13:29:setup_element:INFO: Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
15:13:29:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
15:13:29:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
15:13:29:setup_element:INFO: Eye window for uplink 28: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 29: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:13:29:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
15:13:29:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 3
15:13:29:setup_element:INFO: Scanning data phases
15:13:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:13:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:13:35:setup_element:INFO: Data phase scan results for group 0, downlink 3
15:13:35:setup_element:INFO: Eye window for uplink 16: ________________XXXX____________________
Data delay found: 37
15:13:35:setup_element:INFO: Eye window for uplink 17: ____________XXXX________________________
Data delay found: 33
15:13:35:setup_element:INFO: Eye window for uplink 18: ___________XXXXXX_______________________
Data delay found: 33
15:13:35:setup_element:INFO: Eye window for uplink 19: _________XXXXX__________________________
Data delay found: 31
15:13:35:setup_element:INFO: Eye window for uplink 20: ________XXXXX___________________________
Data delay found: 30
15:13:35:setup_element:INFO: Eye window for uplink 21: ______XXXXXX____________________________
Data delay found: 28
15:13:35:setup_element:INFO: Eye window for uplink 22: ______XXXX______________________________
Data delay found: 27
15:13:35:setup_element:INFO: Eye window for uplink 23: ___XXXX_________________________________
Data delay found: 24
15:13:35:setup_element:INFO: Eye window for uplink 24: XX__________________________________XXXX
Data delay found: 18
15:13:35:setup_element:INFO: Eye window for uplink 25: _XXXX___________________________________
Data delay found: 22
15:13:35:setup_element:INFO: Eye window for uplink 26: _________________________________XXXXX__
Data delay found: 15
15:13:35:setup_element:INFO: Eye window for uplink 27: XXX___________________________________XX
Data delay found: 20
15:13:35:setup_element:INFO: Eye window for uplink 28: XXX___________________________________XX
Data delay found: 20
15:13:35:setup_element:INFO: Eye window for uplink 29: XXXXX__________________________________X
Data delay found: 21
15:13:35:setup_element:INFO: Eye window for uplink 30: XX__________________________________XXXX
Data delay found: 18
15:13:35:setup_element:INFO: Eye window for uplink 31: XX________________________________XXXXX_
Data delay found: 17
15:13:35:setup_element:INFO: Setting the data phase to 37 for uplink 16
15:13:35:setup_element:INFO: Setting the data phase to 33 for uplink 17
15:13:35:setup_element:INFO: Setting the data phase to 33 for uplink 18
15:13:35:setup_element:INFO: Setting the data phase to 31 for uplink 19
15:13:35:setup_element:INFO: Setting the data phase to 30 for uplink 20
15:13:35:setup_element:INFO: Setting the data phase to 28 for uplink 21
15:13:35:setup_element:INFO: Setting the data phase to 27 for uplink 22
15:13:35:setup_element:INFO: Setting the data phase to 24 for uplink 23
15:13:35:setup_element:INFO: Setting the data phase to 18 for uplink 24
15:13:35:setup_element:INFO: Setting the data phase to 22 for uplink 25
15:13:35:setup_element:INFO: Setting the data phase to 15 for uplink 26
15:13:35:setup_element:INFO: Setting the data phase to 20 for uplink 27
15:13:35:setup_element:INFO: Setting the data phase to 20 for uplink 28
15:13:35:setup_element:INFO: Setting the data phase to 21 for uplink 29
15:13:35:setup_element:INFO: Setting the data phase to 18 for uplink 30
15:13:35:setup_element:INFO: Setting the data phase to 17 for uplink 31
15:13:35:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXX_____
Uplink 17: ____________________________________________________________________XXXXXXX_____
Uplink 18: ___________________________________________________________________XXXXXXXX_____
Uplink 19: ___________________________________________________________________XXXXXXXX_____
Uplink 20: ___________________________________________________________________XXXXXXXX_____
Uplink 21: ___________________________________________________________________XXXXXXXX_____
Uplink 22: ____________________________________________________________________XXXXXXXX____
Uplink 23: ____________________________________________________________________XXXXXXXX____
Uplink 24: ___________________________________________________________________XXXXXXXX_____
Uplink 25: ___________________________________________________________________XXXXXXXX_____
Uplink 26: __________________________________________________________________XXXXXXX_______
Uplink 27: __________________________________________________________________XXXXXXX_______
Uplink 28: ____________________________________________________________________XXXXXXX_____
Uplink 29: ____________________________________________________________________XXXXXXX_____
Uplink 30: ____________________________________________________________________XXXXXXX_____
Uplink 31: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 36
Eye Window: ________________XXXX____________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 21:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 22:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 23:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 24:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 25:
Optimal Phase: 22
Window Length: 36
Eye Window: _XXXX___________________________________
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 28:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 29:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 30:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 31:
Optimal Phase: 17
Window Length: 32
Eye Window: XX________________________________XXXXX_
]
15:13:35:setup_element:INFO: Beginning SMX ASICs map scan
15:13:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:13:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:13:35:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
15:13:35:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
15:13:35:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:13:35:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
15:13:35:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
15:13:35:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
15:13:35:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
15:13:35:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
15:13:35:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
15:13:36:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
15:13:36:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
15:13:36:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
15:13:36:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
15:13:36:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
15:13:36:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
15:13:36:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
15:13:36:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
15:13:36:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
15:13:36:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
15:13:38:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXX_____
Uplink 17: ____________________________________________________________________XXXXXXX_____
Uplink 18: ___________________________________________________________________XXXXXXXX_____
Uplink 19: ___________________________________________________________________XXXXXXXX_____
Uplink 20: ___________________________________________________________________XXXXXXXX_____
Uplink 21: ___________________________________________________________________XXXXXXXX_____
Uplink 22: ____________________________________________________________________XXXXXXXX____
Uplink 23: ____________________________________________________________________XXXXXXXX____
Uplink 24: ___________________________________________________________________XXXXXXXX_____
Uplink 25: ___________________________________________________________________XXXXXXXX_____
Uplink 26: __________________________________________________________________XXXXXXX_______
Uplink 27: __________________________________________________________________XXXXXXX_______
Uplink 28: ____________________________________________________________________XXXXXXX_____
Uplink 29: ____________________________________________________________________XXXXXXX_____
Uplink 30: ____________________________________________________________________XXXXXXX_____
Uplink 31: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 36
Eye Window: ________________XXXX____________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 21:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 22:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 23:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 24:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 25:
Optimal Phase: 22
Window Length: 36
Eye Window: _XXXX___________________________________
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 28:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 29:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 30:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 31:
Optimal Phase: 17
Window Length: 32
Eye Window: XX________________________________XXXXX_
15:13:38:setup_element:INFO: Performing Elink synchronization
15:13:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:13:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
15:13:38:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
15:13:38:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
15:13:38:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
15:13:38:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:13:38:ST3_emu:INFO: Number of chips: 8
15:13:38:ST3_emu:INFO: Chip address: 0x0
15:13:38:ST3_emu:INFO: Chip address: 0x1
15:13:38:ST3_emu:INFO: Chip address: 0x2
15:13:38:ST3_emu:INFO: Chip address: 0x3
15:13:38:ST3_emu:INFO: Chip address: 0x4
15:13:38:ST3_emu:INFO: Chip address: 0x5
15:13:38:ST3_emu:INFO: Chip address: 0x6
15:13:38:ST3_emu:INFO: Chip address: 0x7
15:13:39:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:13:39:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 34.6 | 1195.1
15:13:39:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 21.9 | 1242.0
15:13:39:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 40.9 | 1177.4
15:13:39:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 21.9 | 1242.0
15:13:40:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 18.7 | 1253.7
15:13:40:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 50.4 | 1135.9
15:13:40:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 28.2 | 1224.5
15:13:40:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 37.7 | 1195.1
15:13:40:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:13:44:ST3_smx:INFO: chip: 0-0 34.556970 C 1189.190035 mV
15:13:44:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:13:44:ST3_smx:INFO: Electrons
15:13:44:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:13:46:ST3_smx:INFO: ----> Checking Analog response
15:13:46:ST3_smx:INFO: ----> Checking broken channels
15:13:46:ST3_smx:INFO: Total # broken ch: 0
15:13:46:ST3_smx:INFO: List FAST: []
15:13:46:ST3_smx:INFO: List SLOW: []
15:13:46:ST3_smx:INFO: Holes
15:13:46:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:13:48:ST3_smx:INFO: ----> Checking Analog response
15:13:48:ST3_smx:INFO: ----> Checking broken channels
15:13:49:ST3_smx:INFO: Total # broken ch: 0
15:13:49:ST3_smx:INFO: List FAST: []
15:13:49:ST3_smx:INFO: List SLOW: []
15:13:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:13:49:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 34.6 | 1183.3
15:13:49:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 21.9 | 1242.0
15:13:49:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 40.9 | 1177.4
15:13:50:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 18.7 | 1242.0
15:13:50:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 18.7 | 1247.9
15:13:50:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 50.4 | 1135.9
15:13:50:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 28.2 | 1218.6
15:13:50:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 37.7 | 1195.1
15:13:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:13:55:ST3_smx:INFO: chip: 0-1 28.225000 C 1206.851500 mV
15:13:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:13:55:ST3_smx:INFO: Electrons
15:13:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:13:57:ST3_smx:INFO: ----> Checking Analog response
15:13:57:ST3_smx:INFO: ----> Checking broken channels
15:13:57:ST3_smx:INFO: Total # broken ch: 0
15:13:57:ST3_smx:INFO: List FAST: []
15:13:57:ST3_smx:INFO: List SLOW: []
15:13:57:ST3_smx:INFO: Holes
15:13:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:13:59:ST3_smx:INFO: ----> Checking Analog response
15:13:59:ST3_smx:INFO: ----> Checking broken channels
15:13:59:ST3_smx:INFO: Total # broken ch: 0
15:13:59:ST3_smx:INFO: List FAST: []
15:13:59:ST3_smx:INFO: List SLOW: []
15:13:59:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:13:59:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 34.6 | 1183.3
15:14:00:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 28.2 | 1206.9
15:14:00:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 40.9 | 1177.4
15:14:00:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 21.9 | 1242.0
15:14:00:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 18.7 | 1247.9
15:14:01:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 50.4 | 1135.9
15:14:01:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 28.2 | 1218.6
15:14:01:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 37.7 | 1195.1
15:14:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:14:05:ST3_smx:INFO: chip: 0-2 37.726682 C 1177.390875 mV
15:14:05:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:14:05:ST3_smx:INFO: Electrons
15:14:05:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:07:ST3_smx:INFO: ----> Checking Analog response
15:14:07:ST3_smx:INFO: ----> Checking broken channels
15:14:07:ST3_smx:INFO: Total # broken ch: 0
15:14:07:ST3_smx:INFO: List FAST: []
15:14:07:ST3_smx:INFO: List SLOW: []
15:14:07:ST3_smx:INFO: Holes
15:14:07:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:09:ST3_smx:INFO: ----> Checking Analog response
15:14:09:ST3_smx:INFO: ----> Checking broken channels
15:14:10:ST3_smx:INFO: Total # broken ch: 0
15:14:10:ST3_smx:INFO: List FAST: []
15:14:10:ST3_smx:INFO: List SLOW: []
15:14:10:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:14:10:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 34.6 | 1183.3
15:14:10:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 28.2 | 1206.9
15:14:10:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 37.7 | 1177.4
15:14:11:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 21.9 | 1242.0
15:14:11:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 18.7 | 1247.9
15:14:11:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 50.4 | 1135.9
15:14:11:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 28.2 | 1218.6
15:14:11:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 37.7 | 1195.1
15:14:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:14:15:ST3_smx:INFO: chip: 0-3 28.225000 C 1200.969315 mV
15:14:15:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:14:15:ST3_smx:INFO: Electrons
15:14:15:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:17:ST3_smx:INFO: ----> Checking Analog response
15:14:17:ST3_smx:INFO: ----> Checking broken channels
15:14:18:ST3_smx:INFO: Total # broken ch: 0
15:14:18:ST3_smx:INFO: List FAST: []
15:14:18:ST3_smx:INFO: List SLOW: []
15:14:18:ST3_smx:INFO: Holes
15:14:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:20:ST3_smx:INFO: ----> Checking Analog response
15:14:20:ST3_smx:INFO: ----> Checking broken channels
15:14:20:ST3_smx:INFO: Total # broken ch: 0
15:14:20:ST3_smx:INFO: List FAST: []
15:14:20:ST3_smx:INFO: List SLOW: []
15:14:20:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:14:20:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 37.7 | 1183.3
15:14:20:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 28.2 | 1206.9
15:14:21:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 40.9 | 1177.4
15:14:21:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 34.6 | 1195.1
15:14:21:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 21.9 | 1247.9
15:14:21:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 53.6 | 1130.0
15:14:22:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 31.4 | 1218.6
15:14:22:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 40.9 | 1189.2
15:14:22:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:14:26:ST3_smx:INFO: chip: 0-4 31.389742 C 1212.728715 mV
15:14:26:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:14:26:ST3_smx:INFO: Electrons
15:14:26:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:28:ST3_smx:INFO: ----> Checking Analog response
15:14:28:ST3_smx:INFO: ----> Checking broken channels
15:14:28:ST3_smx:INFO: Total # broken ch: 0
15:14:28:ST3_smx:INFO: List FAST: []
15:14:28:ST3_smx:INFO: List SLOW: []
15:14:28:ST3_smx:INFO: Holes
15:14:28:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:30:ST3_smx:INFO: ----> Checking Analog response
15:14:30:ST3_smx:INFO: ----> Checking broken channels
15:14:31:ST3_smx:INFO: Total # broken ch: 0
15:14:31:ST3_smx:INFO: List FAST: []
15:14:31:ST3_smx:INFO: List SLOW: []
15:14:31:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:14:31:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 40.9 | 1183.3
15:14:31:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 34.6 | 1206.9
15:14:31:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 47.3 | 1171.5
15:14:31:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 37.7 | 1195.1
15:14:32:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 34.6 | 1212.7
15:14:32:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 60.0 | 1130.0
15:14:32:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 37.7 | 1212.7
15:14:32:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 44.1 | 1189.2
15:14:33:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:14:36:ST3_smx:INFO: chip: 0-5 53.612520 C 1135.937260 mV
15:14:36:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:14:36:ST3_smx:INFO: Electrons
15:14:37:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:39:ST3_smx:INFO: ----> Checking Analog response
15:14:39:ST3_smx:INFO: ----> Checking broken channels
15:14:39:ST3_smx:INFO: Total # broken ch: 0
15:14:39:ST3_smx:INFO: List FAST: []
15:14:39:ST3_smx:INFO: List SLOW: []
15:14:39:ST3_smx:INFO: Holes
15:14:39:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:41:ST3_smx:INFO: ----> Checking Analog response
15:14:41:ST3_smx:INFO: ----> Checking broken channels
15:14:41:ST3_smx:INFO: Total # broken ch: 0
15:14:41:ST3_smx:INFO: List FAST: []
15:14:41:ST3_smx:INFO: List SLOW: []
15:14:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:14:41:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 37.7 | 1183.3
15:14:42:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 34.6 | 1201.0
15:14:42:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 44.1 | 1171.5
15:14:42:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 34.6 | 1195.1
15:14:42:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 31.4 | 1212.7
15:14:43:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 53.6 | 1135.9
15:14:43:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 34.6 | 1212.7
15:14:43:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 40.9 | 1189.2
15:14:43:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:14:47:ST3_smx:INFO: chip: 0-6 28.225000 C 1212.728715 mV
15:14:47:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:14:47:ST3_smx:INFO: Electrons
15:14:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:49:ST3_smx:INFO: ----> Checking Analog response
15:14:49:ST3_smx:INFO: ----> Checking broken channels
15:14:49:ST3_smx:INFO: Total # broken ch: 0
15:14:49:ST3_smx:INFO: List FAST: []
15:14:49:ST3_smx:INFO: List SLOW: []
15:14:49:ST3_smx:INFO: Holes
15:14:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:14:51:ST3_smx:INFO: ----> Checking Analog response
15:14:51:ST3_smx:INFO: ----> Checking broken channels
15:14:52:ST3_smx:INFO: Total # broken ch: 0
15:14:52:ST3_smx:INFO: List FAST: []
15:14:52:ST3_smx:INFO: List SLOW: []
15:14:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:14:52:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 37.7 | 1177.4
15:14:52:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 31.4 | 1206.9
15:14:52:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 40.9 | 1171.5
15:14:53:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 31.4 | 1195.1
15:14:53:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 28.2 | 1212.7
15:14:53:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 50.4 | 1135.9
15:14:53:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 31.4 | 1206.9
15:14:53:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 37.7 | 1189.2
15:14:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:14:58:ST3_smx:INFO: chip: 0-7 34.556970 C 1177.390875 mV
15:14:58:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:14:58:ST3_smx:INFO: Electrons
15:14:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:15:00:ST3_smx:INFO: ----> Checking Analog response
15:15:00:ST3_smx:INFO: ----> Checking broken channels
15:15:00:ST3_smx:INFO: Total # broken ch: 0
15:15:00:ST3_smx:INFO: List FAST: []
15:15:00:ST3_smx:INFO: List SLOW: []
15:15:00:ST3_smx:INFO: Holes
15:15:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
15:15:02:ST3_smx:INFO: ----> Checking Analog response
15:15:02:ST3_smx:INFO: ----> Checking broken channels
15:15:02:ST3_smx:INFO: Total # broken ch: 0
15:15:02:ST3_smx:INFO: List FAST: []
15:15:02:ST3_smx:INFO: List SLOW: []
15:15:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:15:03:febtest:INFO: 0-0 | XA-000-08-002-002-007-089-13 | 37.7 | 1183.3
15:15:03:febtest:INFO: 0-1 | XA-000-08-002-002-006-168-06 | 31.4 | 1201.0
15:15:03:febtest:INFO: 0-2 | XA-000-08-002-002-007-090-13 | 40.9 | 1177.4
15:15:03:febtest:INFO: 0-3 | XA-000-08-002-002-007-094-13 | 31.4 | 1189.2
15:15:03:febtest:INFO: 0-4 | XA-000-08-002-002-007-088-13 | 28.2 | 1212.7
15:15:04:febtest:INFO: 0-5 | XA-000-08-002-002-007-091-13 | 50.4 | 1130.0
15:15:04:febtest:INFO: 0-6 | XA-000-08-002-002-007-092-13 | 28.2 | 1212.7
15:15:04:febtest:INFO: 0-7 | XA-000-08-002-002-007-093-13 | 37.7 | 1177.4
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_03-15_13_26', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-002-007-093-13', 'FUSED_ID': 6359364699118663133, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.6200', '1.846', '2.0630', '7.000', '1.5440', '7.000', '1.5440'], 'VI_aInit': ['2.450', '2.0290', '1.850', '1.4980', '7.000', '1.5310', '7.000', '1.5310'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
15:15:09:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1005/A//TestDate_2023_08_03-15_13_26/