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FEB_1007 03.08.23 11:22:34
TextEdit.txt
11:21:09:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Robert V.;
11:21:09:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
11:21:11:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Robert V.;
11:22:32:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:22:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:22:34:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:22:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:22:35:febtest:INFO: Tsting FEB with SN 1007
11:22:36:smx_tester:INFO: Scanning setup
11:22:36:elinks:INFO: Disabling clock on downlink 0
11:22:36:elinks:INFO: Disabling clock on downlink 1
11:22:36:elinks:INFO: Disabling clock on downlink 2
11:22:36:elinks:INFO: Disabling clock on downlink 3
11:22:36:elinks:INFO: Disabling clock on downlink 4
11:22:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:22:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:22:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:22:36:elinks:INFO: Disabling clock on downlink 0
11:22:36:elinks:INFO: Disabling clock on downlink 1
11:22:36:elinks:INFO: Disabling clock on downlink 2
11:22:36:elinks:INFO: Disabling clock on downlink 3
11:22:36:elinks:INFO: Disabling clock on downlink 4
11:22:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:22:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:22:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:22:36:elinks:INFO: Disabling clock on downlink 0
11:22:36:elinks:INFO: Disabling clock on downlink 1
11:22:36:elinks:INFO: Disabling clock on downlink 2
11:22:36:elinks:INFO: Disabling clock on downlink 3
11:22:36:elinks:INFO: Disabling clock on downlink 4
11:22:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:22:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:22:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:22:36:elinks:INFO: Disabling clock on downlink 0
11:22:36:elinks:INFO: Disabling clock on downlink 1
11:22:36:elinks:INFO: Disabling clock on downlink 2
11:22:36:elinks:INFO: Disabling clock on downlink 3
11:22:36:elinks:INFO: Disabling clock on downlink 4
11:22:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:22:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
11:22:36:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
11:22:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:22:36:elinks:INFO: Disabling clock on downlink 0
11:22:36:elinks:INFO: Disabling clock on downlink 1
11:22:36:elinks:INFO: Disabling clock on downlink 2
11:22:36:elinks:INFO: Disabling clock on downlink 3
11:22:36:elinks:INFO: Disabling clock on downlink 4
11:22:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:22:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:22:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:22:37:setup_element:INFO: Scanning clock phase
11:22:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:22:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:22:37:setup_element:INFO: Clock phase scan results for group 0, downlink 3
11:22:37:setup_element:INFO: Eye window for uplink 16: ____________________________________________________________________XXXXXX______
Clock Delay: 30
11:22:37:setup_element:INFO: Eye window for uplink 17: ____________________________________________________________________XXXXXX______
Clock Delay: 30
11:22:37:setup_element:INFO: Eye window for uplink 18: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:22:37:setup_element:INFO: Eye window for uplink 19: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:22:37:setup_element:INFO: Eye window for uplink 20: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 21: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXX______
Clock Delay: 30
11:22:37:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXX______
Clock Delay: 30
11:22:37:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
11:22:37:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 28: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 29: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXXXX_______
Clock Delay: 29
11:22:37:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXXXX_______
Clock Delay: 29
11:22:37:setup_element:INFO: Setting the clock phase to 29 for group 0, downlink 3
11:22:37:setup_element:INFO: Scanning data phases
11:22:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:22:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:22:42:setup_element:INFO: Data phase scan results for group 0, downlink 3
11:22:42:setup_element:INFO: Eye window for uplink 16: ________________XXXX____________________
Data delay found: 37
11:22:42:setup_element:INFO: Eye window for uplink 17: ____________XXXX________________________
Data delay found: 33
11:22:42:setup_element:INFO: Eye window for uplink 18: ____________XXXXX_______________________
Data delay found: 34
11:22:42:setup_element:INFO: Eye window for uplink 19: _________XXXXX__________________________
Data delay found: 31
11:22:42:setup_element:INFO: Eye window for uplink 20: ________XXXX____________________________
Data delay found: 29
11:22:42:setup_element:INFO: Eye window for uplink 21: ______XXXXX_____________________________
Data delay found: 28
11:22:42:setup_element:INFO: Eye window for uplink 22: ______XXXX______________________________
Data delay found: 27
11:22:42:setup_element:INFO: Eye window for uplink 23: ___XXXXX________________________________
Data delay found: 25
11:22:42:setup_element:INFO: Eye window for uplink 25: XXX___________________________________XX
Data delay found: 20
11:22:42:setup_element:INFO: Eye window for uplink 26: __________________________________XXXX__
Data delay found: 15
11:22:42:setup_element:INFO: Eye window for uplink 27: XXXX_________________________________XXX
Data delay found: 20
11:22:42:setup_element:INFO: Eye window for uplink 28: XXX__________________________________XXX
Data delay found: 19
11:22:42:setup_element:INFO: Eye window for uplink 29: XXXXX__________________________________X
Data delay found: 21
11:22:42:setup_element:INFO: Eye window for uplink 30: XXXX________________________________XXXX
Data delay found: 19
11:22:42:setup_element:INFO: Eye window for uplink 31: XX_______________________________XXXXXX_
Data delay found: 17
11:22:42:setup_element:INFO: Setting the data phase to 37 for uplink 16
11:22:42:setup_element:INFO: Setting the data phase to 33 for uplink 17
11:22:42:setup_element:INFO: Setting the data phase to 34 for uplink 18
11:22:42:setup_element:INFO: Setting the data phase to 31 for uplink 19
11:22:42:setup_element:INFO: Setting the data phase to 29 for uplink 20
11:22:42:setup_element:INFO: Setting the data phase to 28 for uplink 21
11:22:42:setup_element:INFO: Setting the data phase to 27 for uplink 22
11:22:42:setup_element:INFO: Setting the data phase to 25 for uplink 23
11:22:42:setup_element:INFO: Setting the data phase to 20 for uplink 25
11:22:42:setup_element:INFO: Setting the data phase to 15 for uplink 26
11:22:42:setup_element:INFO: Setting the data phase to 20 for uplink 27
11:22:42:setup_element:INFO: Setting the data phase to 19 for uplink 28
11:22:42:setup_element:INFO: Setting the data phase to 21 for uplink 29
11:22:42:setup_element:INFO: Setting the data phase to 19 for uplink 30
11:22:42:setup_element:INFO: Setting the data phase to 17 for uplink 31
11:22:42:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 71
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXX______
Uplink 17: ____________________________________________________________________XXXXXX______
Uplink 18: ___________________________________________________________________XXXXXXX______
Uplink 19: ___________________________________________________________________XXXXXXX______
Uplink 20: __________________________________________________________________XXXXXXXX______
Uplink 21: __________________________________________________________________XXXXXXXX______
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 25: _________________________________________________________________XXXXXXXX_______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: __________________________________________________________________XXXXXXXX______
Uplink 29: __________________________________________________________________XXXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXX_______
Uplink 31: ___________________________________________________________________XXXXXX_______
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 36
Eye Window: ________________XXXX____________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 21:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 22:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 23:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 26:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 27:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 28:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 29:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 30:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
Uplink 31:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXX_
]
11:22:42:setup_element:INFO: Beginning SMX ASICs map scan
11:22:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:22:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:22:42:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:22:42:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:22:42:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31]
11:22:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
11:22:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
11:22:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
11:22:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
11:22:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
11:22:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
11:22:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
11:22:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
11:22:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
11:22:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
11:22:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
11:22:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
11:22:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
11:22:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
11:22:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
11:22:45:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 71
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXX______
Uplink 17: ____________________________________________________________________XXXXXX______
Uplink 18: ___________________________________________________________________XXXXXXX______
Uplink 19: ___________________________________________________________________XXXXXXX______
Uplink 20: __________________________________________________________________XXXXXXXX______
Uplink 21: __________________________________________________________________XXXXXXXX______
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 25: _________________________________________________________________XXXXXXXX_______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: __________________________________________________________________XXXXXXXX______
Uplink 29: __________________________________________________________________XXXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXX_______
Uplink 31: ___________________________________________________________________XXXXXX_______
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 36
Eye Window: ________________XXXX____________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 21:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 22:
Optimal Phase: 27
Window Length: 36
Eye Window: ______XXXX______________________________
Uplink 23:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 25:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 26:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 27:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 28:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 29:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 30:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
Uplink 31:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXX_
11:22:45:setup_element:INFO: Performing Elink synchronization
11:22:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:22:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:22:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:22:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:22:45:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
11:22:45:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31]
11:22:45:ST3_emu:INFO: Number of chips: 8
11:22:45:ST3_emu:INFO: Chip address: 0x0
11:22:45:ST3_emu:INFO: Chip address: 0x1
11:22:45:ST3_emu:INFO: Chip address: 0x2
11:22:45:ST3_emu:INFO: Chip address: 0x3
11:22:45:ST3_emu:INFO: Chip address: 0x4
11:22:45:ST3_emu:INFO: Chip address: 0x5
11:22:45:ST3_emu:INFO: Chip address: 0x6
11:22:45:ST3_emu:INFO: Chip address: 0x7
11:22:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:22:46:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 34.6 | 1195.1
11:22:46:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 28.2 | 1224.5
11:22:46:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1189.2
11:22:46:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 34.6 | 1201.0
11:22:46:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 44.1 | 1159.7
11:22:47:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 47.3 | 1159.7
11:22:47:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 40.9 | 1171.5
11:22:47:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1189.2
11:22:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:22:51:ST3_smx:INFO: chip: 0-0 40.898880 C 1159.654860 mV
11:22:51:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:22:51:ST3_smx:INFO: Electrons
11:22:51:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:22:53:ST3_smx:INFO: ----> Checking Analog response
11:22:53:ST3_smx:INFO: ----> Checking broken channels
11:22:53:ST3_smx:INFO: Total # broken ch: 0
11:22:53:ST3_smx:INFO: List FAST: []
11:22:53:ST3_smx:INFO: List SLOW: []
11:22:53:ST3_smx:INFO: Holes
11:22:53:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:22:56:ST3_smx:INFO: ----> Checking Analog response
11:22:56:ST3_smx:INFO: ----> Checking broken channels
11:22:56:ST3_smx:INFO: Total # broken ch: 0
11:22:56:ST3_smx:INFO: List FAST: []
11:22:56:ST3_smx:INFO: List SLOW: []
11:22:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:22:56:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 40.9 | 1153.7
11:22:56:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 28.2 | 1224.5
11:22:56:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:22:57:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 34.6 | 1201.0
11:22:57:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 44.1 | 1159.7
11:22:57:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1159.7
11:22:57:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 40.9 | 1171.5
11:22:58:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1183.3
11:22:58:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:02:ST3_smx:INFO: chip: 0-1 37.726682 C 1171.483840 mV
11:23:02:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:02:ST3_smx:INFO: Electrons
11:23:02:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:04:ST3_smx:INFO: ----> Checking Analog response
11:23:04:ST3_smx:INFO: ----> Checking broken channels
11:23:04:ST3_smx:INFO: Total # broken ch: 0
11:23:04:ST3_smx:INFO: List FAST: []
11:23:04:ST3_smx:INFO: List SLOW: []
11:23:04:ST3_smx:INFO: Holes
11:23:04:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:06:ST3_smx:INFO: ----> Checking Analog response
11:23:06:ST3_smx:INFO: ----> Checking broken channels
11:23:06:ST3_smx:INFO: Total # broken ch: 0
11:23:06:ST3_smx:INFO: List FAST: []
11:23:06:ST3_smx:INFO: List SLOW: []
11:23:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:07:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 40.9 | 1153.7
11:23:07:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 40.9 | 1171.5
11:23:07:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:23:07:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 34.6 | 1201.0
11:23:07:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 47.3 | 1159.7
11:23:08:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 47.3 | 1159.7
11:23:08:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 40.9 | 1171.5
11:23:08:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1183.3
11:23:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:12:ST3_smx:INFO: chip: 0-2 34.556970 C 1189.190035 mV
11:23:12:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:12:ST3_smx:INFO: Electrons
11:23:12:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:15:ST3_smx:INFO: ----> Checking Analog response
11:23:15:ST3_smx:INFO: ----> Checking broken channels
11:23:15:ST3_smx:INFO: Total # broken ch: 0
11:23:15:ST3_smx:INFO: List FAST: []
11:23:15:ST3_smx:INFO: List SLOW: []
11:23:15:ST3_smx:INFO: Holes
11:23:15:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:17:ST3_smx:INFO: ----> Checking Analog response
11:23:17:ST3_smx:INFO: ----> Checking broken channels
11:23:17:ST3_smx:INFO: Total # broken ch: 0
11:23:17:ST3_smx:INFO: List FAST: []
11:23:17:ST3_smx:INFO: List SLOW: []
11:23:17:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:17:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 40.9 | 1153.7
11:23:18:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 40.9 | 1171.5
11:23:18:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:23:18:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 34.6 | 1201.0
11:23:18:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 47.3 | 1159.7
11:23:19:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1159.7
11:23:19:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 40.9 | 1171.5
11:23:19:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1183.3
11:23:19:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:23:ST3_smx:INFO: chip: 0-3 47.250730 C 1147.806000 mV
11:23:23:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:23:ST3_smx:INFO: Electrons
11:23:23:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:25:ST3_smx:INFO: ----> Checking Analog response
11:23:25:ST3_smx:INFO: ----> Checking broken channels
11:23:25:ST3_smx:INFO: Total # broken ch: 0
11:23:25:ST3_smx:INFO: List FAST: []
11:23:25:ST3_smx:INFO: List SLOW: []
11:23:25:ST3_smx:INFO: Holes
11:23:25:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:27:ST3_smx:INFO: ----> Checking Analog response
11:23:27:ST3_smx:INFO: ----> Checking broken channels
11:23:28:ST3_smx:INFO: Total # broken ch: 0
11:23:28:ST3_smx:INFO: List FAST: []
11:23:28:ST3_smx:INFO: List SLOW: []
11:23:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:28:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 40.9 | 1153.7
11:23:28:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 44.1 | 1165.6
11:23:28:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:23:29:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 50.4 | 1141.9
11:23:29:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 47.3 | 1159.7
11:23:29:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1153.7
11:23:29:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 44.1 | 1171.5
11:23:29:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1183.3
11:23:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:34:ST3_smx:INFO: chip: 0-4 44.073563 C 1165.571835 mV
11:23:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:34:ST3_smx:INFO: Electrons
11:23:34:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:36:ST3_smx:INFO: ----> Checking Analog response
11:23:36:ST3_smx:INFO: ----> Checking broken channels
11:23:36:ST3_smx:INFO: Total # broken ch: 0
11:23:36:ST3_smx:INFO: List FAST: []
11:23:36:ST3_smx:INFO: List SLOW: []
11:23:36:ST3_smx:INFO: Holes
11:23:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:38:ST3_smx:INFO: ----> Checking Analog response
11:23:38:ST3_smx:INFO: ----> Checking broken channels
11:23:38:ST3_smx:INFO: Total # broken ch: 0
11:23:38:ST3_smx:INFO: List FAST: []
11:23:38:ST3_smx:INFO: List SLOW: []
11:23:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:39:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 44.1 | 1153.7
11:23:39:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 40.9 | 1165.6
11:23:39:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:23:39:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 50.4 | 1147.8
11:23:40:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 44.1 | 1159.7
11:23:40:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1153.7
11:23:40:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 44.1 | 1165.6
11:23:40:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1183.3
11:23:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:45:ST3_smx:INFO: chip: 0-5 47.250730 C 1153.732915 mV
11:23:45:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:45:ST3_smx:INFO: Electrons
11:23:45:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:47:ST3_smx:INFO: ----> Checking Analog response
11:23:47:ST3_smx:INFO: ----> Checking broken channels
11:23:47:ST3_smx:INFO: Total # broken ch: 0
11:23:47:ST3_smx:INFO: List FAST: []
11:23:47:ST3_smx:INFO: List SLOW: []
11:23:47:ST3_smx:INFO: Holes
11:23:47:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:49:ST3_smx:INFO: ----> Checking Analog response
11:23:49:ST3_smx:INFO: ----> Checking broken channels
11:23:49:ST3_smx:INFO: Total # broken ch: 0
11:23:49:ST3_smx:INFO: List FAST: []
11:23:49:ST3_smx:INFO: List SLOW: []
11:23:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:49:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 44.1 | 1153.7
11:23:50:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 44.1 | 1165.6
11:23:50:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:23:50:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 50.4 | 1147.8
11:23:50:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 44.1 | 1159.7
11:23:51:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1147.8
11:23:51:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 44.1 | 1165.6
11:23:51:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 40.9 | 1183.3
11:23:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:55:ST3_smx:INFO: chip: 0-6 44.073563 C 1159.654860 mV
11:23:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:55:ST3_smx:INFO: Electrons
11:23:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:57:ST3_smx:INFO: ----> Checking Analog response
11:23:57:ST3_smx:INFO: ----> Checking broken channels
11:23:57:ST3_smx:INFO: Total # broken ch: 0
11:23:57:ST3_smx:INFO: List FAST: []
11:23:57:ST3_smx:INFO: List SLOW: []
11:23:57:ST3_smx:INFO: Holes
11:23:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:00:ST3_smx:INFO: ----> Checking Analog response
11:24:00:ST3_smx:INFO: ----> Checking broken channels
11:24:00:ST3_smx:INFO: Total # broken ch: 0
11:24:00:ST3_smx:INFO: List FAST: []
11:24:00:ST3_smx:INFO: List SLOW: []
11:24:00:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:00:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 44.1 | 1153.7
11:24:00:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 40.9 | 1165.6
11:24:01:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:24:01:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 50.4 | 1141.9
11:24:01:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 44.1 | 1153.7
11:24:01:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1147.8
11:24:02:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 44.1 | 1153.7
11:24:02:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 44.1 | 1183.3
11:24:02:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:24:06:ST3_smx:INFO: chip: 0-7 44.073563 C 1165.571835 mV
11:24:06:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:24:06:ST3_smx:INFO: Electrons
11:24:06:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:08:ST3_smx:INFO: ----> Checking Analog response
11:24:08:ST3_smx:INFO: ----> Checking broken channels
11:24:08:ST3_smx:INFO: Total # broken ch: 0
11:24:08:ST3_smx:INFO: List FAST: []
11:24:08:ST3_smx:INFO: List SLOW: []
11:24:08:ST3_smx:INFO: Holes
11:24:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:10:ST3_smx:INFO: ----> Checking Analog response
11:24:10:ST3_smx:INFO: ----> Checking broken channels
11:24:10:ST3_smx:INFO: Total # broken ch: 0
11:24:10:ST3_smx:INFO: List FAST: []
11:24:10:ST3_smx:INFO: List SLOW: []
11:24:10:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:11:febtest:INFO: 0-0 | XA-000-08-002-002-007-113-03 | 44.1 | 1153.7
11:24:11:febtest:INFO: 0-1 | XA-000-08-002-002-007-121-03 | 44.1 | 1165.6
11:24:11:febtest:INFO: 0-2 | XA-000-08-002-002-007-118-03 | 37.7 | 1183.3
11:24:11:febtest:INFO: 0-3 | XA-000-08-002-002-007-117-03 | 50.4 | 1141.9
11:24:11:febtest:INFO: 0-4 | XA-000-08-002-002-007-122-03 | 44.1 | 1159.7
11:24:12:febtest:INFO: 0-5 | XA-000-08-002-002-007-129-05 | 50.4 | 1147.8
11:24:12:febtest:INFO: 0-6 | XA-000-08-002-002-007-119-03 | 44.1 | 1153.7
11:24:12:febtest:INFO: 0-7 | XA-000-08-002-002-007-123-03 | 47.3 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_03-11_22_34', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-002-007-123-03', 'FUSED_ID': 6359364699118663603, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '1.6210', '1.846', '1.9770', '7.000', '1.5260', '7.000', '1.5260'], 'VI_aInit': ['2.450', '2.0010', '1.850', '1.4700', '7.000', '1.5310', '7.000', '1.5310'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
11:24:16:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1007/A//TestDate_2023_08_03-11_22_34/