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FEB_1008 03.08.23 11:25:21
Info
11:25:14:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:25:21:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:25:21:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:25:21:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:25:22:febtest:INFO: Tsting FEB with SN 1008
11:25:23:smx_tester:INFO: Scanning setup
11:25:23:elinks:INFO: Disabling clock on downlink 0
11:25:23:elinks:INFO: Disabling clock on downlink 1
11:25:23:elinks:INFO: Disabling clock on downlink 2
11:25:23:elinks:INFO: Disabling clock on downlink 3
11:25:23:elinks:INFO: Disabling clock on downlink 4
11:25:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:25:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:25:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:25:23:elinks:INFO: Disabling clock on downlink 0
11:25:23:elinks:INFO: Disabling clock on downlink 1
11:25:23:elinks:INFO: Disabling clock on downlink 2
11:25:23:elinks:INFO: Disabling clock on downlink 3
11:25:23:elinks:INFO: Disabling clock on downlink 4
11:25:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:25:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:25:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:25:23:elinks:INFO: Disabling clock on downlink 0
11:25:23:elinks:INFO: Disabling clock on downlink 1
11:25:23:elinks:INFO: Disabling clock on downlink 2
11:25:23:elinks:INFO: Disabling clock on downlink 3
11:25:23:elinks:INFO: Disabling clock on downlink 4
11:25:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:25:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:25:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:25:23:elinks:INFO: Disabling clock on downlink 0
11:25:23:elinks:INFO: Disabling clock on downlink 1
11:25:23:elinks:INFO: Disabling clock on downlink 2
11:25:23:elinks:INFO: Disabling clock on downlink 3
11:25:23:elinks:INFO: Disabling clock on downlink 4
11:25:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:25:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:25:23:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
11:25:23:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
11:25:23:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
11:25:23:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
11:25:23:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
11:25:23:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
11:25:24:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
11:25:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:25:24:elinks:INFO: Disabling clock on downlink 0
11:25:24:elinks:INFO: Disabling clock on downlink 1
11:25:24:elinks:INFO: Disabling clock on downlink 2
11:25:24:elinks:INFO: Disabling clock on downlink 3
11:25:24:elinks:INFO: Disabling clock on downlink 4
11:25:24:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:25:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:25:24:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:25:24:setup_element:INFO: Scanning clock phase
11:25:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:25:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:25:24:setup_element:INFO: Clock phase scan results for group 0, downlink 3
11:25:24:setup_element:INFO: Eye window for uplink 16: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:25:24:setup_element:INFO: Eye window for uplink 17: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:25:24:setup_element:INFO: Eye window for uplink 18: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 19: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 20: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 21: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:25:24:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:25:24:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:25:24:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:25:24:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
11:25:24:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
11:25:24:setup_element:INFO: Eye window for uplink 28: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 29: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:25:24:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 3
11:25:24:setup_element:INFO: Scanning data phases
11:25:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:25:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:25:30:setup_element:INFO: Data phase scan results for group 0, downlink 3
11:25:30:setup_element:INFO: Eye window for uplink 16: ________________XXX_____________________
Data delay found: 37
11:25:30:setup_element:INFO: Eye window for uplink 17: ____________XXXX________________________
Data delay found: 33
11:25:30:setup_element:INFO: Eye window for uplink 18: ___________XXXXX________________________
Data delay found: 33
11:25:30:setup_element:INFO: Eye window for uplink 19: _________XXXXX__________________________
Data delay found: 31
11:25:30:setup_element:INFO: Eye window for uplink 20: _______XXXXX____________________________
Data delay found: 29
11:25:30:setup_element:INFO: Eye window for uplink 21: _____XXXXXX_____________________________
Data delay found: 27
11:25:30:setup_element:INFO: Eye window for uplink 22: _____XXXXX______________________________
Data delay found: 27
11:25:30:setup_element:INFO: Eye window for uplink 23: ___XXXX_________________________________
Data delay found: 24
11:25:30:setup_element:INFO: Eye window for uplink 24: XX_________________________________XXXXX
Data delay found: 18
11:25:30:setup_element:INFO: Eye window for uplink 25: XXX____________________________________X
Data delay found: 20
11:25:30:setup_element:INFO: Eye window for uplink 26: _________________________________XXXXX__
Data delay found: 15
11:25:30:setup_element:INFO: Eye window for uplink 27: XXX___________________________________XX
Data delay found: 20
11:25:30:setup_element:INFO: Eye window for uplink 28: X__________________________________XXXXX
Data delay found: 17
11:25:30:setup_element:INFO: Eye window for uplink 29: XXX__________________________________XXX
Data delay found: 19
11:25:30:setup_element:INFO: Eye window for uplink 30: X__________________________________XXXXX
Data delay found: 17
11:25:30:setup_element:INFO: Eye window for uplink 31: _________________________________XXXXX__
Data delay found: 15
11:25:30:setup_element:INFO: Setting the data phase to 37 for uplink 16
11:25:30:setup_element:INFO: Setting the data phase to 33 for uplink 17
11:25:30:setup_element:INFO: Setting the data phase to 33 for uplink 18
11:25:30:setup_element:INFO: Setting the data phase to 31 for uplink 19
11:25:30:setup_element:INFO: Setting the data phase to 29 for uplink 20
11:25:30:setup_element:INFO: Setting the data phase to 27 for uplink 21
11:25:30:setup_element:INFO: Setting the data phase to 27 for uplink 22
11:25:30:setup_element:INFO: Setting the data phase to 24 for uplink 23
11:25:30:setup_element:INFO: Setting the data phase to 18 for uplink 24
11:25:30:setup_element:INFO: Setting the data phase to 20 for uplink 25
11:25:30:setup_element:INFO: Setting the data phase to 15 for uplink 26
11:25:30:setup_element:INFO: Setting the data phase to 20 for uplink 27
11:25:30:setup_element:INFO: Setting the data phase to 17 for uplink 28
11:25:30:setup_element:INFO: Setting the data phase to 19 for uplink 29
11:25:30:setup_element:INFO: Setting the data phase to 17 for uplink 30
11:25:30:setup_element:INFO: Setting the data phase to 15 for uplink 31
11:25:30:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 71
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXX_____
Uplink 17: ____________________________________________________________________XXXXXXX_____
Uplink 18: ___________________________________________________________________XXXXXXX______
Uplink 19: ___________________________________________________________________XXXXXXX______
Uplink 20: ___________________________________________________________________XXXXXXX______
Uplink 21: ___________________________________________________________________XXXXXXX______
Uplink 22: ____________________________________________________________________XXXXXXX_____
Uplink 23: ____________________________________________________________________XXXXXXX_____
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXX_______
Uplink 27: __________________________________________________________________XXXXXXX_______
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 37
Eye Window: ________________XXX_____________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 21:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 22:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 23:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 24:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 36
Eye Window: XXX____________________________________X
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 28:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 29:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 30:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 31:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
]
11:25:30:setup_element:INFO: Beginning SMX ASICs map scan
11:25:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:25:30:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:25:30:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:25:30:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:25:30:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:25:30:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
11:25:30:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
11:25:30:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
11:25:30:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
11:25:30:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
11:25:30:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
11:25:31:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
11:25:31:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
11:25:31:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
11:25:31:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
11:25:31:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
11:25:31:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
11:25:31:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
11:25:31:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
11:25:31:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
11:25:31:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
11:25:33:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 71
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXX_____
Uplink 17: ____________________________________________________________________XXXXXXX_____
Uplink 18: ___________________________________________________________________XXXXXXX______
Uplink 19: ___________________________________________________________________XXXXXXX______
Uplink 20: ___________________________________________________________________XXXXXXX______
Uplink 21: ___________________________________________________________________XXXXXXX______
Uplink 22: ____________________________________________________________________XXXXXXX_____
Uplink 23: ____________________________________________________________________XXXXXXX_____
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXX_______
Uplink 27: __________________________________________________________________XXXXXXX_______
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 37
Eye Window: ________________XXX_____________________
Uplink 17:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 18:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 21:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 22:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 23:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 24:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 36
Eye Window: XXX____________________________________X
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 28:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 29:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 30:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 31:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
11:25:33:setup_element:INFO: Performing Elink synchronization
11:25:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:25:33:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:25:33:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:25:33:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:25:33:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
11:25:33:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:25:33:ST3_emu:INFO: Number of chips: 8
11:25:33:ST3_emu:INFO: Chip address: 0x0
11:25:33:ST3_emu:INFO: Chip address: 0x1
11:25:33:ST3_emu:INFO: Chip address: 0x2
11:25:33:ST3_emu:INFO: Chip address: 0x3
11:25:33:ST3_emu:INFO: Chip address: 0x4
11:25:33:ST3_emu:INFO: Chip address: 0x5
11:25:33:ST3_emu:INFO: Chip address: 0x6
11:25:33:ST3_emu:INFO: Chip address: 0x7
11:25:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:25:34:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 21.9 | 1259.6
11:25:34:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 31.4 | 1224.5
11:25:34:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 31.4 | 1224.5
11:25:34:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 31.4 | 1230.3
11:25:35:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1212.7
11:25:35:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 34.6 | 1212.7
11:25:35:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:25:35:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 34.6 | 1206.9
11:25:35:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:25:39:ST3_smx:INFO: chip: 0-0 34.556970 C 1200.969315 mV
11:25:39:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:25:39:ST3_smx:INFO: Electrons
11:25:39:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:25:41:ST3_smx:INFO: ----> Checking Analog response
11:25:41:ST3_smx:INFO: ----> Checking broken channels
11:25:41:ST3_smx:INFO: Total # broken ch: 0
11:25:41:ST3_smx:INFO: List FAST: []
11:25:41:ST3_smx:INFO: List SLOW: []
11:25:41:ST3_smx:INFO: Holes
11:25:41:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:25:44:ST3_smx:INFO: ----> Checking Analog response
11:25:44:ST3_smx:INFO: ----> Checking broken channels
11:25:44:ST3_smx:INFO: Total # broken ch: 0
11:25:44:ST3_smx:INFO: List FAST: []
11:25:44:ST3_smx:INFO: List SLOW: []
11:25:44:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:25:44:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 34.6 | 1195.1
11:25:44:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 31.4 | 1218.6
11:25:45:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 31.4 | 1224.5
11:25:45:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 31.4 | 1230.3
11:25:45:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1212.7
11:25:45:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 34.6 | 1212.7
11:25:45:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:25:46:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 34.6 | 1206.9
11:25:46:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:25:50:ST3_smx:INFO: chip: 0-1 34.556970 C 1195.082160 mV
11:25:50:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:25:50:ST3_smx:INFO: Electrons
11:25:50:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:25:52:ST3_smx:INFO: ----> Checking Analog response
11:25:52:ST3_smx:INFO: ----> Checking broken channels
11:25:52:ST3_smx:INFO: Total # broken ch: 0
11:25:52:ST3_smx:INFO: List FAST: []
11:25:52:ST3_smx:INFO: List SLOW: []
11:25:52:ST3_smx:INFO: Holes
11:25:52:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:25:54:ST3_smx:INFO: ----> Checking Analog response
11:25:54:ST3_smx:INFO: ----> Checking broken channels
11:25:55:ST3_smx:INFO: Total # broken ch: 0
11:25:55:ST3_smx:INFO: List FAST: []
11:25:55:ST3_smx:INFO: List SLOW: []
11:25:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:25:55:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 34.6 | 1195.1
11:25:55:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 34.6 | 1195.1
11:25:55:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 31.4 | 1224.5
11:25:55:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 31.4 | 1224.5
11:25:56:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1212.7
11:25:56:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 34.6 | 1206.9
11:25:56:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:25:56:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 34.6 | 1201.0
11:25:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:26:00:ST3_smx:INFO: chip: 0-2 37.726682 C 1189.190035 mV
11:26:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:26:00:ST3_smx:INFO: Electrons
11:26:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:03:ST3_smx:INFO: ----> Checking Analog response
11:26:03:ST3_smx:INFO: ----> Checking broken channels
11:26:03:ST3_smx:INFO: Total # broken ch: 0
11:26:03:ST3_smx:INFO: List FAST: []
11:26:03:ST3_smx:INFO: List SLOW: []
11:26:03:ST3_smx:INFO: Holes
11:26:03:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:05:ST3_smx:INFO: ----> Checking Analog response
11:26:05:ST3_smx:INFO: ----> Checking broken channels
11:26:05:ST3_smx:INFO: Total # broken ch: 0
11:26:05:ST3_smx:INFO: List FAST: []
11:26:05:ST3_smx:INFO: List SLOW: []
11:26:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:26:05:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 37.7 | 1195.1
11:26:06:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 37.7 | 1195.1
11:26:06:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 40.9 | 1183.3
11:26:06:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 31.4 | 1224.5
11:26:06:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1212.7
11:26:07:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 34.6 | 1206.9
11:26:07:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:26:07:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 34.6 | 1201.0
11:26:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:26:11:ST3_smx:INFO: chip: 0-3 44.073563 C 1171.483840 mV
11:26:11:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:26:11:ST3_smx:INFO: Electrons
11:26:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:14:ST3_smx:INFO: ----> Checking Analog response
11:26:14:ST3_smx:INFO: ----> Checking broken channels
11:26:14:ST3_smx:INFO: Total # broken ch: 0
11:26:14:ST3_smx:INFO: List FAST: []
11:26:14:ST3_smx:INFO: List SLOW: []
11:26:14:ST3_smx:INFO: Holes
11:26:14:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:16:ST3_smx:INFO: ----> Checking Analog response
11:26:16:ST3_smx:INFO: ----> Checking broken channels
11:26:16:ST3_smx:INFO: Total # broken ch: 0
11:26:16:ST3_smx:INFO: List FAST: []
11:26:16:ST3_smx:INFO: List SLOW: []
11:26:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:26:16:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 37.7 | 1195.1
11:26:16:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 37.7 | 1189.2
11:26:17:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 40.9 | 1183.3
11:26:17:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 47.3 | 1165.6
11:26:17:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1206.9
11:26:17:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 34.6 | 1206.9
11:26:18:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:26:18:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 37.7 | 1201.0
11:26:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:26:22:ST3_smx:INFO: chip: 0-4 34.556970 C 1200.969315 mV
11:26:22:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:26:22:ST3_smx:INFO: Electrons
11:26:22:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:24:ST3_smx:INFO: ----> Checking Analog response
11:26:24:ST3_smx:INFO: ----> Checking broken channels
11:26:24:ST3_smx:INFO: Total # broken ch: 0
11:26:24:ST3_smx:INFO: List FAST: []
11:26:24:ST3_smx:INFO: List SLOW: []
11:26:24:ST3_smx:INFO: Holes
11:26:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:26:ST3_smx:INFO: ----> Checking Analog response
11:26:26:ST3_smx:INFO: ----> Checking broken channels
11:26:27:ST3_smx:INFO: Total # broken ch: 0
11:26:27:ST3_smx:INFO: List FAST: []
11:26:27:ST3_smx:INFO: List SLOW: []
11:26:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:26:27:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 37.7 | 1195.1
11:26:27:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 37.7 | 1189.2
11:26:27:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 40.9 | 1183.3
11:26:27:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 47.3 | 1165.6
11:26:28:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1201.0
11:26:28:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 37.7 | 1206.9
11:26:28:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:26:28:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 34.6 | 1201.0
11:26:29:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:26:32:ST3_smx:INFO: chip: 0-5 47.250730 C 1153.732915 mV
11:26:32:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:26:32:ST3_smx:INFO: Electrons
11:26:32:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:34:ST3_smx:INFO: ----> Checking Analog response
11:26:34:ST3_smx:INFO: ----> Checking broken channels
11:26:35:ST3_smx:INFO: Total # broken ch: 0
11:26:35:ST3_smx:INFO: List FAST: []
11:26:35:ST3_smx:INFO: List SLOW: []
11:26:35:ST3_smx:INFO: Holes
11:26:35:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:37:ST3_smx:INFO: ----> Checking Analog response
11:26:37:ST3_smx:INFO: ----> Checking broken channels
11:26:37:ST3_smx:INFO: Total # broken ch: 0
11:26:37:ST3_smx:INFO: List FAST: []
11:26:37:ST3_smx:INFO: List SLOW: []
11:26:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:26:37:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 37.7 | 1195.1
11:26:37:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 37.7 | 1189.2
11:26:38:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 40.9 | 1183.3
11:26:38:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 47.3 | 1165.6
11:26:38:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 34.6 | 1201.0
11:26:38:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 50.4 | 1153.7
11:26:39:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 28.2 | 1230.3
11:26:39:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 37.7 | 1201.0
11:26:39:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:26:43:ST3_smx:INFO: chip: 0-6 34.556970 C 1206.851500 mV
11:26:43:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:26:43:ST3_smx:INFO: Electrons
11:26:43:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:45:ST3_smx:INFO: ----> Checking Analog response
11:26:45:ST3_smx:INFO: ----> Checking broken channels
11:26:45:ST3_smx:INFO: Total # broken ch: 0
11:26:45:ST3_smx:INFO: List FAST: []
11:26:45:ST3_smx:INFO: List SLOW: []
11:26:45:ST3_smx:INFO: Holes
11:26:45:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:47:ST3_smx:INFO: ----> Checking Analog response
11:26:47:ST3_smx:INFO: ----> Checking broken channels
11:26:47:ST3_smx:INFO: Total # broken ch: 0
11:26:47:ST3_smx:INFO: List FAST: []
11:26:47:ST3_smx:INFO: List SLOW: []
11:26:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:26:47:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 37.7 | 1195.1
11:26:48:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 37.7 | 1189.2
11:26:48:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 40.9 | 1177.4
11:26:48:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 47.3 | 1165.6
11:26:48:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 37.7 | 1195.1
11:26:49:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 50.4 | 1153.7
11:26:49:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 34.6 | 1201.0
11:26:49:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 37.7 | 1201.0
11:26:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:26:53:ST3_smx:INFO: chip: 0-7 44.073563 C 1171.483840 mV
11:26:53:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:26:53:ST3_smx:INFO: Electrons
11:26:53:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:55:ST3_smx:INFO: ----> Checking Analog response
11:26:55:ST3_smx:INFO: ----> Checking broken channels
11:26:56:ST3_smx:INFO: Total # broken ch: 0
11:26:56:ST3_smx:INFO: List FAST: []
11:26:56:ST3_smx:INFO: List SLOW: []
11:26:56:ST3_smx:INFO: Holes
11:26:56:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:26:58:ST3_smx:INFO: ----> Checking Analog response
11:26:58:ST3_smx:INFO: ----> Checking broken channels
11:26:58:ST3_smx:INFO: Total # broken ch: 0
11:26:58:ST3_smx:INFO: List FAST: []
11:26:58:ST3_smx:INFO: List SLOW: []
11:26:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:26:58:febtest:INFO: 0-0 | XA-000-08-002-002-007-128-05 | 37.7 | 1195.1
11:26:58:febtest:INFO: 0-1 | XA-000-08-002-002-007-095-13 | 37.7 | 1189.2
11:26:58:febtest:INFO: 0-2 | XA-000-08-002-002-007-131-05 | 40.9 | 1177.4
11:26:59:febtest:INFO: 0-3 | XA-000-08-002-002-007-134-05 | 47.3 | 1159.7
11:26:59:febtest:INFO: 0-4 | XA-000-08-002-002-007-132-05 | 37.7 | 1195.1
11:26:59:febtest:INFO: 0-5 | XA-000-08-002-002-007-124-03 | 50.4 | 1153.7
11:26:59:febtest:INFO: 0-6 | XA-000-08-002-002-007-116-03 | 34.6 | 1201.0
11:27:00:febtest:INFO: 0-7 | XA-000-08-002-002-007-120-03 | 44.1 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_03-11_25_21', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-002-007-120-03', 'FUSED_ID': 6359364699118663555, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.4690', '1.847', '1.8840', '7.000', '1.5320', '7.000', '1.5320'], 'VI_aInit': ['2.450', '2.0280', '1.850', '1.4930', '7.000', '1.5330', '7.000', '1.5330'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
11:27:05:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1008/A//TestDate_2023_08_03-11_25_21/