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FEB_1009 03.08.23 14:49:39
Info
14:49:34:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:49:34:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
14:49:36:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:49:36:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
14:49:37:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:49:37:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
14:49:38:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:49:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:49:39:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:49:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:49:40:febtest:INFO: Tsting FEB with SN 1009
14:49:41:smx_tester:INFO: Scanning setup
14:49:41:elinks:INFO: Disabling clock on downlink 0
14:49:41:elinks:INFO: Disabling clock on downlink 1
14:49:41:elinks:INFO: Disabling clock on downlink 2
14:49:41:elinks:INFO: Disabling clock on downlink 3
14:49:41:elinks:INFO: Disabling clock on downlink 4
14:49:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:49:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:49:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:49:41:elinks:INFO: Disabling clock on downlink 0
14:49:41:elinks:INFO: Disabling clock on downlink 1
14:49:41:elinks:INFO: Disabling clock on downlink 2
14:49:41:elinks:INFO: Disabling clock on downlink 3
14:49:41:elinks:INFO: Disabling clock on downlink 4
14:49:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:49:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:49:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:49:41:elinks:INFO: Disabling clock on downlink 0
14:49:41:elinks:INFO: Disabling clock on downlink 1
14:49:41:elinks:INFO: Disabling clock on downlink 2
14:49:41:elinks:INFO: Disabling clock on downlink 3
14:49:41:elinks:INFO: Disabling clock on downlink 4
14:49:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:49:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:49:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:49:41:elinks:INFO: Disabling clock on downlink 0
14:49:41:elinks:INFO: Disabling clock on downlink 1
14:49:41:elinks:INFO: Disabling clock on downlink 2
14:49:41:elinks:INFO: Disabling clock on downlink 3
14:49:41:elinks:INFO: Disabling clock on downlink 4
14:49:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:49:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
14:49:42:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
14:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:49:42:elinks:INFO: Disabling clock on downlink 0
14:49:42:elinks:INFO: Disabling clock on downlink 1
14:49:42:elinks:INFO: Disabling clock on downlink 2
14:49:42:elinks:INFO: Disabling clock on downlink 3
14:49:42:elinks:INFO: Disabling clock on downlink 4
14:49:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:49:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:49:42:setup_element:INFO: Scanning clock phase
14:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:49:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:49:43:setup_element:INFO: Clock phase scan results for group 0, downlink 3
14:49:43:setup_element:INFO: Eye window for uplink 16: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:49:43:setup_element:INFO: Eye window for uplink 17: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:49:43:setup_element:INFO: Eye window for uplink 18: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 19: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 20: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 21: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXX______
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXX______
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:49:43:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:49:43:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:49:43:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
14:49:43:setup_element:INFO: Eye window for uplink 28: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 29: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:49:43:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
14:49:43:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 3
14:49:43:setup_element:INFO: Scanning data phases
14:49:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:49:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:49:48:setup_element:INFO: Data phase scan results for group 0, downlink 3
14:49:48:setup_element:INFO: Eye window for uplink 16: ________________XXXXX___________________
Data delay found: 38
14:49:48:setup_element:INFO: Eye window for uplink 17: ____________XXXXX_______________________
Data delay found: 34
14:49:48:setup_element:INFO: Eye window for uplink 18: ___________XXXXX________________________
Data delay found: 33
14:49:48:setup_element:INFO: Eye window for uplink 19: _________XXXXX__________________________
Data delay found: 31
14:49:48:setup_element:INFO: Eye window for uplink 20: _______XXXXX____________________________
Data delay found: 29
14:49:48:setup_element:INFO: Eye window for uplink 21: ______XXXXX_____________________________
Data delay found: 28
14:49:48:setup_element:INFO: Eye window for uplink 22: ____XXXX________________________________
Data delay found: 25
14:49:48:setup_element:INFO: Eye window for uplink 23: _XXXX___________________________________
Data delay found: 22
14:49:48:setup_element:INFO: Eye window for uplink 24: __________________________________XXXXX_
Data delay found: 16
14:49:48:setup_element:INFO: Eye window for uplink 25: XXX___________________________________XX
Data delay found: 20
14:49:48:setup_element:INFO: Eye window for uplink 26: _________________________________XXXXX__
Data delay found: 15
14:49:48:setup_element:INFO: Eye window for uplink 27: XXX__________________________________XXX
Data delay found: 19
14:49:48:setup_element:INFO: Eye window for uplink 28: ___________________________________XXXXX
Data delay found: 17
14:49:48:setup_element:INFO: Eye window for uplink 29: XX__________________________________XXXX
Data delay found: 18
14:49:48:setup_element:INFO: Eye window for uplink 30: X__________________________________XXXXX
Data delay found: 17
14:49:48:setup_element:INFO: Eye window for uplink 31: _________________________________XXXXX__
Data delay found: 15
14:49:48:setup_element:INFO: Setting the data phase to 38 for uplink 16
14:49:48:setup_element:INFO: Setting the data phase to 34 for uplink 17
14:49:48:setup_element:INFO: Setting the data phase to 33 for uplink 18
14:49:48:setup_element:INFO: Setting the data phase to 31 for uplink 19
14:49:48:setup_element:INFO: Setting the data phase to 29 for uplink 20
14:49:48:setup_element:INFO: Setting the data phase to 28 for uplink 21
14:49:48:setup_element:INFO: Setting the data phase to 25 for uplink 22
14:49:48:setup_element:INFO: Setting the data phase to 22 for uplink 23
14:49:48:setup_element:INFO: Setting the data phase to 16 for uplink 24
14:49:48:setup_element:INFO: Setting the data phase to 20 for uplink 25
14:49:48:setup_element:INFO: Setting the data phase to 15 for uplink 26
14:49:48:setup_element:INFO: Setting the data phase to 19 for uplink 27
14:49:48:setup_element:INFO: Setting the data phase to 17 for uplink 28
14:49:48:setup_element:INFO: Setting the data phase to 18 for uplink 29
14:49:48:setup_element:INFO: Setting the data phase to 17 for uplink 30
14:49:48:setup_element:INFO: Setting the data phase to 15 for uplink 31
14:49:48:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXXX____
Uplink 17: ____________________________________________________________________XXXXXXXX____
Uplink 18: ___________________________________________________________________XXXXXXXX_____
Uplink 19: ___________________________________________________________________XXXXXXXX_____
Uplink 20: ___________________________________________________________________XXXXXXXX_____
Uplink 21: ___________________________________________________________________XXXXXXXX_____
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 17:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 18:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 21:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 22:
Optimal Phase: 25
Window Length: 36
Eye Window: ____XXXX________________________________
Uplink 23:
Optimal Phase: 22
Window Length: 36
Eye Window: _XXXX___________________________________
Uplink 24:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 25:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 28:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 29:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 30:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 31:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
]
14:49:48:setup_element:INFO: Beginning SMX ASICs map scan
14:49:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:49:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:49:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:49:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:49:49:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:49:49:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
14:49:49:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
14:49:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
14:49:49:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
14:49:49:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
14:49:49:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
14:49:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
14:49:49:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
14:49:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
14:49:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
14:49:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
14:49:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
14:49:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
14:49:50:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
14:49:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
14:49:50:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
14:49:51:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXXX____
Uplink 17: ____________________________________________________________________XXXXXXXX____
Uplink 18: ___________________________________________________________________XXXXXXXX_____
Uplink 19: ___________________________________________________________________XXXXXXXX_____
Uplink 20: ___________________________________________________________________XXXXXXXX_____
Uplink 21: ___________________________________________________________________XXXXXXXX_____
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 24: __________________________________________________________________XXXXXXXX______
Uplink 25: __________________________________________________________________XXXXXXXX______
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ___________________________________________________________________XXXXXXX______
Uplink 31: ___________________________________________________________________XXXXXXX______
Data phase characteristics:
Uplink 16:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 17:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 18:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 19:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 20:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 21:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 22:
Optimal Phase: 25
Window Length: 36
Eye Window: ____XXXX________________________________
Uplink 23:
Optimal Phase: 22
Window Length: 36
Eye Window: _XXXX___________________________________
Uplink 24:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 25:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 26:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 27:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 28:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 29:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 30:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 31:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
14:49:51:setup_element:INFO: Performing Elink synchronization
14:49:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:49:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:49:51:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:49:51:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:49:51:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
14:49:51:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:49:51:ST3_emu:INFO: Number of chips: 8
14:49:51:ST3_emu:INFO: Chip address: 0x0
14:49:51:ST3_emu:INFO: Chip address: 0x1
14:49:51:ST3_emu:INFO: Chip address: 0x2
14:49:51:ST3_emu:INFO: Chip address: 0x3
14:49:51:ST3_emu:INFO: Chip address: 0x4
14:49:52:ST3_emu:INFO: Chip address: 0x5
14:49:52:ST3_emu:INFO: Chip address: 0x6
14:49:52:ST3_emu:INFO: Chip address: 0x7
14:49:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:49:52:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 31.4 | 1206.9
14:49:52:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 44.1 | 1165.6
14:49:53:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 47.3 | 1159.7
14:49:53:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 25.1 | 1230.3
14:49:53:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 25.1 | 1230.3
14:49:53:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1171.5
14:49:54:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:49:54:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:49:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:49:58:ST3_smx:INFO: chip: 0-0 34.556970 C 1189.190035 mV
14:49:58:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:49:58:ST3_smx:INFO: Electrons
14:49:58:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:00:ST3_smx:INFO: ----> Checking Analog response
14:50:00:ST3_smx:INFO: ----> Checking broken channels
14:50:00:ST3_smx:INFO: Total # broken ch: 0
14:50:00:ST3_smx:INFO: List FAST: []
14:50:00:ST3_smx:INFO: List SLOW: []
14:50:00:ST3_smx:INFO: Holes
14:50:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:02:ST3_smx:INFO: ----> Checking Analog response
14:50:02:ST3_smx:INFO: ----> Checking broken channels
14:50:02:ST3_smx:INFO: Total # broken ch: 0
14:50:02:ST3_smx:INFO: List FAST: []
14:50:02:ST3_smx:INFO: List SLOW: []
14:50:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:50:02:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:50:03:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 44.1 | 1165.6
14:50:03:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 47.3 | 1153.7
14:50:03:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 25.1 | 1230.3
14:50:03:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 25.1 | 1230.3
14:50:03:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1171.5
14:50:04:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:50:04:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1165.6
14:50:04:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:50:08:ST3_smx:INFO: chip: 0-1 44.073563 C 1141.874115 mV
14:50:08:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:50:08:ST3_smx:INFO: Electrons
14:50:08:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:10:ST3_smx:INFO: ----> Checking Analog response
14:50:10:ST3_smx:INFO: ----> Checking broken channels
14:50:10:ST3_smx:INFO: Total # broken ch: 0
14:50:10:ST3_smx:INFO: List FAST: []
14:50:10:ST3_smx:INFO: List SLOW: []
14:50:10:ST3_smx:INFO: Holes
14:50:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:12:ST3_smx:INFO: ----> Checking Analog response
14:50:12:ST3_smx:INFO: ----> Checking broken channels
14:50:12:ST3_smx:INFO: Total # broken ch: 0
14:50:12:ST3_smx:INFO: List FAST: []
14:50:12:ST3_smx:INFO: List SLOW: []
14:50:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:50:12:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:50:13:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1141.9
14:50:13:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 47.3 | 1159.7
14:50:13:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 25.1 | 1230.3
14:50:13:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 25.1 | 1230.3
14:50:14:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1171.5
14:50:14:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:50:14:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:50:14:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:50:18:ST3_smx:INFO: chip: 0-2 37.726682 C 1183.292940 mV
14:50:18:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:50:18:ST3_smx:INFO: Electrons
14:50:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:20:ST3_smx:INFO: ----> Checking Analog response
14:50:20:ST3_smx:INFO: ----> Checking broken channels
14:50:20:ST3_smx:INFO: Total # broken ch: 0
14:50:20:ST3_smx:INFO: List FAST: []
14:50:20:ST3_smx:INFO: List SLOW: []
14:50:20:ST3_smx:INFO: Holes
14:50:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:22:ST3_smx:INFO: ----> Checking Analog response
14:50:22:ST3_smx:INFO: ----> Checking broken channels
14:50:23:ST3_smx:INFO: Total # broken ch: 0
14:50:23:ST3_smx:INFO: List FAST: []
14:50:23:ST3_smx:INFO: List SLOW: []
14:50:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:50:23:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:50:23:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1141.9
14:50:23:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 37.7 | 1177.4
14:50:23:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 25.1 | 1230.3
14:50:24:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 25.1 | 1230.3
14:50:24:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1171.5
14:50:24:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:50:24:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:50:25:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:50:28:ST3_smx:INFO: chip: 0-3 34.556970 C 1177.390875 mV
14:50:28:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:50:28:ST3_smx:INFO: Electrons
14:50:28:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:30:ST3_smx:INFO: ----> Checking Analog response
14:50:30:ST3_smx:INFO: ----> Checking broken channels
14:50:30:ST3_smx:INFO: Total # broken ch: 0
14:50:31:ST3_smx:INFO: List FAST: []
14:50:31:ST3_smx:INFO: List SLOW: []
14:50:31:ST3_smx:INFO: Holes
14:50:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:32:ST3_smx:INFO: ----> Checking Analog response
14:50:32:ST3_smx:INFO: ----> Checking broken channels
14:50:33:ST3_smx:INFO: Total # broken ch: 0
14:50:33:ST3_smx:INFO: List FAST: []
14:50:33:ST3_smx:INFO: List SLOW: []
14:50:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:50:33:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:50:33:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1141.9
14:50:33:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 37.7 | 1177.4
14:50:34:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 37.7 | 1177.4
14:50:34:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 25.1 | 1230.3
14:50:34:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1171.5
14:50:34:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:50:35:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:50:35:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:50:39:ST3_smx:INFO: chip: 0-4 34.556970 C 1177.390875 mV
14:50:39:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:50:39:ST3_smx:INFO: Electrons
14:50:39:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:41:ST3_smx:INFO: ----> Checking Analog response
14:50:41:ST3_smx:INFO: ----> Checking broken channels
14:50:41:ST3_smx:INFO: Total # broken ch: 0
14:50:41:ST3_smx:INFO: List FAST: []
14:50:41:ST3_smx:INFO: List SLOW: []
14:50:41:ST3_smx:INFO: Holes
14:50:41:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:43:ST3_smx:INFO: ----> Checking Analog response
14:50:43:ST3_smx:INFO: ----> Checking broken channels
14:50:43:ST3_smx:INFO: Total # broken ch: 0
14:50:43:ST3_smx:INFO: List FAST: []
14:50:43:ST3_smx:INFO: List SLOW: []
14:50:43:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:50:43:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:50:44:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1141.9
14:50:44:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 37.7 | 1177.4
14:50:44:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 37.7 | 1177.4
14:50:44:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 37.7 | 1177.4
14:50:45:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1171.5
14:50:45:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:50:45:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:50:45:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:50:49:ST3_smx:INFO: chip: 0-5 40.898880 C 1159.654860 mV
14:50:49:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:50:49:ST3_smx:INFO: Electrons
14:50:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:51:ST3_smx:INFO: ----> Checking Analog response
14:50:51:ST3_smx:INFO: ----> Checking broken channels
14:50:51:ST3_smx:INFO: Total # broken ch: 0
14:50:51:ST3_smx:INFO: List FAST: []
14:50:51:ST3_smx:INFO: List SLOW: []
14:50:51:ST3_smx:INFO: Holes
14:50:51:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:50:53:ST3_smx:INFO: ----> Checking Analog response
14:50:53:ST3_smx:INFO: ----> Checking broken channels
14:50:53:ST3_smx:INFO: Total # broken ch: 0
14:50:53:ST3_smx:INFO: List FAST: []
14:50:53:ST3_smx:INFO: List SLOW: []
14:50:53:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:50:54:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:50:54:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1135.9
14:50:54:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 37.7 | 1171.5
14:50:54:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 37.7 | 1177.4
14:50:55:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 37.7 | 1171.5
14:50:55:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1153.7
14:50:55:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 34.6 | 1195.1
14:50:55:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:50:55:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:50:59:ST3_smx:INFO: chip: 0-6 40.898880 C 1165.571835 mV
14:50:59:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:50:59:ST3_smx:INFO: Electrons
14:50:59:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:51:01:ST3_smx:INFO: ----> Checking Analog response
14:51:01:ST3_smx:INFO: ----> Checking broken channels
14:51:01:ST3_smx:INFO: Total # broken ch: 0
14:51:01:ST3_smx:INFO: List FAST: []
14:51:01:ST3_smx:INFO: List SLOW: []
14:51:01:ST3_smx:INFO: Holes
14:51:01:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:51:03:ST3_smx:INFO: ----> Checking Analog response
14:51:03:ST3_smx:INFO: ----> Checking broken channels
14:51:03:ST3_smx:INFO: Total # broken ch: 0
14:51:03:ST3_smx:INFO: List FAST: []
14:51:03:ST3_smx:INFO: List SLOW: []
14:51:03:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:51:04:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1183.3
14:51:04:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1141.9
14:51:04:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 37.7 | 1177.4
14:51:04:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 37.7 | 1171.5
14:51:05:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 37.7 | 1171.5
14:51:05:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 40.9 | 1153.7
14:51:05:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 40.9 | 1159.7
14:51:05:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 44.1 | 1159.7
14:51:06:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:51:09:ST3_smx:INFO: chip: 0-7 44.073563 C 1147.806000 mV
14:51:09:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:51:09:ST3_smx:INFO: Electrons
14:51:09:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:51:11:ST3_smx:INFO: ----> Checking Analog response
14:51:11:ST3_smx:INFO: ----> Checking broken channels
14:51:11:ST3_smx:INFO: Total # broken ch: 0
14:51:11:ST3_smx:INFO: List FAST: []
14:51:11:ST3_smx:INFO: List SLOW: []
14:51:11:ST3_smx:INFO: Holes
14:51:11:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
14:51:13:ST3_smx:INFO: ----> Checking Analog response
14:51:13:ST3_smx:INFO: ----> Checking broken channels
14:51:14:ST3_smx:INFO: Total # broken ch: 0
14:51:14:ST3_smx:INFO: List FAST: []
14:51:14:ST3_smx:INFO: List SLOW: []
14:51:14:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:51:14:febtest:INFO: 0-0 | XA-000-08-002-002-007-104-04 | 34.6 | 1177.4
14:51:14:febtest:INFO: 0-1 | XA-000-08-002-002-007-087-13 | 47.3 | 1135.9
14:51:14:febtest:INFO: 0-2 | XA-000-08-002-002-007-101-04 | 40.9 | 1177.4
14:51:14:febtest:INFO: 0-3 | XA-000-08-002-002-007-085-13 | 37.7 | 1171.5
14:51:15:febtest:INFO: 0-4 | XA-000-08-002-002-007-098-04 | 37.7 | 1171.5
14:51:15:febtest:INFO: 0-5 | XA-000-08-002-002-007-084-13 | 44.1 | 1153.7
14:51:15:febtest:INFO: 0-6 | XA-000-08-002-002-007-083-13 | 40.9 | 1159.7
14:51:15:febtest:INFO: 0-7 | XA-000-08-002-002-007-086-13 | 47.3 | 1147.8
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_03-14_49_39', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-002-007-086-13', 'FUSED_ID': 6359364699118663021, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '1.6470', '1.845', '2.7700', '7.000', '1.5240', '7.000', '1.5240'], 'VI_aInit': ['2.450', '2.0130', '1.850', '1.4760', '7.000', '1.5490', '7.000', '1.5490'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
14:51:17:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1009/A//TestDate_2023_08_03-14_49_39/