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FEB_1010 17.08.23 11:40:25
TextEdit.txt
11:39:57:ST3_hmp4040:INFO:
11:39:58:febtest:INFO: FEB8.2 selected
11:39:58:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:39:58:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
11:39:58:febtest:INFO: FEB8.2 selected
11:39:58:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:39:58:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
Using config file: /home/cbm/ipbus-software/controlhub/sys.config
Starting ControlHub ... ok
11:40:05:ST3_Shared:INFO: Listo of operators:Olga B.;
11:40:06:ST3_Shared:INFO: Listo of operators:Olga B.; Oleksandr S.;
11:40:07:ST3_Shared:INFO: Listo of operators:Olga B.; Oleksandr S.; Irakli K.;
11:40:20:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:40:25:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:40:25:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
11:40:25:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:40:26:febtest:INFO: Tsting FEB with SN 1010
11:40:27:smx_tester:INFO: Scanning setup
11:40:27:elinks:INFO: Disabling clock on downlink 0
11:40:27:elinks:INFO: Disabling clock on downlink 1
11:40:27:elinks:INFO: Disabling clock on downlink 2
11:40:27:elinks:INFO: Disabling clock on downlink 3
11:40:27:elinks:INFO: Disabling clock on downlink 4
11:40:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:40:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:40:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:40:27:elinks:INFO: Disabling clock on downlink 0
11:40:27:elinks:INFO: Disabling clock on downlink 1
11:40:27:elinks:INFO: Disabling clock on downlink 2
11:40:27:elinks:INFO: Disabling clock on downlink 3
11:40:27:elinks:INFO: Disabling clock on downlink 4
11:40:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:40:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:40:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:40:27:elinks:INFO: Disabling clock on downlink 0
11:40:27:elinks:INFO: Disabling clock on downlink 1
11:40:27:elinks:INFO: Disabling clock on downlink 2
11:40:27:elinks:INFO: Disabling clock on downlink 3
11:40:27:elinks:INFO: Disabling clock on downlink 4
11:40:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:40:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:40:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:40:27:elinks:INFO: Disabling clock on downlink 0
11:40:27:elinks:INFO: Disabling clock on downlink 1
11:40:27:elinks:INFO: Disabling clock on downlink 2
11:40:27:elinks:INFO: Disabling clock on downlink 3
11:40:27:elinks:INFO: Disabling clock on downlink 4
11:40:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:40:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
11:40:27:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
11:40:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
11:40:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
11:40:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
11:40:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:40:28:elinks:INFO: Disabling clock on downlink 0
11:40:28:elinks:INFO: Disabling clock on downlink 1
11:40:28:elinks:INFO: Disabling clock on downlink 2
11:40:28:elinks:INFO: Disabling clock on downlink 3
11:40:28:elinks:INFO: Disabling clock on downlink 4
11:40:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:40:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:40:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:40:28:setup_element:INFO: Scanning clock phase
11:40:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:40:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:40:28:setup_element:INFO: Clock phase scan results for group 0, downlink 3
11:40:28:setup_element:INFO: Eye window for uplink 16: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:40:28:setup_element:INFO: Eye window for uplink 17: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:40:28:setup_element:INFO: Eye window for uplink 18: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
11:40:28:setup_element:INFO: Eye window for uplink 19: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
11:40:28:setup_element:INFO: Eye window for uplink 20: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:40:28:setup_element:INFO: Eye window for uplink 21: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:40:28:setup_element:INFO: Eye window for uplink 22: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:40:28:setup_element:INFO: Eye window for uplink 23: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:40:28:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
11:40:28:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
11:40:28:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:40:28:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
11:40:28:setup_element:INFO: Eye window for uplink 28: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:40:28:setup_element:INFO: Eye window for uplink 29: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:40:28:setup_element:INFO: Eye window for uplink 30: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:40:28:setup_element:INFO: Eye window for uplink 31: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:40:28:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 3
11:40:28:setup_element:INFO: Scanning data phases
11:40:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:40:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:40:34:setup_element:INFO: Data phase scan results for group 0, downlink 3
11:40:34:setup_element:INFO: Eye window for uplink 16: _______________XXXXX____________________
Data delay found: 37
11:40:34:setup_element:INFO: Eye window for uplink 17: ___________XXXXX________________________
Data delay found: 33
11:40:34:setup_element:INFO: Eye window for uplink 18: ________XXXXX___________________________
Data delay found: 30
11:40:34:setup_element:INFO: Eye window for uplink 19: ______XXXXX_____________________________
Data delay found: 28
11:40:34:setup_element:INFO: Eye window for uplink 20: ______XXXXX_____________________________
Data delay found: 28
11:40:34:setup_element:INFO: Eye window for uplink 21: ____XXXXXX______________________________
Data delay found: 26
11:40:34:setup_element:INFO: Eye window for uplink 22: _______XXXXX____________________________
Data delay found: 29
11:40:34:setup_element:INFO: Eye window for uplink 23: _____XXXX_______________________________
Data delay found: 26
11:40:34:setup_element:INFO: Eye window for uplink 24: XXX________________________________XXXXX
Data delay found: 18
11:40:34:setup_element:INFO: Eye window for uplink 25: XXXXX___________________________________
Data delay found: 22
11:40:34:setup_element:INFO: Eye window for uplink 26: __________________________________XXXX__
Data delay found: 15
11:40:34:setup_element:INFO: Eye window for uplink 27: XXX__________________________________XXX
Data delay found: 19
11:40:34:setup_element:INFO: Eye window for uplink 28: XXX__________________________________XXX
Data delay found: 19
11:40:34:setup_element:INFO: Eye window for uplink 29: XXXXX__________________________________X
Data delay found: 21
11:40:34:setup_element:INFO: Eye window for uplink 30: XXXXX_________________________________XX
Data delay found: 21
11:40:34:setup_element:INFO: Eye window for uplink 31: XXXX________________________________XXXX
Data delay found: 19
11:40:34:setup_element:INFO: Setting the data phase to 37 for uplink 16
11:40:34:setup_element:INFO: Setting the data phase to 33 for uplink 17
11:40:34:setup_element:INFO: Setting the data phase to 30 for uplink 18
11:40:34:setup_element:INFO: Setting the data phase to 28 for uplink 19
11:40:34:setup_element:INFO: Setting the data phase to 28 for uplink 20
11:40:34:setup_element:INFO: Setting the data phase to 26 for uplink 21
11:40:34:setup_element:INFO: Setting the data phase to 29 for uplink 22
11:40:34:setup_element:INFO: Setting the data phase to 26 for uplink 23
11:40:34:setup_element:INFO: Setting the data phase to 18 for uplink 24
11:40:34:setup_element:INFO: Setting the data phase to 22 for uplink 25
11:40:34:setup_element:INFO: Setting the data phase to 15 for uplink 26
11:40:34:setup_element:INFO: Setting the data phase to 19 for uplink 27
11:40:34:setup_element:INFO: Setting the data phase to 19 for uplink 28
11:40:34:setup_element:INFO: Setting the data phase to 21 for uplink 29
11:40:34:setup_element:INFO: Setting the data phase to 21 for uplink 30
11:40:34:setup_element:INFO: Setting the data phase to 19 for uplink 31
11:40:34:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXX_____
Uplink 17: ____________________________________________________________________XXXXXXX_____
Uplink 18: __________________________________________________________________XXXXXXX_______
Uplink 19: __________________________________________________________________XXXXXXX_______
Uplink 20: ___________________________________________________________________XXXXXXX______
Uplink 21: ___________________________________________________________________XXXXXXX______
Uplink 22: _____________________________________________________________________XXXXXXX____
Uplink 23: _____________________________________________________________________XXXXXXX____
Uplink 24: __________________________________________________________________XXXXXXXXX_____
Uplink 25: __________________________________________________________________XXXXXXXXX_____
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: ____________________________________________________________________XXXXXXX_____
Uplink 29: ____________________________________________________________________XXXXXXX_____
Uplink 30: _____________________________________________________________________XXXXXXX____
Uplink 31: _____________________________________________________________________XXXXXXX____
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 17:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 18:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 19:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 20:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 21:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 22:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 23:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 24:
Optimal Phase: 18
Window Length: 32
Eye Window: XXX________________________________XXXXX
Uplink 25:
Optimal Phase: 22
Window Length: 35
Eye Window: XXXXX___________________________________
Uplink 26:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 27:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 28:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 29:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 30:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 31:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
]
11:40:34:setup_element:INFO: Beginning SMX ASICs map scan
11:40:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:40:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:40:34:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:40:34:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:40:34:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:40:34:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
11:40:34:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
11:40:34:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
11:40:34:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
11:40:34:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
11:40:34:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
11:40:34:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
11:40:34:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
11:40:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
11:40:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
11:40:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
11:40:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
11:40:35:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
11:40:35:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
11:40:35:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
11:40:35:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
11:40:36:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 70
Eye Windows:
Uplink 16: ____________________________________________________________________XXXXXXX_____
Uplink 17: ____________________________________________________________________XXXXXXX_____
Uplink 18: __________________________________________________________________XXXXXXX_______
Uplink 19: __________________________________________________________________XXXXXXX_______
Uplink 20: ___________________________________________________________________XXXXXXX______
Uplink 21: ___________________________________________________________________XXXXXXX______
Uplink 22: _____________________________________________________________________XXXXXXX____
Uplink 23: _____________________________________________________________________XXXXXXX____
Uplink 24: __________________________________________________________________XXXXXXXXX_____
Uplink 25: __________________________________________________________________XXXXXXXXX_____
Uplink 26: __________________________________________________________________XXXXXXXX______
Uplink 27: __________________________________________________________________XXXXXXXX______
Uplink 28: ____________________________________________________________________XXXXXXX_____
Uplink 29: ____________________________________________________________________XXXXXXX_____
Uplink 30: _____________________________________________________________________XXXXXXX____
Uplink 31: _____________________________________________________________________XXXXXXX____
Data phase characteristics:
Uplink 16:
Optimal Phase: 37
Window Length: 35
Eye Window: _______________XXXXX____________________
Uplink 17:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 18:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 19:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 20:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 21:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 22:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 23:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 24:
Optimal Phase: 18
Window Length: 32
Eye Window: XXX________________________________XXXXX
Uplink 25:
Optimal Phase: 22
Window Length: 35
Eye Window: XXXXX___________________________________
Uplink 26:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 27:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 28:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 29:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 30:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 31:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
11:40:36:setup_element:INFO: Performing Elink synchronization
11:40:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:40:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:40:36:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:40:36:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:40:37:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
11:40:37:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:40:37:ST3_emu:INFO: Number of chips: 8
11:40:37:ST3_emu:INFO: Chip address: 0x0
11:40:37:ST3_emu:INFO: Chip address: 0x1
11:40:37:ST3_emu:INFO: Chip address: 0x2
11:40:37:ST3_emu:INFO: Chip address: 0x3
11:40:37:ST3_emu:INFO: Chip address: 0x4
11:40:37:ST3_emu:INFO: Chip address: 0x5
11:40:37:ST3_emu:INFO: Chip address: 0x6
11:40:37:ST3_emu:INFO: Chip address: 0x7
11:40:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:40:38:febtest:INFO: 0-0 | XA-000-08-001-064-041-200-08 | 40.9 | 1183.3
11:40:38:febtest:INFO: 0-1 | XA-000-08-002-000-006-213-03 | 28.2 | 1218.6
11:40:38:febtest:INFO: 0-2 | XA-000-08-001-064-041-136-13 | 50.4 | 1141.9
11:40:39:febtest:INFO: 0-3 | XA-000-08-002-000-006-216-03 | 50.4 | 1153.7
11:40:39:febtest:INFO: 0-4 | XA-000-08-001-064-042-192-06 | 40.9 | 1183.3
11:40:39:febtest:INFO: 0-5 | XA-000-08-002-000-006-215-03 | 34.6 | 1212.7
11:40:39:febtest:INFO: 0-6 | XA-000-08-002-000-006-217-03 | 37.7 | 1183.3
11:40:40:febtest:INFO: 0-7 | XA-000-08-002-000-006-218-03 | 44.1 | 1171.5
11:40:40:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:40:43:ST3_smx:INFO: chip: 0-0 47.250730 C 1147.806000 mV
11:40:43:ST3_smx:INFO: # loops 0
11:40:45:ST3_smx:INFO: # loops 1
11:40:46:ST3_smx:INFO: # loops 2
11:40:48:ST3_smx:INFO: # loops 3
11:40:50:ST3_smx:INFO: # loops 4
11:40:51:ST3_smx:INFO: Total # of broken channels: 0
11:40:51:ST3_smx:INFO: List of broken channels: []
11:40:51:ST3_smx:INFO: Total # of broken channels: 0
11:40:51:ST3_smx:INFO: List of broken channels: []
11:40:52:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:40:56:ST3_smx:INFO: chip: 0-1 31.389742 C 1195.082160 mV
11:40:56:ST3_smx:INFO: # loops 0
11:40:58:ST3_smx:INFO: # loops 1
11:40:59:ST3_smx:INFO: # loops 2
11:41:01:ST3_smx:INFO: # loops 3
11:41:03:ST3_smx:INFO: # loops 4
11:41:04:ST3_smx:INFO: Total # of broken channels: 0
11:41:04:ST3_smx:INFO: List of broken channels: []
11:41:04:ST3_smx:INFO: Total # of broken channels: 0
11:41:04:ST3_smx:INFO: List of broken channels: []
11:41:05:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:41:09:ST3_smx:INFO: chip: 0-2 47.250730 C 1153.732915 mV
11:41:09:ST3_smx:INFO: # loops 0
11:41:10:ST3_smx:INFO: # loops 1
11:41:12:ST3_smx:INFO: # loops 2
11:41:14:ST3_smx:INFO: # loops 3
11:41:15:ST3_smx:INFO: # loops 4
11:41:17:ST3_smx:INFO: Total # of broken channels: 0
11:41:17:ST3_smx:INFO: List of broken channels: []
11:41:17:ST3_smx:INFO: Total # of broken channels: 0
11:41:17:ST3_smx:INFO: List of broken channels: []
11:41:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:41:21:ST3_smx:INFO: chip: 0-3 40.898880 C 1159.654860 mV
11:41:21:ST3_smx:INFO: # loops 0
11:41:23:ST3_smx:INFO: # loops 1
11:41:25:ST3_smx:INFO: # loops 2
11:41:26:ST3_smx:INFO: # loops 3
11:41:28:ST3_smx:INFO: # loops 4
11:41:30:ST3_smx:INFO: Total # of broken channels: 0
11:41:30:ST3_smx:INFO: List of broken channels: []
11:41:30:ST3_smx:INFO: Total # of broken channels: 5
11:41:30:ST3_smx:INFO: List of broken channels: [37, 39, 41, 43, 45]
11:41:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:41:34:ST3_smx:INFO: chip: 0-4 44.073563 C 1153.732915 mV
11:41:34:ST3_smx:INFO: # loops 0
11:41:36:ST3_smx:INFO: # loops 1
11:41:37:ST3_smx:INFO: # loops 2
11:41:39:ST3_smx:INFO: # loops 3
11:41:41:ST3_smx:INFO: # loops 4
11:41:42:ST3_smx:INFO: Total # of broken channels: 0
11:41:42:ST3_smx:INFO: List of broken channels: []
11:41:42:ST3_smx:INFO: Total # of broken channels: 0
11:41:42:ST3_smx:INFO: List of broken channels: []
11:41:43:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:41:47:ST3_smx:INFO: chip: 0-5 40.898880 C 1183.292940 mV
11:41:47:ST3_smx:INFO: # loops 0
11:41:48:ST3_smx:INFO: # loops 1
11:41:50:ST3_smx:INFO: # loops 2
11:41:52:ST3_smx:INFO: # loops 3
11:41:53:ST3_smx:INFO: # loops 4
11:41:55:ST3_smx:INFO: Total # of broken channels: 0
11:41:55:ST3_smx:INFO: List of broken channels: []
11:41:55:ST3_smx:INFO: Total # of broken channels: 0
11:41:55:ST3_smx:INFO: List of broken channels: []
11:41:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:41:59:ST3_smx:INFO: chip: 0-6 34.556970 C 1195.082160 mV
11:41:59:ST3_smx:INFO: # loops 0
11:42:01:ST3_smx:INFO: # loops 1
11:42:02:ST3_smx:INFO: # loops 2
11:42:04:ST3_smx:INFO: # loops 3
11:42:05:ST3_smx:INFO: # loops 4
11:42:07:ST3_smx:INFO: Total # of broken channels: 1
11:42:07:ST3_smx:INFO: List of broken channels: [121]
11:42:07:ST3_smx:INFO: Total # of broken channels: 1
11:42:07:ST3_smx:INFO: List of broken channels: [121]
11:42:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:42:11:ST3_smx:INFO: chip: 0-7 37.726682 C 1177.390875 mV
11:42:11:ST3_smx:INFO: # loops 0
11:42:13:ST3_smx:INFO: # loops 1
11:42:14:ST3_smx:INFO: # loops 2
11:42:16:ST3_smx:INFO: # loops 3
11:42:17:ST3_smx:INFO: # loops 4
11:42:19:ST3_smx:INFO: Total # of broken channels: 0
11:42:19:ST3_smx:INFO: List of broken channels: []
11:42:19:ST3_smx:INFO: Total # of broken channels: 0
11:42:19:ST3_smx:INFO: List of broken channels: []
11:42:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:42:20:febtest:INFO: 0-0 | XA-000-08-001-064-041-200-08 | 50.4 | 1135.9
11:42:20:febtest:INFO: 0-1 | XA-000-08-002-000-006-213-03 | 34.6 | 1189.2
11:42:20:febtest:INFO: 0-2 | XA-000-08-001-064-041-136-13 | 47.3 | 1141.9
11:42:20:febtest:INFO: 0-3 | XA-000-08-002-000-006-216-03 | 47.3 | 1153.7
11:42:21:febtest:INFO: 0-4 | XA-000-08-001-064-042-192-06 | 47.3 | 1147.8
11:42:21:febtest:INFO: 0-5 | XA-000-08-002-000-006-215-03 | 44.1 | 1177.4
11:42:21:febtest:INFO: 0-6 | XA-000-08-002-000-006-217-03 | 34.6 | 1189.2
11:42:21:febtest:INFO: 0-7 | XA-000-08-002-000-006-218-03 | 40.9 | 1177.4
11:43:03:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1010/A//TestDate_2023_08_17-11_40_25/