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FEB_1012 22.11.24 14:40:13
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14:40:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:40:13:ST3_Shared:INFO: FEB-ASIC
14:40:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:40:13:febtest:INFO: Testing FEB with SN 1012
14:40:15:smx_tester:INFO: Scanning setup
14:40:15:elinks:INFO: Disabling clock on downlink 0
14:40:15:elinks:INFO: Disabling clock on downlink 1
14:40:15:elinks:INFO: Disabling clock on downlink 2
14:40:15:elinks:INFO: Disabling clock on downlink 3
14:40:15:elinks:INFO: Disabling clock on downlink 4
14:40:15:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:40:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:15:elinks:INFO: Disabling clock on downlink 0
14:40:15:elinks:INFO: Disabling clock on downlink 1
14:40:15:elinks:INFO: Disabling clock on downlink 2
14:40:15:elinks:INFO: Disabling clock on downlink 3
14:40:15:elinks:INFO: Disabling clock on downlink 4
14:40:15:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
14:40:15:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
14:40:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:15:elinks:INFO: Disabling clock on downlink 0
14:40:15:elinks:INFO: Disabling clock on downlink 1
14:40:15:elinks:INFO: Disabling clock on downlink 2
14:40:15:elinks:INFO: Disabling clock on downlink 3
14:40:15:elinks:INFO: Disabling clock on downlink 4
14:40:15:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:40:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:15:elinks:INFO: Disabling clock on downlink 0
14:40:15:elinks:INFO: Disabling clock on downlink 1
14:40:15:elinks:INFO: Disabling clock on downlink 2
14:40:15:elinks:INFO: Disabling clock on downlink 3
14:40:15:elinks:INFO: Disabling clock on downlink 4
14:40:15:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:40:15:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:40:15:elinks:INFO: Disabling clock on downlink 0
14:40:15:elinks:INFO: Disabling clock on downlink 1
14:40:15:elinks:INFO: Disabling clock on downlink 2
14:40:15:elinks:INFO: Disabling clock on downlink 3
14:40:15:elinks:INFO: Disabling clock on downlink 4
14:40:15:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:40:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:40:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:40:16:setup_element:INFO: Scanning clock phase
14:40:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:40:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:40:16:setup_element:INFO: Clock phase scan results for group 0, downlink 1
14:40:16:setup_element:INFO: Eye window for uplink 0 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:40:16:setup_element:INFO: Eye window for uplink 1 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:40:16:setup_element:INFO: Eye window for uplink 2 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 3 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:40:16:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:40:16:setup_element:INFO: Eye window for uplink 6 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 7 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
14:40:16:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
14:40:16:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 12: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:40:16:setup_element:INFO: Eye window for uplink 13: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:40:16:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:40:16:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:40:16:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
14:40:16:setup_element:INFO: Scanning data phases
14:40:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:40:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:40:22:setup_element:INFO: Data phase scan results for group 0, downlink 1
14:40:22:setup_element:INFO: Eye window for uplink 0 : ____________XXXXXX______________________
Data delay found: 34
14:40:22:setup_element:INFO: Eye window for uplink 1 : _______XXXXXXX__________________________
Data delay found: 30
14:40:22:setup_element:INFO: Eye window for uplink 2 : _____XXXXXXXX___________________________
Data delay found: 28
14:40:22:setup_element:INFO: Eye window for uplink 3 : __XXXXXXXX______________________________
Data delay found: 25
14:40:22:setup_element:INFO: Eye window for uplink 4 : _____XXXXXXX____________________________
Data delay found: 28
14:40:22:setup_element:INFO: Eye window for uplink 5 : _XXXXXX_________________________________
Data delay found: 23
14:40:22:setup_element:INFO: Eye window for uplink 6 : XXXX________________________________XXXX
Data delay found: 19
14:40:22:setup_element:INFO: Eye window for uplink 7 : X________________________________XXXXXX_
Data delay found: 16
14:40:22:setup_element:INFO: Eye window for uplink 8 : ________________________XXXXXX__________
Data delay found: 6
14:40:22:setup_element:INFO: Eye window for uplink 9 : ____________________________XXXXXXXX____
Data delay found: 11
14:40:22:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXXXX______
Data delay found: 9
14:40:22:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXXXX__
Data delay found: 14
14:40:22:setup_element:INFO: Eye window for uplink 12: _________________________XXXXXX_________
Data delay found: 7
14:40:22:setup_element:INFO: Eye window for uplink 13: __________________________X_XXXXXXXX____
Data delay found: 10
14:40:22:setup_element:INFO: Eye window for uplink 14: _________________________XXXXXXXXX______
Data delay found: 9
14:40:22:setup_element:INFO: Eye window for uplink 15: ____________________________XXXXXXX_____
Data delay found: 11
14:40:22:setup_element:INFO: Setting the data phase to 34 for uplink 0
14:40:22:setup_element:INFO: Setting the data phase to 30 for uplink 1
14:40:22:setup_element:INFO: Setting the data phase to 28 for uplink 2
14:40:22:setup_element:INFO: Setting the data phase to 25 for uplink 3
14:40:22:setup_element:INFO: Setting the data phase to 28 for uplink 4
14:40:22:setup_element:INFO: Setting the data phase to 23 for uplink 5
14:40:22:setup_element:INFO: Setting the data phase to 19 for uplink 6
14:40:22:setup_element:INFO: Setting the data phase to 16 for uplink 7
14:40:22:setup_element:INFO: Setting the data phase to 6 for uplink 8
14:40:22:setup_element:INFO: Setting the data phase to 11 for uplink 9
14:40:22:setup_element:INFO: Setting the data phase to 9 for uplink 10
14:40:22:setup_element:INFO: Setting the data phase to 14 for uplink 11
14:40:22:setup_element:INFO: Setting the data phase to 7 for uplink 12
14:40:22:setup_element:INFO: Setting the data phase to 10 for uplink 13
14:40:22:setup_element:INFO: Setting the data phase to 9 for uplink 14
14:40:22:setup_element:INFO: Setting the data phase to 11 for uplink 15
==============================================OOO==============================================
14:40:22:setup_element:INFO: Beginning SMX ASICs map scan
14:40:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:40:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:40:22:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:40:22:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
14:40:22:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:40:22:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:40:22:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:40:22:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:40:22:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:40:22:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:40:22:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:40:22:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:40:22:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:40:23:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:40:23:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:40:23:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:40:23:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:40:23:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:40:23:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:40:23:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:40:23:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:40:24:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXX__
Uplink 1: _______________________________________________________________________XXXXXXX__
Uplink 2: ______________________________________________________________________XXXXXXX___
Uplink 3: ______________________________________________________________________XXXXXXX___
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ______________________________________________________________________XXXXXXX___
Uplink 7: ______________________________________________________________________XXXXXXX___
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ____________________________________________________________________XXXXXXXXX___
Uplink 13: ____________________________________________________________________XXXXXXXXX___
Uplink 14: ______________________________________________________________________XXXXXXX___
Uplink 15: ______________________________________________________________________XXXXXXX___
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 1:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 2:
Optimal Phase: 28
Window Length: 32
Eye Window: _____XXXXXXXX___________________________
Uplink 3:
Optimal Phase: 25
Window Length: 32
Eye Window: __XXXXXXXX______________________________
Uplink 4:
Optimal Phase: 28
Window Length: 33
Eye Window: _____XXXXXXX____________________________
Uplink 5:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
Uplink 7:
Optimal Phase: 16
Window Length: 32
Eye Window: X________________________________XXXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 34
Eye Window: ________________________XXXXXX__________
Uplink 9:
Optimal Phase: 11
Window Length: 32
Eye Window: ____________________________XXXXXXXX____
Uplink 10:
Optimal Phase: 9
Window Length: 32
Eye Window: __________________________XXXXXXXX______
Uplink 11:
Optimal Phase: 14
Window Length: 33
Eye Window: _______________________________XXXXXXX__
Uplink 12:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 13:
Optimal Phase: 10
Window Length: 30
Eye Window: __________________________X_XXXXXXXX____
Uplink 14:
Optimal Phase: 9
Window Length: 31
Eye Window: _________________________XXXXXXXXX______
Uplink 15:
Optimal Phase: 11
Window Length: 33
Eye Window: ____________________________XXXXXXX_____
==============================================OOO==============================================
14:40:24:setup_element:INFO: Performing Elink synchronization
14:40:24:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:40:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:40:24:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:40:24:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
14:40:24:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
14:40:24:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:40:25:febtest:INFO: Init all SMX (CSA): 30
14:40:40:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:40:40:febtest:INFO: 01-00 | XA-000-08-002-001-006-160-07 | 40.9 | 1141.9
14:40:40:febtest:INFO: 08-01 | XA-000-08-002-001-006-165-07 | 40.9 | 1153.7
14:40:40:febtest:INFO: 03-02 | XA-000-08-002-001-006-175-07 | 28.2 | 1195.1
14:40:41:febtest:INFO: 10-03 | XA-000-08-002-001-006-179-00 | 40.9 | 1147.8
14:40:41:febtest:INFO: 05-04 | XA-000-08-002-001-006-178-00 | 40.9 | 1153.7
14:40:41:febtest:INFO: 12-05 | XA-000-08-002-001-006-174-07 | 21.9 | 1218.6
14:40:41:febtest:INFO: 07-06 | XA-000-08-002-001-006-167-07 | 34.6 | 1177.4
14:40:41:febtest:INFO: 14-07 | XA-000-08-002-001-006-162-07 | 31.4 | 1201.0
14:40:42:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:40:45:ST3_smx:INFO: chip: 1-0 40.898880 C 1153.732915 mV
14:40:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:45:ST3_smx:INFO: Electrons
14:40:45:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:40:47:ST3_smx:INFO: ----> Checking Analog response
14:40:47:ST3_smx:INFO: ----> Checking broken channels
14:40:48:ST3_smx:INFO: Total # broken ch: 0
14:40:48:ST3_smx:INFO: List FAST: []
14:40:48:ST3_smx:INFO: List SLOW: []
14:40:49:ST3_smx:INFO: chip: 8-1 40.898880 C 1165.571835 mV
14:40:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:49:ST3_smx:INFO: Electrons
14:40:49:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:40:52:ST3_smx:INFO: ----> Checking Analog response
14:40:52:ST3_smx:INFO: ----> Checking broken channels
14:40:52:ST3_smx:INFO: Total # broken ch: 0
14:40:52:ST3_smx:INFO: List FAST: []
14:40:52:ST3_smx:INFO: List SLOW: []
14:40:54:ST3_smx:INFO: chip: 3-2 28.225000 C 1212.728715 mV
14:40:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:54:ST3_smx:INFO: Electrons
14:40:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:40:56:ST3_smx:INFO: ----> Checking Analog response
14:40:56:ST3_smx:INFO: ----> Checking broken channels
14:40:56:ST3_smx:INFO: Total # broken ch: 0
14:40:56:ST3_smx:INFO: List FAST: []
14:40:56:ST3_smx:INFO: List SLOW: []
14:40:58:ST3_smx:INFO: chip: 10-3 40.898880 C 1159.654860 mV
14:40:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:40:58:ST3_smx:INFO: Electrons
14:40:58:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:41:01:ST3_smx:INFO: ----> Checking Analog response
14:41:01:ST3_smx:INFO: ----> Checking broken channels
14:41:01:ST3_smx:INFO: Total # broken ch: 0
14:41:01:ST3_smx:INFO: List FAST: []
14:41:01:ST3_smx:INFO: List SLOW: []
14:41:03:ST3_smx:INFO: chip: 5-4 40.898880 C 1165.571835 mV
14:41:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:03:ST3_smx:INFO: Electrons
14:41:03:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:41:05:ST3_smx:INFO: ----> Checking Analog response
14:41:05:ST3_smx:INFO: ----> Checking broken channels
14:41:06:ST3_smx:INFO: Total # broken ch: 0
14:41:06:ST3_smx:INFO: List FAST: []
14:41:06:ST3_smx:INFO: List SLOW: []
14:41:07:ST3_smx:INFO: chip: 12-5 25.062742 C 1230.330540 mV
14:41:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:07:ST3_smx:INFO: Electrons
14:41:07:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:41:10:ST3_smx:INFO: ----> Checking Analog response
14:41:10:ST3_smx:INFO: ----> Checking broken channels
14:41:10:ST3_smx:INFO: Total # broken ch: 0
14:41:10:ST3_smx:INFO: List FAST: []
14:41:10:ST3_smx:INFO: List SLOW: []
14:41:12:ST3_smx:INFO: chip: 7-6 37.726682 C 1189.190035 mV
14:41:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:12:ST3_smx:INFO: Electrons
14:41:12:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:41:14:ST3_smx:INFO: ----> Checking Analog response
14:41:14:ST3_smx:INFO: ----> Checking broken channels
14:41:14:ST3_smx:INFO: Total # broken ch: 0
14:41:14:ST3_smx:INFO: List FAST: []
14:41:14:ST3_smx:INFO: List SLOW: []
14:41:16:ST3_smx:INFO: chip: 14-7 31.389742 C 1212.728715 mV
14:41:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:41:16:ST3_smx:INFO: Electrons
14:41:16:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:41:18:ST3_smx:INFO: ----> Checking Analog response
14:41:18:ST3_smx:INFO: ----> Checking broken channels
14:41:19:ST3_smx:INFO: Total # broken ch: 0
14:41:19:ST3_smx:INFO: List FAST: []
14:41:19:ST3_smx:INFO: List SLOW: []
14:41:19:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:41:19:febtest:INFO: 01-00 | XA-000-08-002-001-006-160-07 | 40.9 | 1171.5
14:41:19:febtest:INFO: 08-01 | XA-000-08-002-001-006-165-07 | 40.9 | 1189.2
14:41:19:febtest:INFO: 03-02 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
14:41:20:febtest:INFO: 10-03 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
14:41:20:febtest:INFO: 05-04 | XA-000-08-002-001-006-178-00 | 44.1 | 1183.3
14:41:20:febtest:INFO: 12-05 | XA-000-08-002-001-006-174-07 | 25.1 | 1253.7
14:41:20:febtest:INFO: 07-06 | XA-000-08-002-001-006-167-07 | 37.7 | 1206.9
14:41:20:febtest:INFO: 14-07 | XA-000-08-002-001-006-162-07 | 34.6 | 1230.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_11_22-14_40_13
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1012| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
MODULE_NAME
------------------------------------------------------------
VI_before_Init : ['2.449', '1.3860', '1.849', '2.3340', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9830', '1.850', '2.3020', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9520', '1.850', '0.5160', '0.000', '0.0000', '0.000', '0.0000']