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FEB_1012 28.08.23 11:23:29
Info
11:22:47:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:23:29:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:23:29:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:23:29:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:23:29:febtest:INFO: Tsting FEB with SN 1012
11:23:30:smx_tester:INFO: Scanning setup
11:23:30:elinks:INFO: Disabling clock on downlink 0
11:23:30:elinks:INFO: Disabling clock on downlink 1
11:23:30:elinks:INFO: Disabling clock on downlink 2
11:23:30:elinks:INFO: Disabling clock on downlink 3
11:23:30:elinks:INFO: Disabling clock on downlink 4
11:23:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:23:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:23:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:23:30:elinks:INFO: Disabling clock on downlink 0
11:23:30:elinks:INFO: Disabling clock on downlink 1
11:23:30:elinks:INFO: Disabling clock on downlink 2
11:23:30:elinks:INFO: Disabling clock on downlink 3
11:23:30:elinks:INFO: Disabling clock on downlink 4
11:23:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:23:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:23:30:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:23:30:elinks:INFO: Disabling clock on downlink 0
11:23:30:elinks:INFO: Disabling clock on downlink 1
11:23:30:elinks:INFO: Disabling clock on downlink 2
11:23:30:elinks:INFO: Disabling clock on downlink 3
11:23:30:elinks:INFO: Disabling clock on downlink 4
11:23:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:23:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:23:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:23:31:elinks:INFO: Disabling clock on downlink 0
11:23:31:elinks:INFO: Disabling clock on downlink 1
11:23:31:elinks:INFO: Disabling clock on downlink 2
11:23:31:elinks:INFO: Disabling clock on downlink 3
11:23:31:elinks:INFO: Disabling clock on downlink 4
11:23:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:23:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 16
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 17
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 18
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 19
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 20
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 21
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 22
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 23
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
11:23:31:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
11:23:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:23:31:elinks:INFO: Disabling clock on downlink 0
11:23:31:elinks:INFO: Disabling clock on downlink 1
11:23:31:elinks:INFO: Disabling clock on downlink 2
11:23:31:elinks:INFO: Disabling clock on downlink 3
11:23:31:elinks:INFO: Disabling clock on downlink 4
11:23:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:23:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:23:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:23:31:setup_element:INFO: Scanning clock phase
11:23:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:23:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:23:31:setup_element:INFO: Clock phase scan results for group 0, downlink 3
11:23:31:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:23:31:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
11:23:31:setup_element:INFO: Eye window for uplink 18: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 19: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 20: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 21: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 22: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 23: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
11:23:31:setup_element:INFO: Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
11:23:31:setup_element:INFO: Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 28: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:23:31:setup_element:INFO: Eye window for uplink 29: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
11:23:31:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:23:31:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:23:31:setup_element:INFO: Setting the clock phase to 31 for group 0, downlink 3
11:23:31:setup_element:INFO: Scanning data phases
11:23:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:23:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:23:37:setup_element:INFO: Data phase scan results for group 0, downlink 3
11:23:37:setup_element:INFO: Eye window for uplink 16: _________________XXXX___________________
Data delay found: 38
11:23:37:setup_element:INFO: Eye window for uplink 17: ____________XXXXX_______________________
Data delay found: 34
11:23:37:setup_element:INFO: Eye window for uplink 18: __________XXXXXX________________________
Data delay found: 32
11:23:37:setup_element:INFO: Eye window for uplink 19: ________XXXXX___________________________
Data delay found: 30
11:23:37:setup_element:INFO: Eye window for uplink 20: _________XXXX___________________________
Data delay found: 30
11:23:37:setup_element:INFO: Eye window for uplink 21: _______XXXXX____________________________
Data delay found: 29
11:23:37:setup_element:INFO: Eye window for uplink 22: _____XXXX_______________________________
Data delay found: 26
11:23:37:setup_element:INFO: Eye window for uplink 23: __XXXX__________________________________
Data delay found: 23
11:23:37:setup_element:INFO: Eye window for uplink 24: X__________________________________XXXXX
Data delay found: 17
11:23:37:setup_element:INFO: Eye window for uplink 25: XXXX__________________________________XX
Data delay found: 20
11:23:37:setup_element:INFO: Eye window for uplink 26: X__________________________________XXXX_
Data delay found: 17
11:23:37:setup_element:INFO: Eye window for uplink 27: XXXXX__________________________________X
Data delay found: 21
11:23:37:setup_element:INFO: Eye window for uplink 28: __________________________________XXXXX_
Data delay found: 16
11:23:37:setup_element:INFO: Eye window for uplink 29: XX__________________________________XXXX
Data delay found: 18
11:23:37:setup_element:INFO: Eye window for uplink 30: XX_________________________________XXXXX
Data delay found: 18
11:23:37:setup_element:INFO: Eye window for uplink 31: XX________________________________XXXXX_
Data delay found: 17
11:23:37:setup_element:INFO: Setting the data phase to 38 for uplink 16
11:23:37:setup_element:INFO: Setting the data phase to 34 for uplink 17
11:23:37:setup_element:INFO: Setting the data phase to 32 for uplink 18
11:23:37:setup_element:INFO: Setting the data phase to 30 for uplink 19
11:23:37:setup_element:INFO: Setting the data phase to 30 for uplink 20
11:23:37:setup_element:INFO: Setting the data phase to 29 for uplink 21
11:23:37:setup_element:INFO: Setting the data phase to 26 for uplink 22
11:23:37:setup_element:INFO: Setting the data phase to 23 for uplink 23
11:23:37:setup_element:INFO: Setting the data phase to 17 for uplink 24
11:23:37:setup_element:INFO: Setting the data phase to 20 for uplink 25
11:23:37:setup_element:INFO: Setting the data phase to 17 for uplink 26
11:23:37:setup_element:INFO: Setting the data phase to 21 for uplink 27
11:23:37:setup_element:INFO: Setting the data phase to 16 for uplink 28
11:23:37:setup_element:INFO: Setting the data phase to 18 for uplink 29
11:23:37:setup_element:INFO: Setting the data phase to 18 for uplink 30
11:23:37:setup_element:INFO: Setting the data phase to 17 for uplink 31
11:23:37:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 71
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: ____________________________________________________________________XXXXXXX_____
Uplink 19: ____________________________________________________________________XXXXXXX_____
Uplink 20: ____________________________________________________________________XXXXXXXX____
Uplink 21: ____________________________________________________________________XXXXXXXX____
Uplink 22: _____________________________________________________________________XXXXXX_____
Uplink 23: _____________________________________________________________________XXXXXX_____
Uplink 24: ___________________________________________________________________XXXXXXXX_____
Uplink 25: ___________________________________________________________________XXXXXXXX_____
Uplink 26: ____________________________________________________________________XXXXXXXX____
Uplink 27: ____________________________________________________________________XXXXXXXX____
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ____________________________________________________________________XXXXXXX_____
Uplink 31: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 16:
Optimal Phase: 38
Window Length: 36
Eye Window: _________________XXXX___________________
Uplink 17:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 18:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 19:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 20:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 21:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 22:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 23:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 24:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 26:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 27:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 28:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 29:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 30:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 31:
Optimal Phase: 17
Window Length: 32
Eye Window: XX________________________________XXXXX_
]
11:23:37:setup_element:INFO: Beginning SMX ASICs map scan
11:23:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:23:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:23:37:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:23:37:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:23:37:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:23:37:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 17
11:23:37:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 16
11:23:37:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
11:23:37:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
11:23:38:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 19
11:23:38:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 18
11:23:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
11:23:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
11:23:38:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 21
11:23:38:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 20
11:23:38:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
11:23:38:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
11:23:38:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 23
11:23:38:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 22
11:23:38:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
11:23:38:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
11:23:40:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 71
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: ____________________________________________________________________XXXXXXX_____
Uplink 19: ____________________________________________________________________XXXXXXX_____
Uplink 20: ____________________________________________________________________XXXXXXXX____
Uplink 21: ____________________________________________________________________XXXXXXXX____
Uplink 22: _____________________________________________________________________XXXXXX_____
Uplink 23: _____________________________________________________________________XXXXXX_____
Uplink 24: ___________________________________________________________________XXXXXXXX_____
Uplink 25: ___________________________________________________________________XXXXXXXX_____
Uplink 26: ____________________________________________________________________XXXXXXXX____
Uplink 27: ____________________________________________________________________XXXXXXXX____
Uplink 28: ___________________________________________________________________XXXXXXX______
Uplink 29: ___________________________________________________________________XXXXXXX______
Uplink 30: ____________________________________________________________________XXXXXXX_____
Uplink 31: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 16:
Optimal Phase: 38
Window Length: 36
Eye Window: _________________XXXX___________________
Uplink 17:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 18:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 19:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 20:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 21:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 22:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 23:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 24:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 26:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 27:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 28:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 29:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 30:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 31:
Optimal Phase: 17
Window Length: 32
Eye Window: XX________________________________XXXXX_
11:23:40:setup_element:INFO: Performing Elink synchronization
11:23:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:23:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
11:23:40:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
11:23:40:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
11:23:40:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
11:23:40:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
11:23:40:ST3_emu:INFO: Number of chips: 8
11:23:40:ST3_emu:INFO: Chip address: 0x0
11:23:40:ST3_emu:INFO: Chip address: 0x1
11:23:40:ST3_emu:INFO: Chip address: 0x2
11:23:40:ST3_emu:INFO: Chip address: 0x3
11:23:40:ST3_emu:INFO: Chip address: 0x4
11:23:40:ST3_emu:INFO: Chip address: 0x5
11:23:40:ST3_emu:INFO: Chip address: 0x6
11:23:40:ST3_emu:INFO: Chip address: 0x7
11:23:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:41:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 31.4 | 1195.1
11:23:41:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 37.7 | 1201.0
11:23:41:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1236.2
11:23:42:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 44.1 | 1177.4
11:23:42:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1177.4
11:23:42:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 12.4 | 1288.7
11:23:42:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1206.9
11:23:42:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 25.1 | 1236.2
11:23:42:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:46:ST3_smx:INFO: chip: 0-0 37.726682 C 1165.571835 mV
11:23:46:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:46:ST3_smx:INFO: Electrons
11:23:46:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:48:ST3_smx:INFO: ----> Checking Analog response
11:23:48:ST3_smx:INFO: ----> Checking broken channels
11:23:49:ST3_smx:INFO: Total # broken ch: 0
11:23:49:ST3_smx:INFO: List FAST: []
11:23:49:ST3_smx:INFO: List SLOW: []
11:23:49:ST3_smx:INFO: Holes
11:23:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:51:ST3_smx:INFO: ----> Checking Analog response
11:23:51:ST3_smx:INFO: ----> Checking broken channels
11:23:51:ST3_smx:INFO: Total # broken ch: 0
11:23:51:ST3_smx:INFO: List FAST: []
11:23:51:ST3_smx:INFO: List SLOW: []
11:23:51:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:23:51:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 40.9 | 1159.7
11:23:51:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 37.7 | 1201.0
11:23:52:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1236.2
11:23:52:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 44.1 | 1177.4
11:23:52:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1177.4
11:23:52:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 12.4 | 1288.7
11:23:52:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1206.9
11:23:53:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 25.1 | 1236.2
11:23:53:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:23:57:ST3_smx:INFO: chip: 0-1 44.073563 C 1165.571835 mV
11:23:57:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:23:57:ST3_smx:INFO: Electrons
11:23:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:23:59:ST3_smx:INFO: ----> Checking Analog response
11:23:59:ST3_smx:INFO: ----> Checking broken channels
11:23:59:ST3_smx:INFO: Total # broken ch: 0
11:23:59:ST3_smx:INFO: List FAST: []
11:23:59:ST3_smx:INFO: List SLOW: []
11:23:59:ST3_smx:INFO: Holes
11:23:59:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:01:ST3_smx:INFO: ----> Checking Analog response
11:24:01:ST3_smx:INFO: ----> Checking broken channels
11:24:01:ST3_smx:INFO: Total # broken ch: 0
11:24:01:ST3_smx:INFO: List FAST: []
11:24:01:ST3_smx:INFO: List SLOW: []
11:24:01:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:02:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1159.7
11:24:02:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 47.3 | 1159.7
11:24:02:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1236.2
11:24:02:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 44.1 | 1177.4
11:24:03:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 40.9 | 1177.4
11:24:03:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 12.4 | 1288.7
11:24:03:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1206.9
11:24:03:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 28.2 | 1236.2
11:24:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:24:07:ST3_smx:INFO: chip: 0-2 28.225000 C 1218.600960 mV
11:24:07:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:24:07:ST3_smx:INFO: Electrons
11:24:07:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:09:ST3_smx:INFO: ----> Checking Analog response
11:24:09:ST3_smx:INFO: ----> Checking broken channels
11:24:10:ST3_smx:INFO: Total # broken ch: 0
11:24:10:ST3_smx:INFO: List FAST: []
11:24:10:ST3_smx:INFO: List SLOW: []
11:24:10:ST3_smx:INFO: Holes
11:24:10:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:12:ST3_smx:INFO: ----> Checking Analog response
11:24:12:ST3_smx:INFO: ----> Checking broken channels
11:24:12:ST3_smx:INFO: Total # broken ch: 0
11:24:12:ST3_smx:INFO: List FAST: []
11:24:12:ST3_smx:INFO: List SLOW: []
11:24:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:12:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1159.7
11:24:12:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 47.3 | 1165.6
11:24:13:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1206.9
11:24:13:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1177.4
11:24:13:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 40.9 | 1171.5
11:24:13:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 12.4 | 1288.7
11:24:13:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1206.9
11:24:14:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 25.1 | 1236.2
11:24:14:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:24:18:ST3_smx:INFO: chip: 0-3 47.250730 C 1153.732915 mV
11:24:18:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:24:18:ST3_smx:INFO: Electrons
11:24:18:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:20:ST3_smx:INFO: ----> Checking Analog response
11:24:20:ST3_smx:INFO: ----> Checking broken channels
11:24:20:ST3_smx:INFO: Total # broken ch: 0
11:24:20:ST3_smx:INFO: List FAST: []
11:24:20:ST3_smx:INFO: List SLOW: []
11:24:20:ST3_smx:INFO: Holes
11:24:20:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:22:ST3_smx:INFO: ----> Checking Analog response
11:24:22:ST3_smx:INFO: ----> Checking broken channels
11:24:23:ST3_smx:INFO: Total # broken ch: 0
11:24:23:ST3_smx:INFO: List FAST: []
11:24:23:ST3_smx:INFO: List SLOW: []
11:24:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:23:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1159.7
11:24:23:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 47.3 | 1159.7
11:24:23:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1212.7
11:24:23:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 50.4 | 1153.7
11:24:24:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 40.9 | 1171.5
11:24:24:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1282.9
11:24:24:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1206.9
11:24:24:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 25.1 | 1236.2
11:24:25:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:24:28:ST3_smx:INFO: chip: 0-4 44.073563 C 1153.732915 mV
11:24:28:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:24:28:ST3_smx:INFO: Electrons
11:24:28:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:30:ST3_smx:INFO: ----> Checking Analog response
11:24:30:ST3_smx:INFO: ----> Checking broken channels
11:24:31:ST3_smx:INFO: Total # broken ch: 0
11:24:31:ST3_smx:INFO: List FAST: []
11:24:31:ST3_smx:INFO: List SLOW: []
11:24:31:ST3_smx:INFO: Holes
11:24:31:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:33:ST3_smx:INFO: ----> Checking Analog response
11:24:33:ST3_smx:INFO: ----> Checking broken channels
11:24:33:ST3_smx:INFO: Total # broken ch: 0
11:24:33:ST3_smx:INFO: List FAST: []
11:24:33:ST3_smx:INFO: List SLOW: []
11:24:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:33:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1159.7
11:24:33:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 50.4 | 1159.7
11:24:34:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1212.7
11:24:34:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 50.4 | 1153.7
11:24:34:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 47.3 | 1153.7
11:24:34:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1282.9
11:24:35:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1201.0
11:24:35:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 28.2 | 1236.2
11:24:35:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:24:39:ST3_smx:INFO: chip: 0-5 28.225000 C 1224.468235 mV
11:24:39:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:24:39:ST3_smx:INFO: Electrons
11:24:39:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:41:ST3_smx:INFO: ----> Checking Analog response
11:24:41:ST3_smx:INFO: ----> Checking broken channels
11:24:41:ST3_smx:INFO: Total # broken ch: 0
11:24:41:ST3_smx:INFO: List FAST: []
11:24:41:ST3_smx:INFO: List SLOW: []
11:24:41:ST3_smx:INFO: Holes
11:24:41:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:43:ST3_smx:INFO: ----> Checking Analog response
11:24:43:ST3_smx:INFO: ----> Checking broken channels
11:24:44:ST3_smx:INFO: Total # broken ch: 0
11:24:44:ST3_smx:INFO: List FAST: []
11:24:44:ST3_smx:INFO: List SLOW: []
11:24:44:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:44:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1159.7
11:24:44:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 50.4 | 1159.7
11:24:44:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1212.7
11:24:44:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 50.4 | 1147.8
11:24:45:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 47.3 | 1147.8
11:24:45:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 31.4 | 1224.5
11:24:45:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1201.0
11:24:45:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 28.2 | 1230.3
11:24:46:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:24:49:ST3_smx:INFO: chip: 0-6 31.389742 C 1189.190035 mV
11:24:49:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:24:49:ST3_smx:INFO: Electrons
11:24:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:51:ST3_smx:INFO: ----> Checking Analog response
11:24:51:ST3_smx:INFO: ----> Checking broken channels
11:24:52:ST3_smx:INFO: Total # broken ch: 0
11:24:52:ST3_smx:INFO: List FAST: []
11:24:52:ST3_smx:INFO: List SLOW: []
11:24:52:ST3_smx:INFO: Holes
11:24:52:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:24:54:ST3_smx:INFO: ----> Checking Analog response
11:24:54:ST3_smx:INFO: ----> Checking broken channels
11:24:54:ST3_smx:INFO: Total # broken ch: 0
11:24:54:ST3_smx:INFO: List FAST: []
11:24:54:ST3_smx:INFO: List SLOW: []
11:24:54:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:24:54:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 40.9 | 1153.7
11:24:55:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1159.7
11:24:55:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1212.7
11:24:55:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1153.7
11:24:55:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1153.7
11:24:55:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 28.2 | 1224.5
11:24:56:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1189.2
11:24:56:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 28.2 | 1230.3
11:24:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:25:00:ST3_smx:INFO: chip: 0-7 25.062742 C 1230.330540 mV
11:25:00:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:25:00:ST3_smx:INFO: Electrons
11:25:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:25:02:ST3_smx:INFO: ----> Checking Analog response
11:25:02:ST3_smx:INFO: ----> Checking broken channels
11:25:02:ST3_smx:INFO: Total # broken ch: 0
11:25:02:ST3_smx:INFO: List FAST: []
11:25:02:ST3_smx:INFO: List SLOW: []
11:25:02:ST3_smx:INFO: Holes
11:25:02:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:25:04:ST3_smx:INFO: ----> Checking Analog response
11:25:04:ST3_smx:INFO: ----> Checking broken channels
11:25:05:ST3_smx:INFO: Total # broken ch: 0
11:25:05:ST3_smx:INFO: List FAST: []
11:25:05:ST3_smx:INFO: List SLOW: []
11:25:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:25:05:febtest:INFO: 0-0 | XA-000-08-002-001-006-160-07 | 40.9 | 1159.7
11:25:05:febtest:INFO: 0-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1159.7
11:25:05:febtest:INFO: 0-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1212.7
11:25:06:febtest:INFO: 0-3 | XA-000-08-002-001-006-179-00 | 44.1 | 1153.7
11:25:06:febtest:INFO: 0-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1153.7
11:25:06:febtest:INFO: 0-5 | XA-000-08-002-001-006-174-07 | 28.2 | 1218.6
11:25:06:febtest:INFO: 0-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1189.2
11:25:06:febtest:INFO: 0-7 | XA-000-08-002-001-006-162-07 | 25.1 | 1224.5
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_28-11_23_29', 'OPERATOR': 'Oleksandr S.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-162-07', 'FUSED_ID': 6359364699117611559, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.449', '1.3830', '1.846', '2.3090', '6.999', '1.5440', '6.999', '1.5440'], 'VI_aInit': ['2.450', '1.9930', '1.850', '1.4310', '7.000', '1.5330', '7.000', '1.5330'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
11:25:33:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1012/A//TestDate_2023_08_28-11_23_29/