13:52:45:ST3_hmp4040:INFO:	HAMEG,HMP2030,017836163,HW50010002/SW2.30
13:52:45:febtest:INFO:	FEB8.2 selected
13:52:45:febtest:INFO:	FEB8.2 selected
13:52:50:ST3_Shared:INFO:	Listo of operators:Oleksandr S.; 
13:53:05:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
13:53:05:ST3_emu:ERROR:	device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
13:53:08:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
13:53:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:53:10:ST3_Shared:INFO:	--------------------------FEB-ASIC--------------------------
13:53:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:53:10:febtest:INFO:	Tsting FEB with SN 1012
13:53:11:smx_tester:INFO:	Scanning setup
13:53:11:elinks:INFO:	Disabling clock on downlink 0
13:53:11:elinks:INFO:	Disabling clock on downlink 1
13:53:11:elinks:INFO:	Disabling clock on downlink 2
13:53:11:elinks:INFO:	Disabling clock on downlink 3
13:53:11:elinks:INFO:	Disabling clock on downlink 4
13:53:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:53:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:53:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:53:11:elinks:INFO:	Disabling clock on downlink 0
13:53:11:elinks:INFO:	Disabling clock on downlink 1
13:53:11:elinks:INFO:	Disabling clock on downlink 2
13:53:11:elinks:INFO:	Disabling clock on downlink 3
13:53:11:elinks:INFO:	Disabling clock on downlink 4
13:53:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:53:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:53:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:53:12:elinks:INFO:	Disabling clock on downlink 0
13:53:12:elinks:INFO:	Disabling clock on downlink 1
13:53:12:elinks:INFO:	Disabling clock on downlink 2
13:53:12:elinks:INFO:	Disabling clock on downlink 3
13:53:12:elinks:INFO:	Disabling clock on downlink 4
13:53:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:53:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:53:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:53:12:elinks:INFO:	Disabling clock on downlink 0
13:53:12:elinks:INFO:	Disabling clock on downlink 1
13:53:12:elinks:INFO:	Disabling clock on downlink 2
13:53:12:elinks:INFO:	Disabling clock on downlink 3
13:53:12:elinks:INFO:	Disabling clock on downlink 4
13:53:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:53:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 16
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 17
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 18
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 19
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 20
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 21
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 22
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 23
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 24
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 25
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 26
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 27
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 28
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 29
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 30
13:53:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 31
13:53:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:53:12:elinks:INFO:	Disabling clock on downlink 0
13:53:12:elinks:INFO:	Disabling clock on downlink 1
13:53:12:elinks:INFO:	Disabling clock on downlink 2
13:53:12:elinks:INFO:	Disabling clock on downlink 3
13:53:12:elinks:INFO:	Disabling clock on downlink 4
13:53:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:53:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:53:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:53:12:setup_element:INFO:	Scanning clock phase
13:53:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:53:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:53:12:setup_element:INFO:	Clock phase scan results for group 0, downlink 3
13:53:12:setup_element:INFO:	Eye window for uplink 16: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
13:53:12:setup_element:INFO:	Eye window for uplink 17: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
13:53:12:setup_element:INFO:	Eye window for uplink 18: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
13:53:12:setup_element:INFO:	Eye window for uplink 19: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
13:53:12:setup_element:INFO:	Eye window for uplink 20: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
13:53:12:setup_element:INFO:	Eye window for uplink 21: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
13:53:12:setup_element:INFO:	Eye window for uplink 22: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
13:53:12:setup_element:INFO:	Eye window for uplink 23: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
13:53:12:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:53:12:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:53:12:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:53:12:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:53:12:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:53:13:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:53:13:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:53:13:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:53:13:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 3
13:53:13:setup_element:INFO:	Scanning data phases
13:53:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:53:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:53:18:setup_element:INFO:	Data phase scan results for group 0, downlink 3
13:53:18:setup_element:INFO:	Eye window for uplink 16: __________________XXXX__________________
Data delay found: 39
13:53:18:setup_element:INFO:	Eye window for uplink 17: _____________XXXXX______________________
Data delay found: 35
13:53:18:setup_element:INFO:	Eye window for uplink 18: ____________XXXX________________________
Data delay found: 33
13:53:18:setup_element:INFO:	Eye window for uplink 19: _________XXXX___________________________
Data delay found: 30
13:53:18:setup_element:INFO:	Eye window for uplink 20: __________XXXX__________________________
Data delay found: 31
13:53:18:setup_element:INFO:	Eye window for uplink 21: ________XXXXX___________________________
Data delay found: 30
13:53:18:setup_element:INFO:	Eye window for uplink 22: _____XXXX_______________________________
Data delay found: 26
13:53:18:setup_element:INFO:	Eye window for uplink 23: __XXXXX_________________________________
Data delay found: 24
13:53:18:setup_element:INFO:	Eye window for uplink 24: XX__________________________________XXXX
Data delay found: 18
13:53:18:setup_element:INFO:	Eye window for uplink 25: XXXX___________________________________X
Data delay found: 21
13:53:18:setup_element:INFO:	Eye window for uplink 26: X__________________________________XXXXX
Data delay found: 17
13:53:18:setup_element:INFO:	Eye window for uplink 27: XXXXX__________________________________X
Data delay found: 21
13:53:18:setup_element:INFO:	Eye window for uplink 28: ___________________________________XXXXX
Data delay found: 17
13:53:18:setup_element:INFO:	Eye window for uplink 29: XXX__________________________________XXX
Data delay found: 19
13:53:18:setup_element:INFO:	Eye window for uplink 30: XX__________________________________XXXX
Data delay found: 18
13:53:18:setup_element:INFO:	Eye window for uplink 31: XX________________________________XXXXX_
Data delay found: 17
13:53:18:setup_element:INFO:	Setting the data phase to 39 for uplink 16
13:53:18:setup_element:INFO:	Setting the data phase to 35 for uplink 17
13:53:18:setup_element:INFO:	Setting the data phase to 33 for uplink 18
13:53:18:setup_element:INFO:	Setting the data phase to 30 for uplink 19
13:53:18:setup_element:INFO:	Setting the data phase to 31 for uplink 20
13:53:18:setup_element:INFO:	Setting the data phase to 30 for uplink 21
13:53:18:setup_element:INFO:	Setting the data phase to 26 for uplink 22
13:53:18:setup_element:INFO:	Setting the data phase to 24 for uplink 23
13:53:18:setup_element:INFO:	Setting the data phase to 18 for uplink 24
13:53:18:setup_element:INFO:	Setting the data phase to 21 for uplink 25
13:53:18:setup_element:INFO:	Setting the data phase to 17 for uplink 26
13:53:18:setup_element:INFO:	Setting the data phase to 21 for uplink 27
13:53:18:setup_element:INFO:	Setting the data phase to 17 for uplink 28
13:53:18:setup_element:INFO:	Setting the data phase to 19 for uplink 29
13:53:18:setup_element:INFO:	Setting the data phase to 18 for uplink 30
13:53:18:setup_element:INFO:	Setting the data phase to 17 for uplink 31
13:53:18:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 3
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 71
    Eye Windows:
      Uplink 16: _____________________________________________________________________XXXXXXX____
      Uplink 17: _____________________________________________________________________XXXXXXX____
      Uplink 18: ____________________________________________________________________XXXXXXX_____
      Uplink 19: ____________________________________________________________________XXXXXXX_____
      Uplink 20: _____________________________________________________________________XXXXXXX____
      Uplink 21: _____________________________________________________________________XXXXXXX____
      Uplink 22: _____________________________________________________________________XXXXXX_____
      Uplink 23: _____________________________________________________________________XXXXXX_____
      Uplink 24: ___________________________________________________________________XXXXXXXX_____
      Uplink 25: ___________________________________________________________________XXXXXXXX_____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ___________________________________________________________________XXXXXXXX_____
      Uplink 29: ___________________________________________________________________XXXXXXXX_____
      Uplink 30: ____________________________________________________________________XXXXXXXX____
      Uplink 31: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 39
      Window Length: 36
      Eye Window: __________________XXXX__________________
    Uplink 17:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 18:
      Optimal Phase: 33
      Window Length: 36
      Eye Window: ____________XXXX________________________
    Uplink 19:
      Optimal Phase: 30
      Window Length: 36
      Eye Window: _________XXXX___________________________
    Uplink 20:
      Optimal Phase: 31
      Window Length: 36
      Eye Window: __________XXXX__________________________
    Uplink 21:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 22:
      Optimal Phase: 26
      Window Length: 36
      Eye Window: _____XXXX_______________________________
    Uplink 23:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 24:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 25:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 26:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 27:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 28:
      Optimal Phase: 17
      Window Length: 35
      Eye Window: ___________________________________XXXXX
    Uplink 29:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 30:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 31:
      Optimal Phase: 17
      Window Length: 32
      Eye Window: XX________________________________XXXXX_
]
13:53:18:setup_element:INFO:	Beginning SMX ASICs map scan
13:53:18:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:53:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:53:18:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [3]
13:53:18:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [3]
13:53:18:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:53:18:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 17
13:53:18:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 16
13:53:19:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 24
13:53:19:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 25
13:53:19:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 19
13:53:19:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 18
13:53:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 26
13:53:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 27
13:53:19:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 21
13:53:19:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 20
13:53:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 28
13:53:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 29
13:53:20:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 23
13:53:20:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 22
13:53:20:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 30
13:53:20:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 31
13:53:21:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 3
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 71
    Eye Windows:
      Uplink 16: _____________________________________________________________________XXXXXXX____
      Uplink 17: _____________________________________________________________________XXXXXXX____
      Uplink 18: ____________________________________________________________________XXXXXXX_____
      Uplink 19: ____________________________________________________________________XXXXXXX_____
      Uplink 20: _____________________________________________________________________XXXXXXX____
      Uplink 21: _____________________________________________________________________XXXXXXX____
      Uplink 22: _____________________________________________________________________XXXXXX_____
      Uplink 23: _____________________________________________________________________XXXXXX_____
      Uplink 24: ___________________________________________________________________XXXXXXXX_____
      Uplink 25: ___________________________________________________________________XXXXXXXX_____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ___________________________________________________________________XXXXXXXX_____
      Uplink 29: ___________________________________________________________________XXXXXXXX_____
      Uplink 30: ____________________________________________________________________XXXXXXXX____
      Uplink 31: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 39
      Window Length: 36
      Eye Window: __________________XXXX__________________
    Uplink 17:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 18:
      Optimal Phase: 33
      Window Length: 36
      Eye Window: ____________XXXX________________________
    Uplink 19:
      Optimal Phase: 30
      Window Length: 36
      Eye Window: _________XXXX___________________________
    Uplink 20:
      Optimal Phase: 31
      Window Length: 36
      Eye Window: __________XXXX__________________________
    Uplink 21:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 22:
      Optimal Phase: 26
      Window Length: 36
      Eye Window: _____XXXX_______________________________
    Uplink 23:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 24:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 25:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 26:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 27:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 28:
      Optimal Phase: 17
      Window Length: 35
      Eye Window: ___________________________________XXXXX
    Uplink 29:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 30:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 31:
      Optimal Phase: 17
      Window Length: 32
      Eye Window: XX________________________________XXXXX_

13:53:21:setup_element:INFO:	Performing Elink synchronization
13:53:21:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:53:21:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:53:21:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [3]
13:53:21:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [3]
13:53:21:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 3
13:53:21:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:53:21:ST3_emu:INFO:	Number of chips: 8
13:53:21:ST3_emu:INFO:	Chip address:  	0x0
13:53:21:ST3_emu:INFO:	Chip address:  	0x1
13:53:21:ST3_emu:INFO:	Chip address:  	0x2
13:53:21:ST3_emu:INFO:	Chip address:  	0x3
13:53:21:ST3_emu:INFO:	Chip address:  	0x4
13:53:21:ST3_emu:INFO:	Chip address:  	0x5
13:53:21:ST3_emu:INFO:	Chip address:  	0x6
13:53:21:ST3_emu:INFO:	Chip address:  	0x7
13:53:22:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:53:23:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  15.6 | 1206.9
13:53:23:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  18.7 | 1218.6
13:53:23:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |   6.1 | 1259.6
13:53:23:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  25.1 | 1195.1
13:53:23:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  21.9 | 1195.1
13:53:24:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  -3.3 | 1294.5
13:53:24:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  15.6 | 1224.5
13:53:24:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  12.4 | 1242.0
13:53:24:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:53:28:ST3_smx:INFO:	chip: 0-0 	 21.902970 C 	 1177.390875 mV
13:53:28:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:53:28:ST3_smx:INFO:		Electrons
13:53:28:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:53:30:ST3_smx:INFO:	----> Checking Analog response
13:53:30:ST3_smx:INFO:	----> Checking broken channels
13:53:31:ST3_smx:INFO:	Total # broken ch: 0
13:53:31:ST3_smx:INFO:	List FAST: []
13:53:31:ST3_smx:INFO:	List SLOW: []
13:53:31:ST3_smx:INFO:		Holes
13:53:31:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:53:32:ST3_smx:INFO:	----> Checking Analog response
13:53:32:ST3_smx:INFO:	----> Checking broken channels
13:53:33:ST3_smx:INFO:	Total # broken ch: 0
13:53:33:ST3_smx:INFO:	List FAST: []
13:53:33:ST3_smx:INFO:	List SLOW: []
13:53:33:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:53:33:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  25.1 | 1177.4
13:53:33:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  18.7 | 1218.6
13:53:33:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |   6.1 | 1253.7
13:53:34:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  25.1 | 1195.1
13:53:34:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  21.9 | 1195.1
13:53:34:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  -3.3 | 1294.5
13:53:34:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  15.6 | 1224.5
13:53:35:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  12.4 | 1242.0
13:53:35:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:53:39:ST3_smx:INFO:	chip: 0-1 	 25.062742 C 	 1189.190035 mV
13:53:39:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:53:39:ST3_smx:INFO:		Electrons
13:53:39:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:53:41:ST3_smx:INFO:	----> Checking Analog response
13:53:41:ST3_smx:INFO:	----> Checking broken channels
13:53:41:ST3_smx:INFO:	Total # broken ch: 0
13:53:41:ST3_smx:INFO:	List FAST: []
13:53:41:ST3_smx:INFO:	List SLOW: []
13:53:41:ST3_smx:INFO:		Holes
13:53:41:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:53:43:ST3_smx:INFO:	----> Checking Analog response
13:53:43:ST3_smx:INFO:	----> Checking broken channels
13:53:43:ST3_smx:INFO:	Total # broken ch: 0
13:53:43:ST3_smx:INFO:	List FAST: []
13:53:43:ST3_smx:INFO:	List SLOW: []
13:53:43:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:53:43:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  25.1 | 1177.4
13:53:44:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  28.2 | 1183.3
13:53:44:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |   6.1 | 1253.7
13:53:44:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  25.1 | 1189.2
13:53:44:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  21.9 | 1195.1
13:53:45:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  -3.3 | 1294.5
13:53:45:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  15.6 | 1224.5
13:53:45:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  12.4 | 1242.0
13:53:45:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:53:49:ST3_smx:INFO:	chip: 0-2 	 9.288730 C 	 1236.187875 mV
13:53:49:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:53:49:ST3_smx:INFO:		Electrons
13:53:49:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:53:51:ST3_smx:INFO:	----> Checking Analog response
13:53:51:ST3_smx:INFO:	----> Checking broken channels
13:53:51:ST3_smx:INFO:	Total # broken ch: 0
13:53:51:ST3_smx:INFO:	List FAST: []
13:53:51:ST3_smx:INFO:	List SLOW: []
13:53:51:ST3_smx:INFO:		Holes
13:53:51:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:53:53:ST3_smx:INFO:	----> Checking Analog response
13:53:53:ST3_smx:INFO:	----> Checking broken channels
13:53:53:ST3_smx:INFO:	Total # broken ch: 0
13:53:53:ST3_smx:INFO:	List FAST: []
13:53:53:ST3_smx:INFO:	List SLOW: []
13:53:53:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:53:54:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  25.1 | 1171.5
13:53:54:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  28.2 | 1177.4
13:53:54:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |  12.4 | 1230.3
13:53:54:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  28.2 | 1189.2
13:53:55:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  25.1 | 1189.2
13:53:55:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  -0.1 | 1294.5
13:53:55:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  15.6 | 1218.6
13:53:55:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  12.4 | 1242.0
13:53:56:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:53:59:ST3_smx:INFO:	chip: 0-3 	 31.389742 C 	 1171.483840 mV
13:53:59:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:53:59:ST3_smx:INFO:		Electrons
13:53:59:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:01:ST3_smx:INFO:	----> Checking Analog response
13:54:01:ST3_smx:INFO:	----> Checking broken channels
13:54:01:ST3_smx:INFO:	Total # broken ch: 0
13:54:01:ST3_smx:INFO:	List FAST: []
13:54:01:ST3_smx:INFO:	List SLOW: []
13:54:01:ST3_smx:INFO:		Holes
13:54:01:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:03:ST3_smx:INFO:	----> Checking Analog response
13:54:03:ST3_smx:INFO:	----> Checking broken channels
13:54:04:ST3_smx:INFO:	Total # broken ch: 0
13:54:04:ST3_smx:INFO:	List FAST: []
13:54:04:ST3_smx:INFO:	List SLOW: []
13:54:04:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:54:04:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  28.2 | 1171.5
13:54:04:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  31.4 | 1177.4
13:54:04:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |  15.6 | 1230.3
13:54:05:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  34.6 | 1165.6
13:54:05:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  28.2 | 1189.2
13:54:05:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |   3.0 | 1288.7
13:54:05:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  18.7 | 1218.6
13:54:06:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  15.6 | 1242.0
13:54:06:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:54:10:ST3_smx:INFO:	chip: 0-4 	 31.389742 C 	 1171.483840 mV
13:54:10:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:54:10:ST3_smx:INFO:		Electrons
13:54:10:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:12:ST3_smx:INFO:	----> Checking Analog response
13:54:12:ST3_smx:INFO:	----> Checking broken channels
13:54:12:ST3_smx:INFO:	Total # broken ch: 0
13:54:12:ST3_smx:INFO:	List FAST: []
13:54:12:ST3_smx:INFO:	List SLOW: []
13:54:12:ST3_smx:INFO:		Holes
13:54:12:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:14:ST3_smx:INFO:	----> Checking Analog response
13:54:14:ST3_smx:INFO:	----> Checking broken channels
13:54:14:ST3_smx:INFO:	Total # broken ch: 0
13:54:14:ST3_smx:INFO:	List FAST: []
13:54:14:ST3_smx:INFO:	List SLOW: []
13:54:14:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:54:15:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  31.4 | 1171.5
13:54:15:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  34.6 | 1177.4
13:54:15:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |  15.6 | 1230.3
13:54:15:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  37.7 | 1165.6
13:54:15:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  31.4 | 1165.6
13:54:16:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |   3.0 | 1288.7
13:54:16:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  18.7 | 1218.6
13:54:16:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  15.6 | 1242.0
13:54:17:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:54:20:ST3_smx:INFO:	chip: 0-5 	 15.590880 C 	 1236.187875 mV
13:54:20:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:54:20:ST3_smx:INFO:		Electrons
13:54:20:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:22:ST3_smx:INFO:	----> Checking Analog response
13:54:22:ST3_smx:INFO:	----> Checking broken channels
13:54:23:ST3_smx:INFO:	Total # broken ch: 0
13:54:23:ST3_smx:INFO:	List FAST: []
13:54:23:ST3_smx:INFO:	List SLOW: []
13:54:23:ST3_smx:INFO:		Holes
13:54:23:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:24:ST3_smx:INFO:	----> Checking Analog response
13:54:24:ST3_smx:INFO:	----> Checking broken channels
13:54:25:ST3_smx:INFO:	Total # broken ch: 0
13:54:25:ST3_smx:INFO:	List FAST: []
13:54:25:ST3_smx:INFO:	List SLOW: []
13:54:25:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:54:25:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  31.4 | 1171.5
13:54:25:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  34.6 | 1177.4
13:54:25:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |  15.6 | 1230.3
13:54:26:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  37.7 | 1165.6
13:54:26:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  31.4 | 1165.6
13:54:26:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  15.6 | 1230.3
13:54:26:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  18.7 | 1218.6
13:54:27:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  15.6 | 1236.2
13:54:27:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:54:31:ST3_smx:INFO:	chip: 0-6 	 18.745682 C 	 1206.851500 mV
13:54:31:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:54:31:ST3_smx:INFO:		Electrons
13:54:31:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:33:ST3_smx:INFO:	----> Checking Analog response
13:54:33:ST3_smx:INFO:	----> Checking broken channels
13:54:33:ST3_smx:INFO:	Total # broken ch: 0
13:54:33:ST3_smx:INFO:	List FAST: []
13:54:33:ST3_smx:INFO:	List SLOW: []
13:54:33:ST3_smx:INFO:		Holes
13:54:33:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:35:ST3_smx:INFO:	----> Checking Analog response
13:54:35:ST3_smx:INFO:	----> Checking broken channels
13:54:35:ST3_smx:INFO:	Total # broken ch: 0
13:54:35:ST3_smx:INFO:	List FAST: []
13:54:35:ST3_smx:INFO:	List SLOW: []
13:54:35:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:54:35:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  31.4 | 1171.5
13:54:36:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  34.6 | 1177.4
13:54:36:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |  15.6 | 1224.5
13:54:36:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  34.6 | 1165.6
13:54:36:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  31.4 | 1165.6
13:54:37:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  15.6 | 1230.3
13:54:37:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  18.7 | 1206.9
13:54:37:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  15.6 | 1236.2
13:54:37:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:54:41:ST3_smx:INFO:	chip: 0-7 	 15.590880 C 	 1236.187875 mV
13:54:41:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:54:41:ST3_smx:INFO:		Electrons
13:54:41:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:43:ST3_smx:INFO:	----> Checking Analog response
13:54:43:ST3_smx:INFO:	----> Checking broken channels
13:54:43:ST3_smx:INFO:	Total # broken ch: 0
13:54:43:ST3_smx:INFO:	List FAST: []
13:54:43:ST3_smx:INFO:	List SLOW: []
13:54:43:ST3_smx:INFO:		Holes
13:54:43:ST3_smx:INFO:			Injected pulses: 200LSB, amp_cal 11.200000 fC
13:54:45:ST3_smx:INFO:	----> Checking Analog response
13:54:45:ST3_smx:INFO:	----> Checking broken channels
13:54:45:ST3_smx:INFO:	Total # broken ch: 0
13:54:45:ST3_smx:INFO:	List FAST: []
13:54:45:ST3_smx:INFO:	List SLOW: []
13:54:45:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:54:46:febtest:INFO:	0-0 | XA-000-08-002-001-006-160-07 |  31.4 | 1171.5
13:54:46:febtest:INFO:	0-1 | XA-000-08-002-001-006-165-07 |  34.6 | 1177.4
13:54:46:febtest:INFO:	0-2 | XA-000-08-002-001-006-175-07 |  15.6 | 1230.3
13:54:46:febtest:INFO:	0-3 | XA-000-08-002-001-006-179-00 |  37.7 | 1165.6
13:54:47:febtest:INFO:	0-4 | XA-000-08-002-001-006-178-00 |  31.4 | 1165.6
13:54:47:febtest:INFO:	0-5 | XA-000-08-002-001-006-174-07 |  18.7 | 1230.3
13:54:47:febtest:INFO:	0-6 | XA-000-08-002-001-006-167-07 |  21.9 | 1206.9
13:54:47:febtest:INFO:	0-7 | XA-000-08-002-001-006-162-07 |  15.6 | 1236.2
############################################################
#                   S U M M A R Y                          #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_28-13_53_10', 'OPERATOR': 'Oleksandr S.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-162-07', 'FUSED_ID': 6359364699117611559, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.4770', '1.847', '2.2620', '7.000', '1.5340', '7.000', '1.5340'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

13:54:50:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_1012/A//TestDate_2023_08_28-13_53_10/