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FEB_1012 30.11.23 15:17:35
TextEdit.txt
15:17:19:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:17:19:febtest:INFO: FEB 8-2 selected
15:17:19:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:17:24:febtest:INFO: FEB 8-2 selected
15:17:24:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:17:33:ST3_Shared:INFO: Listo of operators:Irakli K.;
15:17:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:17:35:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:17:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:17:35:febtest:INFO: Testing FEB with SN 1012
15:17:36:smx_tester:INFO: Scanning setup
15:17:36:elinks:INFO: Disabling clock on downlink 0
15:17:36:elinks:INFO: Disabling clock on downlink 1
15:17:36:elinks:INFO: Disabling clock on downlink 2
15:17:36:elinks:INFO: Disabling clock on downlink 3
15:17:36:elinks:INFO: Disabling clock on downlink 4
15:17:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:17:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:17:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:17:36:elinks:INFO: Disabling clock on downlink 0
15:17:36:elinks:INFO: Disabling clock on downlink 1
15:17:36:elinks:INFO: Disabling clock on downlink 2
15:17:36:elinks:INFO: Disabling clock on downlink 3
15:17:36:elinks:INFO: Disabling clock on downlink 4
15:17:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:17:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
15:17:36:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
15:17:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:17:36:elinks:INFO: Disabling clock on downlink 0
15:17:36:elinks:INFO: Disabling clock on downlink 1
15:17:36:elinks:INFO: Disabling clock on downlink 2
15:17:36:elinks:INFO: Disabling clock on downlink 3
15:17:36:elinks:INFO: Disabling clock on downlink 4
15:17:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:17:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:17:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:17:37:elinks:INFO: Disabling clock on downlink 0
15:17:37:elinks:INFO: Disabling clock on downlink 1
15:17:37:elinks:INFO: Disabling clock on downlink 2
15:17:37:elinks:INFO: Disabling clock on downlink 3
15:17:37:elinks:INFO: Disabling clock on downlink 4
15:17:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:17:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:17:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:17:37:elinks:INFO: Disabling clock on downlink 0
15:17:37:elinks:INFO: Disabling clock on downlink 1
15:17:37:elinks:INFO: Disabling clock on downlink 2
15:17:37:elinks:INFO: Disabling clock on downlink 3
15:17:37:elinks:INFO: Disabling clock on downlink 4
15:17:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:17:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:17:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:17:37:setup_element:INFO: Scanning clock phase
15:17:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:17:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:17:37:setup_element:INFO: Clock phase scan results for group 0, downlink 1
15:17:37:setup_element:INFO: Eye window for uplink 0 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
15:17:37:setup_element:INFO: Eye window for uplink 1 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
15:17:37:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:17:37:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:17:37:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________________
Clock Delay: 40
15:17:37:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________________
Clock Delay: 40
15:17:37:setup_element:INFO: Eye window for uplink 6 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:17:37:setup_element:INFO: Eye window for uplink 7 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:17:37:setup_element:INFO: Eye window for uplink 8 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:17:37:setup_element:INFO: Eye window for uplink 9 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:17:37:setup_element:INFO: Eye window for uplink 10: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:17:37:setup_element:INFO: Eye window for uplink 11: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:17:37:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:17:37:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:17:37:setup_element:INFO: Eye window for uplink 14: _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:17:37:setup_element:INFO: Eye window for uplink 15: _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:17:37:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
15:17:37:setup_element:INFO: Scanning data phases
15:17:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:17:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:17:42:setup_element:INFO: Data phase scan results for group 0, downlink 1
15:17:42:setup_element:INFO: Eye window for uplink 0 : ___________XXXXX________________________
Data delay found: 33
15:17:42:setup_element:INFO: Eye window for uplink 1 : ________XXXX____________________________
Data delay found: 29
15:17:42:setup_element:INFO: Eye window for uplink 2 : _____XXXXXX_____________________________
Data delay found: 27
15:17:42:setup_element:INFO: Eye window for uplink 3 : ___XXXXX________________________________
Data delay found: 25
15:17:42:setup_element:INFO: Eye window for uplink 4 : _____XXXXXX_____________________________
Data delay found: 27
15:17:42:setup_element:INFO: Eye window for uplink 5 : _XXXXX__________________________________
Data delay found: 23
15:17:42:setup_element:INFO: Eye window for uplink 6 : XXX__________________________________XXX
Data delay found: 19
15:17:42:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXXXX__
Data delay found: 14
15:17:42:setup_element:INFO: Eye window for uplink 8 : __________________________XXXXX_________
Data delay found: 8
15:17:42:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
15:17:42:setup_element:INFO: Eye window for uplink 10: ____________________________XXXXX_______
Data delay found: 10
15:17:42:setup_element:INFO: Eye window for uplink 11: ________________________________XXXXX___
Data delay found: 14
15:17:42:setup_element:INFO: Eye window for uplink 12: __________________________XXXXX_________
Data delay found: 8
15:17:42:setup_element:INFO: Eye window for uplink 13: _____________________________XXXXX______
Data delay found: 11
15:17:42:setup_element:INFO: Eye window for uplink 14: ___________________________XXXXX________
Data delay found: 9
15:17:42:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
15:17:42:setup_element:INFO: Setting the data phase to 33 for uplink 0
15:17:42:setup_element:INFO: Setting the data phase to 29 for uplink 1
15:17:42:setup_element:INFO: Setting the data phase to 27 for uplink 2
15:17:42:setup_element:INFO: Setting the data phase to 25 for uplink 3
15:17:42:setup_element:INFO: Setting the data phase to 27 for uplink 4
15:17:42:setup_element:INFO: Setting the data phase to 23 for uplink 5
15:17:42:setup_element:INFO: Setting the data phase to 19 for uplink 6
15:17:42:setup_element:INFO: Setting the data phase to 14 for uplink 7
15:17:42:setup_element:INFO: Setting the data phase to 8 for uplink 8
15:17:42:setup_element:INFO: Setting the data phase to 12 for uplink 9
15:17:42:setup_element:INFO: Setting the data phase to 10 for uplink 10
15:17:42:setup_element:INFO: Setting the data phase to 14 for uplink 11
15:17:42:setup_element:INFO: Setting the data phase to 8 for uplink 12
15:17:42:setup_element:INFO: Setting the data phase to 11 for uplink 13
15:17:42:setup_element:INFO: Setting the data phase to 9 for uplink 14
15:17:42:setup_element:INFO: Setting the data phase to 13 for uplink 15
15:17:42:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: ________________________________________________________________________________
Uplink 5: ________________________________________________________________________________
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: _______________________________________________________________________XXXXXXXX_
Uplink 9: _______________________________________________________________________XXXXXXXX_
Uplink 10: ________________________________________________________________________XXXXXXXX
Uplink 11: ________________________________________________________________________XXXXXXXX
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _________________________________________________________________________XXXXXXX
Uplink 15: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 2:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 4:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 7:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 11:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 12:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 13:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 14:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
]
15:17:42:setup_element:INFO: Beginning SMX ASICs map scan
15:17:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:17:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:17:42:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:17:42:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:17:42:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:17:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
15:17:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
15:17:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
15:17:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
15:17:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
15:17:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
15:17:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
15:17:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
15:17:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
15:17:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
15:17:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
15:17:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
15:17:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
15:17:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
15:17:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
15:17:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
15:17:45:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: ________________________________________________________________________________
Uplink 5: ________________________________________________________________________________
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: _______________________________________________________________________XXXXXXXX_
Uplink 9: _______________________________________________________________________XXXXXXXX_
Uplink 10: ________________________________________________________________________XXXXXXXX
Uplink 11: ________________________________________________________________________XXXXXXXX
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _________________________________________________________________________XXXXXXX
Uplink 15: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 2:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 4:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 7:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 11:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 12:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 13:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 14:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
15:17:45:setup_element:INFO: Performing Elink synchronization
15:17:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:17:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:17:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:17:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:17:45:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
15:17:45:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:17:45:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
15:17:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:17:46:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 34.6 | 1195.1
15:17:47:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 34.6 | 1206.9
15:17:47:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1236.2
15:17:47:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 37.7 | 1195.1
15:17:47:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 34.6 | 1189.2
15:17:47:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1277.1
15:17:48:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 28.2 | 1212.7
15:17:48:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:17:48:ST3_smx:INFO: Configuring SMX FAST
15:17:50:ST3_smx:INFO: chip: 1-0 40.898880 C 1177.390875 mV
15:17:50:ST3_smx:INFO: Electrons
15:17:50:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:17:52:ST3_smx:INFO: ----> Checking Analog response
15:17:52:ST3_smx:INFO: ----> Checking broken channels
15:17:52:ST3_smx:INFO: Total # broken ch: 0
15:17:52:ST3_smx:INFO: List FAST: []
15:17:52:ST3_smx:INFO: List SLOW: []
15:17:52:ST3_smx:INFO: Holes
15:17:52:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:17:54:ST3_smx:INFO: ----> Checking Analog response
15:17:54:ST3_smx:INFO: ----> Checking broken channels
15:17:55:ST3_smx:INFO: Total # broken ch: 0
15:17:55:ST3_smx:INFO: List FAST: []
15:17:55:ST3_smx:INFO: List SLOW: []
15:17:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:17:55:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1165.6
15:17:55:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 34.6 | 1206.9
15:17:55:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1242.0
15:17:55:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1195.1
15:17:56:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:17:56:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1277.1
15:17:56:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1212.7
15:17:56:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1218.6
15:17:57:ST3_smx:INFO: Configuring SMX FAST
15:17:59:ST3_smx:INFO: chip: 8-1 40.898880 C 1189.190035 mV
15:17:59:ST3_smx:INFO: Electrons
15:17:59:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:01:ST3_smx:INFO: ----> Checking Analog response
15:18:01:ST3_smx:INFO: ----> Checking broken channels
15:18:01:ST3_smx:INFO: Total # broken ch: 0
15:18:01:ST3_smx:INFO: List FAST: []
15:18:01:ST3_smx:INFO: List SLOW: []
15:18:01:ST3_smx:INFO: Holes
15:18:01:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:03:ST3_smx:INFO: ----> Checking Analog response
15:18:03:ST3_smx:INFO: ----> Checking broken channels
15:18:03:ST3_smx:INFO: Total # broken ch: 0
15:18:03:ST3_smx:INFO: List FAST: []
15:18:03:ST3_smx:INFO: List SLOW: []
15:18:03:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:03:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:04:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1183.3
15:18:04:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1242.0
15:18:04:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1195.1
15:18:04:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:18:04:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 18.7 | 1277.1
15:18:05:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1212.7
15:18:05:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:18:05:ST3_smx:INFO: Configuring SMX FAST
15:18:07:ST3_smx:INFO: chip: 3-2 28.225000 C 1230.330540 mV
15:18:07:ST3_smx:INFO: Electrons
15:18:07:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:09:ST3_smx:INFO: ----> Checking Analog response
15:18:09:ST3_smx:INFO: ----> Checking broken channels
15:18:10:ST3_smx:INFO: Total # broken ch: 0
15:18:10:ST3_smx:INFO: List FAST: []
15:18:10:ST3_smx:INFO: List SLOW: []
15:18:10:ST3_smx:INFO: Holes
15:18:10:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:11:ST3_smx:INFO: ----> Checking Analog response
15:18:11:ST3_smx:INFO: ----> Checking broken channels
15:18:12:ST3_smx:INFO: Total # broken ch: 0
15:18:12:ST3_smx:INFO: List FAST: []
15:18:12:ST3_smx:INFO: List SLOW: []
15:18:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:12:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:12:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1189.2
15:18:12:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1230.3
15:18:13:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1195.1
15:18:13:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:18:13:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 18.7 | 1277.1
15:18:13:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1212.7
15:18:14:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:18:14:ST3_smx:INFO: Configuring SMX FAST
15:18:16:ST3_smx:INFO: chip: 10-3 44.073563 C 1183.292940 mV
15:18:16:ST3_smx:INFO: Electrons
15:18:16:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:18:ST3_smx:INFO: ----> Checking Analog response
15:18:18:ST3_smx:INFO: ----> Checking broken channels
15:18:18:ST3_smx:INFO: Total # broken ch: 0
15:18:18:ST3_smx:INFO: List FAST: []
15:18:18:ST3_smx:INFO: List SLOW: []
15:18:18:ST3_smx:INFO: Holes
15:18:18:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:20:ST3_smx:INFO: ----> Checking Analog response
15:18:20:ST3_smx:INFO: ----> Checking broken channels
15:18:20:ST3_smx:INFO: Total # broken ch: 0
15:18:20:ST3_smx:INFO: List FAST: []
15:18:20:ST3_smx:INFO: List SLOW: []
15:18:20:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:21:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:21:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1189.2
15:18:21:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:18:21:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1183.3
15:18:22:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1195.1
15:18:22:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 18.7 | 1277.1
15:18:22:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1212.7
15:18:22:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:18:23:ST3_smx:INFO: Configuring SMX FAST
15:18:25:ST3_smx:INFO: chip: 5-4 40.898880 C 1183.292940 mV
15:18:25:ST3_smx:INFO: Electrons
15:18:25:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:26:ST3_smx:INFO: ----> Checking Analog response
15:18:26:ST3_smx:INFO: ----> Checking broken channels
15:18:27:ST3_smx:INFO: Total # broken ch: 0
15:18:27:ST3_smx:INFO: List FAST: []
15:18:27:ST3_smx:INFO: List SLOW: []
15:18:27:ST3_smx:INFO: Holes
15:18:27:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:29:ST3_smx:INFO: ----> Checking Analog response
15:18:29:ST3_smx:INFO: ----> Checking broken channels
15:18:29:ST3_smx:INFO: Total # broken ch: 0
15:18:29:ST3_smx:INFO: List FAST: []
15:18:29:ST3_smx:INFO: List SLOW: []
15:18:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:29:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:29:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1183.3
15:18:30:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1230.3
15:18:30:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1183.3
15:18:30:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1177.4
15:18:30:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 18.7 | 1277.1
15:18:31:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1212.7
15:18:31:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1218.6
15:18:31:ST3_smx:INFO: Configuring SMX FAST
15:18:33:ST3_smx:INFO: chip: 12-5 28.225000 C 1253.730060 mV
15:18:33:ST3_smx:INFO: Electrons
15:18:33:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:35:ST3_smx:INFO: ----> Checking Analog response
15:18:35:ST3_smx:INFO: ----> Checking broken channels
15:18:35:ST3_smx:INFO: Total # broken ch: 0
15:18:35:ST3_smx:INFO: List FAST: []
15:18:35:ST3_smx:INFO: List SLOW: []
15:18:35:ST3_smx:INFO: Holes
15:18:35:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:37:ST3_smx:INFO: ----> Checking Analog response
15:18:37:ST3_smx:INFO: ----> Checking broken channels
15:18:38:ST3_smx:INFO: Total # broken ch: 0
15:18:38:ST3_smx:INFO: List FAST: []
15:18:38:ST3_smx:INFO: List SLOW: []
15:18:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:38:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:38:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1189.2
15:18:38:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1230.3
15:18:39:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1183.3
15:18:39:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1177.4
15:18:39:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 28.2 | 1247.9
15:18:39:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 31.4 | 1212.7
15:18:40:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:18:40:ST3_smx:INFO: Configuring SMX FAST
15:18:42:ST3_smx:INFO: chip: 7-6 31.389742 C 1212.728715 mV
15:18:42:ST3_smx:INFO: Electrons
15:18:42:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:44:ST3_smx:INFO: ----> Checking Analog response
15:18:44:ST3_smx:INFO: ----> Checking broken channels
15:18:44:ST3_smx:INFO: Total # broken ch: 0
15:18:44:ST3_smx:INFO: List FAST: []
15:18:44:ST3_smx:INFO: List SLOW: []
15:18:44:ST3_smx:INFO: Holes
15:18:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:46:ST3_smx:INFO: ----> Checking Analog response
15:18:46:ST3_smx:INFO: ----> Checking broken channels
15:18:46:ST3_smx:INFO: Total # broken ch: 0
15:18:46:ST3_smx:INFO: List FAST: []
15:18:46:ST3_smx:INFO: List SLOW: []
15:18:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:47:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:47:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 47.3 | 1189.2
15:18:47:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1230.3
15:18:47:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1183.3
15:18:48:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1177.4
15:18:48:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 28.2 | 1247.9
15:18:48:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:18:48:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:18:49:ST3_smx:INFO: Configuring SMX FAST
15:18:51:ST3_smx:INFO: chip: 14-7 31.389742 C 1230.330540 mV
15:18:51:ST3_smx:INFO: Electrons
15:18:51:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:53:ST3_smx:INFO: ----> Checking Analog response
15:18:53:ST3_smx:INFO: ----> Checking broken channels
15:18:53:ST3_smx:INFO: Total # broken ch: 0
15:18:53:ST3_smx:INFO: List FAST: []
15:18:53:ST3_smx:INFO: List SLOW: []
15:18:53:ST3_smx:INFO: Holes
15:18:53:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:18:55:ST3_smx:INFO: ----> Checking Analog response
15:18:55:ST3_smx:INFO: ----> Checking broken channels
15:18:55:ST3_smx:INFO: Total # broken ch: 0
15:18:55:ST3_smx:INFO: List FAST: []
15:18:55:ST3_smx:INFO: List SLOW: []
15:18:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:18:55:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:18:56:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 47.3 | 1189.2
15:18:56:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 31.4 | 1230.3
15:18:56:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 47.3 | 1183.3
15:18:56:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 40.9 | 1183.3
15:18:57:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 28.2 | 1247.9
15:18:57:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:18:57:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1230.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_30-15_17_35', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-162-07', 'FUSED_ID': 6359364699117611559, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '1012', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.448', '1.4020', '1.846', '2.2780', '7.000', '1.5430', '7.000', '1.5430'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 200, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_30-15_17_35
OPERATOR : Irakli K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1012
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.448', '1.4020', '1.846', '2.2780', '7.000', '1.5430', '7.000', '1.5430']
VI_after__Init : ['2.450', '1.9640', '1.850', '0.3111', '7.000', '1.5480', '7.000', '1.5480']
VI_at__the_End : ['2.450', '1.9640', '1.850', '0.3111', '7.000', '1.5480', '7.000', '1.5480']
15:19:06:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1012/TestDate_2023_11_30-15_17_35/