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FEB_1012 12.02.24 15:57:51
TextEdit.txt
15:57:48:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,123796,HW50020003/SW2.71
15:57:49:febtest:INFO: FEB 8-2 selected
15:57:49:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:57:51:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:57:51:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:57:51:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:57:52:febtest:INFO: Testing FEB with SN 1012
15:57:54:smx_tester:INFO: Scanning setup
15:57:54:elinks:INFO: Disabling clock on downlink 0
15:57:54:elinks:INFO: Disabling clock on downlink 1
15:57:54:elinks:INFO: Disabling clock on downlink 2
15:57:54:elinks:INFO: Disabling clock on downlink 3
15:57:54:elinks:INFO: Disabling clock on downlink 4
15:57:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:57:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:54:elinks:INFO: Disabling clock on downlink 0
15:57:54:elinks:INFO: Disabling clock on downlink 1
15:57:54:elinks:INFO: Disabling clock on downlink 2
15:57:54:elinks:INFO: Disabling clock on downlink 3
15:57:54:elinks:INFO: Disabling clock on downlink 4
15:57:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
15:57:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
15:57:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
15:57:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
15:57:55:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
15:57:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:55:elinks:INFO: Disabling clock on downlink 0
15:57:55:elinks:INFO: Disabling clock on downlink 1
15:57:55:elinks:INFO: Disabling clock on downlink 2
15:57:55:elinks:INFO: Disabling clock on downlink 3
15:57:55:elinks:INFO: Disabling clock on downlink 4
15:57:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:57:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:55:elinks:INFO: Disabling clock on downlink 0
15:57:55:elinks:INFO: Disabling clock on downlink 1
15:57:55:elinks:INFO: Disabling clock on downlink 2
15:57:55:elinks:INFO: Disabling clock on downlink 3
15:57:55:elinks:INFO: Disabling clock on downlink 4
15:57:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:57:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:55:elinks:INFO: Disabling clock on downlink 0
15:57:55:elinks:INFO: Disabling clock on downlink 1
15:57:55:elinks:INFO: Disabling clock on downlink 2
15:57:55:elinks:INFO: Disabling clock on downlink 3
15:57:55:elinks:INFO: Disabling clock on downlink 4
15:57:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:57:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:55:setup_element:INFO: Scanning clock phase
15:57:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:57:55:setup_element:INFO: Clock phase scan results for group 0, downlink 1
15:57:55:setup_element:INFO: Eye window for uplink 0 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:57:55:setup_element:INFO: Eye window for uplink 1 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:57:55:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:55:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:55:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:57:55:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:57:55:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:57:55:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:57:55:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
15:57:55:setup_element:INFO: Scanning data phases
15:57:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:58:01:setup_element:INFO: Data phase scan results for group 0, downlink 1
15:58:01:setup_element:INFO: Eye window for uplink 0 : ____________XXXXX_______________________
Data delay found: 34
15:58:01:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
15:58:01:setup_element:INFO: Eye window for uplink 2 : ______XXXXX_____________________________
Data delay found: 28
15:58:01:setup_element:INFO: Eye window for uplink 3 : ___XXXXX________________________________
Data delay found: 25
15:58:01:setup_element:INFO: Eye window for uplink 4 : _____XXXXX______________________________
Data delay found: 27
15:58:01:setup_element:INFO: Eye window for uplink 5 : __XXXX__________________________________
Data delay found: 23
15:58:01:setup_element:INFO: Eye window for uplink 6 : XXX__________________________________XXX
Data delay found: 19
15:58:01:setup_element:INFO: Eye window for uplink 7 : _________________________________XXXXX__
Data delay found: 15
15:58:01:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________
Data delay found: 6
15:58:01:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
15:58:01:setup_element:INFO: Eye window for uplink 10: ___________________________XXXXXX_______
Data delay found: 9
15:58:01:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXX____
Data delay found: 13
15:58:01:setup_element:INFO: Eye window for uplink 12: __________________________XXXX__________
Data delay found: 7
15:58:01:setup_element:INFO: Eye window for uplink 13: _____________________________XXXX_______
Data delay found: 10
15:58:01:setup_element:INFO: Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
15:58:01:setup_element:INFO: Eye window for uplink 15: ______________________________XXXXX_____
Data delay found: 12
15:58:01:setup_element:INFO: Setting the data phase to 34 for uplink 0
15:58:01:setup_element:INFO: Setting the data phase to 30 for uplink 1
15:58:01:setup_element:INFO: Setting the data phase to 28 for uplink 2
15:58:01:setup_element:INFO: Setting the data phase to 25 for uplink 3
15:58:01:setup_element:INFO: Setting the data phase to 27 for uplink 4
15:58:01:setup_element:INFO: Setting the data phase to 23 for uplink 5
15:58:01:setup_element:INFO: Setting the data phase to 19 for uplink 6
15:58:01:setup_element:INFO: Setting the data phase to 15 for uplink 7
15:58:01:setup_element:INFO: Setting the data phase to 6 for uplink 8
15:58:01:setup_element:INFO: Setting the data phase to 12 for uplink 9
15:58:01:setup_element:INFO: Setting the data phase to 9 for uplink 10
15:58:01:setup_element:INFO: Setting the data phase to 13 for uplink 11
15:58:01:setup_element:INFO: Setting the data phase to 7 for uplink 12
15:58:01:setup_element:INFO: Setting the data phase to 10 for uplink 13
15:58:01:setup_element:INFO: Setting the data phase to 10 for uplink 14
15:58:01:setup_element:INFO: Setting the data phase to 12 for uplink 15
15:58:01:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXX_
Uplink 1: ________________________________________________________________________XXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXXX__
Uplink 3: _______________________________________________________________________XXXXXXX__
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXX__
Uplink 7: ________________________________________________________________________XXXXXX__
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ______________________________________________________________________XXXXXXX___
Uplink 13: ______________________________________________________________________XXXXXXX___
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 4:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 13:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
]
15:58:01:setup_element:INFO: Beginning SMX ASICs map scan
15:58:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:58:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:58:01:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:58:01:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:58:01:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:58:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
15:58:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
15:58:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
15:58:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
15:58:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
15:58:02:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
15:58:02:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
15:58:02:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
15:58:02:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
15:58:02:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
15:58:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
15:58:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
15:58:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
15:58:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
15:58:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
15:58:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
15:58:04:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXX_
Uplink 1: ________________________________________________________________________XXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXXX__
Uplink 3: _______________________________________________________________________XXXXXXX__
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXX__
Uplink 7: ________________________________________________________________________XXXXXX__
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ______________________________________________________________________XXXXXXX___
Uplink 13: ______________________________________________________________________XXXXXXX___
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 4:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 13:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
15:58:04:setup_element:INFO: Performing Elink synchronization
15:58:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:58:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:58:04:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:58:04:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:58:04:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
15:58:04:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:58:04:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
15:58:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:06:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 34.6 | 1195.1
15:58:06:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 37.7 | 1206.9
15:58:06:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1242.0
15:58:07:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
15:58:07:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:58:07:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 18.7 | 1277.1
15:58:07:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:58:08:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1218.6
15:58:08:ST3_smx:INFO: Configuring SMX FAST
15:58:10:ST3_smx:INFO: chip: 1-0 40.898880 C 1177.390875 mV
15:58:10:ST3_smx:INFO: Electrons
15:58:10:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:12:ST3_smx:INFO: ----> Checking Analog response
15:58:12:ST3_smx:INFO: ----> Checking broken channels
15:58:12:ST3_smx:INFO: Total # broken ch: 0
15:58:12:ST3_smx:INFO: List FAST: []
15:58:12:ST3_smx:INFO: List SLOW: []
15:58:12:ST3_smx:INFO: Holes
15:58:12:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:14:ST3_smx:INFO: ----> Checking Analog response
15:58:14:ST3_smx:INFO: ----> Checking broken channels
15:58:14:ST3_smx:INFO: Total # broken ch: 0
15:58:15:ST3_smx:INFO: List FAST: []
15:58:15:ST3_smx:INFO: List SLOW: []
15:58:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:15:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:58:15:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 34.6 | 1206.9
15:58:15:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 21.9 | 1247.9
15:58:15:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
15:58:16:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:58:16:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1277.1
15:58:16:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:58:16:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1218.6
15:58:17:ST3_smx:INFO: Configuring SMX FAST
15:58:19:ST3_smx:INFO: chip: 8-1 40.898880 C 1189.190035 mV
15:58:19:ST3_smx:INFO: Electrons
15:58:19:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:21:ST3_smx:INFO: ----> Checking Analog response
15:58:21:ST3_smx:INFO: ----> Checking broken channels
15:58:21:ST3_smx:INFO: Total # broken ch: 0
15:58:21:ST3_smx:INFO: List FAST: []
15:58:21:ST3_smx:INFO: List SLOW: []
15:58:21:ST3_smx:INFO: Holes
15:58:21:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:23:ST3_smx:INFO: ----> Checking Analog response
15:58:23:ST3_smx:INFO: ----> Checking broken channels
15:58:23:ST3_smx:INFO: Total # broken ch: 0
15:58:23:ST3_smx:INFO: List FAST: []
15:58:23:ST3_smx:INFO: List SLOW: []
15:58:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:24:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:58:24:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1183.3
15:58:24:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 25.1 | 1247.9
15:58:24:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
15:58:25:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:58:25:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1277.1
15:58:25:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:58:25:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1218.6
15:58:26:ST3_smx:INFO: Configuring SMX FAST
15:58:28:ST3_smx:INFO: chip: 3-2 28.225000 C 1230.330540 mV
15:58:28:ST3_smx:INFO: Electrons
15:58:28:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:30:ST3_smx:INFO: ----> Checking Analog response
15:58:30:ST3_smx:INFO: ----> Checking broken channels
15:58:30:ST3_smx:INFO: Total # broken ch: 0
15:58:30:ST3_smx:INFO: List FAST: []
15:58:30:ST3_smx:INFO: List SLOW: []
15:58:30:ST3_smx:INFO: Holes
15:58:30:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:32:ST3_smx:INFO: ----> Checking Analog response
15:58:32:ST3_smx:INFO: ----> Checking broken channels
15:58:32:ST3_smx:INFO: Total # broken ch: 0
15:58:32:ST3_smx:INFO: List FAST: []
15:58:32:ST3_smx:INFO: List SLOW: []
15:58:32:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:32:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:58:33:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1183.3
15:58:33:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:58:33:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1189.2
15:58:33:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:58:34:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1282.9
15:58:34:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:58:34:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1218.6
15:58:35:ST3_smx:INFO: Configuring SMX FAST
15:58:37:ST3_smx:INFO: chip: 10-3 40.898880 C 1189.190035 mV
15:58:37:ST3_smx:INFO: Electrons
15:58:37:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:39:ST3_smx:INFO: ----> Checking Analog response
15:58:39:ST3_smx:INFO: ----> Checking broken channels
15:58:39:ST3_smx:INFO: Total # broken ch: 0
15:58:39:ST3_smx:INFO: List FAST: []
15:58:39:ST3_smx:INFO: List SLOW: []
15:58:39:ST3_smx:INFO: Holes
15:58:39:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:41:ST3_smx:INFO: ----> Checking Analog response
15:58:41:ST3_smx:INFO: ----> Checking broken channels
15:58:41:ST3_smx:INFO: Total # broken ch: 0
15:58:41:ST3_smx:INFO: List FAST: []
15:58:41:ST3_smx:INFO: List SLOW: []
15:58:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:41:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:58:41:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1183.3
15:58:42:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:58:42:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 44.1 | 1183.3
15:58:42:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 37.7 | 1189.2
15:58:42:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1277.1
15:58:43:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:58:43:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 31.4 | 1224.5
15:58:44:ST3_smx:INFO: Configuring SMX FAST
15:58:45:ST3_smx:INFO: chip: 5-4 40.898880 C 1183.292940 mV
15:58:45:ST3_smx:INFO: Electrons
15:58:45:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:47:ST3_smx:INFO: ----> Checking Analog response
15:58:47:ST3_smx:INFO: ----> Checking broken channels
15:58:48:ST3_smx:INFO: Total # broken ch: 0
15:58:48:ST3_smx:INFO: List FAST: []
15:58:48:ST3_smx:INFO: List SLOW: []
15:58:48:ST3_smx:INFO: Holes
15:58:48:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:50:ST3_smx:INFO: ----> Checking Analog response
15:58:50:ST3_smx:INFO: ----> Checking broken channels
15:58:50:ST3_smx:INFO: Total # broken ch: 0
15:58:50:ST3_smx:INFO: List FAST: []
15:58:50:ST3_smx:INFO: List SLOW: []
15:58:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:50:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 40.9 | 1177.4
15:58:50:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 40.9 | 1183.3
15:58:51:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:58:51:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
15:58:51:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1183.3
15:58:51:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 15.6 | 1277.1
15:58:52:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:58:52:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1224.5
15:58:52:ST3_smx:INFO: Configuring SMX FAST
15:58:54:ST3_smx:INFO: chip: 12-5 25.062742 C 1253.730060 mV
15:58:54:ST3_smx:INFO: Electrons
15:58:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:56:ST3_smx:INFO: ----> Checking Analog response
15:58:56:ST3_smx:INFO: ----> Checking broken channels
15:58:56:ST3_smx:INFO: Total # broken ch: 0
15:58:56:ST3_smx:INFO: List FAST: []
15:58:56:ST3_smx:INFO: List SLOW: []
15:58:56:ST3_smx:INFO: Holes
15:58:56:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:58:58:ST3_smx:INFO: ----> Checking Analog response
15:58:58:ST3_smx:INFO: ----> Checking broken channels
15:58:59:ST3_smx:INFO: Total # broken ch: 0
15:58:59:ST3_smx:INFO: List FAST: []
15:58:59:ST3_smx:INFO: List SLOW: []
15:58:59:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:58:59:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:58:59:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 40.9 | 1189.2
15:58:59:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:59:00:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 44.1 | 1183.3
15:59:00:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1183.3
15:59:00:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 25.1 | 1247.9
15:59:00:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:59:01:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1224.5
15:59:01:ST3_smx:INFO: Configuring SMX FAST
15:59:03:ST3_smx:INFO: chip: 7-6 34.556970 C 1212.728715 mV
15:59:03:ST3_smx:INFO: Electrons
15:59:03:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:59:05:ST3_smx:INFO: ----> Checking Analog response
15:59:05:ST3_smx:INFO: ----> Checking broken channels
15:59:05:ST3_smx:INFO: Total # broken ch: 0
15:59:05:ST3_smx:INFO: List FAST: []
15:59:05:ST3_smx:INFO: List SLOW: []
15:59:05:ST3_smx:INFO: Holes
15:59:05:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:59:07:ST3_smx:INFO: ----> Checking Analog response
15:59:07:ST3_smx:INFO: ----> Checking broken channels
15:59:08:ST3_smx:INFO: Total # broken ch: 0
15:59:08:ST3_smx:INFO: List FAST: []
15:59:08:ST3_smx:INFO: List SLOW: []
15:59:08:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:59:08:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1171.5
15:59:08:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 40.9 | 1183.3
15:59:08:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:59:08:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
15:59:09:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1177.4
15:59:09:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 25.1 | 1247.9
15:59:09:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 37.7 | 1206.9
15:59:09:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1224.5
15:59:10:ST3_smx:INFO: Configuring SMX FAST
15:59:12:ST3_smx:INFO: chip: 14-7 31.389742 C 1230.330540 mV
15:59:12:ST3_smx:INFO: Electrons
15:59:12:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:59:14:ST3_smx:INFO: ----> Checking Analog response
15:59:14:ST3_smx:INFO: ----> Checking broken channels
15:59:14:ST3_smx:INFO: Total # broken ch: 0
15:59:14:ST3_smx:INFO: List FAST: []
15:59:14:ST3_smx:INFO: List SLOW: []
15:59:14:ST3_smx:INFO: Holes
15:59:14:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
15:59:16:ST3_smx:INFO: ----> Checking Analog response
15:59:16:ST3_smx:INFO: ----> Checking broken channels
15:59:16:ST3_smx:INFO: Total # broken ch: 0
15:59:16:ST3_smx:INFO: List FAST: []
15:59:16:ST3_smx:INFO: List SLOW: []
15:59:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:59:16:febtest:INFO: 1-0 | XA-000-08-002-001-006-160-07 | 44.1 | 1177.4
15:59:17:febtest:INFO: 8-1 | XA-000-08-002-001-006-165-07 | 44.1 | 1189.2
15:59:17:febtest:INFO: 3-2 | XA-000-08-002-001-006-175-07 | 28.2 | 1230.3
15:59:17:febtest:INFO: 10-3 | XA-000-08-002-001-006-179-00 | 40.9 | 1183.3
15:59:17:febtest:INFO: 5-4 | XA-000-08-002-001-006-178-00 | 44.1 | 1183.3
15:59:18:febtest:INFO: 12-5 | XA-000-08-002-001-006-174-07 | 25.1 | 1247.9
15:59:18:febtest:INFO: 7-6 | XA-000-08-002-001-006-167-07 | 34.6 | 1212.7
15:59:18:febtest:INFO: 14-7 | XA-000-08-002-001-006-162-07 | 34.6 | 1230.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2024_02_12-15_57_51', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-162-07', 'FUSED_ID': 6359364699117611559, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '1012', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.450', '1.8250', '1.850', '2.2380', '2.450', '0.0002', '1.850', '0.0001'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 200, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2024_02_12-15_57_51
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1012
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.450', '1.8250', '1.850', '2.2380', '2.450', '0.0002', '1.850', '0.0001']
VI_after__Init : ['2.450', '1.9650', '1.850', '0.3114', '2.450', '0.0002', '1.850', '0.0001']
VI_at__the_End : ['2.450', '1.9650', '1.850', '0.3113', '2.450', '0.0001', '1.850', '0.0001']
15:59:44:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1012/TestDate_2024_02_12-15_57_51/