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FEB_1017 28.11.23 11:06:02
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10:56:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:56:26:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:56:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:56:27:febtest:INFO: Tsting FEB with SN 1020
10:56:28:smx_tester:INFO: Scanning setup
10:56:28:elinks:INFO: Disabling clock on downlink 0
10:56:28:elinks:INFO: Disabling clock on downlink 1
10:56:28:elinks:INFO: Disabling clock on downlink 2
10:56:28:elinks:INFO: Disabling clock on downlink 3
10:56:28:elinks:INFO: Disabling clock on downlink 4
10:56:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:56:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:28:elinks:INFO: Disabling clock on downlink 0
10:56:28:elinks:INFO: Disabling clock on downlink 1
10:56:28:elinks:INFO: Disabling clock on downlink 2
10:56:28:elinks:INFO: Disabling clock on downlink 3
10:56:28:elinks:INFO: Disabling clock on downlink 4
10:56:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
10:56:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
10:56:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:28:elinks:INFO: Disabling clock on downlink 0
10:56:28:elinks:INFO: Disabling clock on downlink 1
10:56:28:elinks:INFO: Disabling clock on downlink 2
10:56:28:elinks:INFO: Disabling clock on downlink 3
10:56:28:elinks:INFO: Disabling clock on downlink 4
10:56:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:56:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:28:elinks:INFO: Disabling clock on downlink 0
10:56:28:elinks:INFO: Disabling clock on downlink 1
10:56:28:elinks:INFO: Disabling clock on downlink 2
10:56:28:elinks:INFO: Disabling clock on downlink 3
10:56:28:elinks:INFO: Disabling clock on downlink 4
10:56:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:56:29:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:29:elinks:INFO: Disabling clock on downlink 0
10:56:29:elinks:INFO: Disabling clock on downlink 1
10:56:29:elinks:INFO: Disabling clock on downlink 2
10:56:29:elinks:INFO: Disabling clock on downlink 3
10:56:29:elinks:INFO: Disabling clock on downlink 4
10:56:29:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:56:29:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:29:setup_element:INFO: Scanning clock phase
10:56:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:56:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:56:29:setup_element:INFO: Clock phase scan results for group 0, downlink 1
10:56:29:setup_element:INFO: Eye window for uplink 0 : X__________________________________________________________________________XXXXX
Clock Delay: 37
10:56:29:setup_element:INFO: Eye window for uplink 1 : X__________________________________________________________________________XXXXX
Clock Delay: 37
10:56:29:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:56:29:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:56:29:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
10:56:29:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
10:56:29:setup_element:INFO: Eye window for uplink 6 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:56:29:setup_element:INFO: Eye window for uplink 7 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:56:29:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:56:29:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
10:56:29:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:56:29:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
10:56:29:setup_element:INFO: Eye window for uplink 12: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:56:29:setup_element:INFO: Eye window for uplink 13: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
10:56:29:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:56:29:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:56:29:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
10:56:29:setup_element:INFO: Scanning data phases
10:56:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:56:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:56:34:setup_element:INFO: Data phase scan results for group 0, downlink 1
10:56:35:setup_element:INFO: Eye window for uplink 0 : ______________XXXX______________________
Data delay found: 35
10:56:35:setup_element:INFO: Eye window for uplink 1 : ___________XXXX_________________________
Data delay found: 32
10:56:35:setup_element:INFO: Eye window for uplink 2 : _____XXXX_______________________________
Data delay found: 26
10:56:35:setup_element:INFO: Eye window for uplink 3 : __XXXXX_________________________________
Data delay found: 24
10:56:35:setup_element:INFO: Eye window for uplink 4 : ___XXXX_________________________________
Data delay found: 24
10:56:35:setup_element:INFO: Eye window for uplink 5 : XXX__________________________________XXX
Data delay found: 19
10:56:35:setup_element:INFO: Eye window for uplink 6 : XXXXX_________________________________XX
Data delay found: 21
10:56:35:setup_element:INFO: Eye window for uplink 7 : X_________________________________XXXXXX
Data delay found: 17
10:56:35:setup_element:INFO: Eye window for uplink 8 : ________________________XXXXX___________
Data delay found: 6
10:56:35:setup_element:INFO: Eye window for uplink 9 : _____________________________XXXXX______
Data delay found: 11
10:56:35:setup_element:INFO: Eye window for uplink 10: ___________________________XXXXX________
Data delay found: 9
10:56:35:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXX____
Data delay found: 13
10:56:35:setup_element:INFO: Eye window for uplink 12: __________________________XXXXX_________
Data delay found: 8
10:56:35:setup_element:INFO: Eye window for uplink 13: _____________________________XXXXXX_____
Data delay found: 11
10:56:35:setup_element:INFO: Eye window for uplink 14: ___________________________XXXX_________
Data delay found: 8
10:56:35:setup_element:INFO: Eye window for uplink 15: _____________________________XXXXX______
Data delay found: 11
10:56:35:setup_element:INFO: Setting the data phase to 35 for uplink 0
10:56:35:setup_element:INFO: Setting the data phase to 32 for uplink 1
10:56:35:setup_element:INFO: Setting the data phase to 26 for uplink 2
10:56:35:setup_element:INFO: Setting the data phase to 24 for uplink 3
10:56:35:setup_element:INFO: Setting the data phase to 24 for uplink 4
10:56:35:setup_element:INFO: Setting the data phase to 19 for uplink 5
10:56:35:setup_element:INFO: Setting the data phase to 21 for uplink 6
10:56:35:setup_element:INFO: Setting the data phase to 17 for uplink 7
10:56:35:setup_element:INFO: Setting the data phase to 6 for uplink 8
10:56:35:setup_element:INFO: Setting the data phase to 11 for uplink 9
10:56:35:setup_element:INFO: Setting the data phase to 9 for uplink 10
10:56:35:setup_element:INFO: Setting the data phase to 13 for uplink 11
10:56:35:setup_element:INFO: Setting the data phase to 8 for uplink 12
10:56:35:setup_element:INFO: Setting the data phase to 11 for uplink 13
10:56:35:setup_element:INFO: Setting the data phase to 8 for uplink 14
10:56:35:setup_element:INFO: Setting the data phase to 11 for uplink 15
10:56:35:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: X__________________________________________________________________________XXXXX
Uplink 1: X__________________________________________________________________________XXXXX
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: ________________________________________________________________________XXXXXX__
Uplink 5: ________________________________________________________________________XXXXXX__
Uplink 6: X_________________________________________________________________________XXXXXX
Uplink 7: X_________________________________________________________________________XXXXXX
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: ________________________________________________________________________XXXXXXXX
Uplink 13: ________________________________________________________________________XXXXXXXX
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
Uplink 1:
Optimal Phase: 32
Window Length: 36
Eye Window: ___________XXXX_________________________
Uplink 2:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 4:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 5:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 6:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 7:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 8:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 10:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 13:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 14:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 15:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
]
10:56:35:setup_element:INFO: Beginning SMX ASICs map scan
10:56:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:56:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:56:35:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:56:35:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:56:35:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:56:35:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
10:56:35:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
10:56:35:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
10:56:35:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
10:56:35:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
10:56:35:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
10:56:35:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
10:56:35:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
10:56:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
10:56:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
10:56:36:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
10:56:36:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
10:56:36:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
10:56:36:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
10:56:36:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
10:56:36:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
10:56:37:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: X__________________________________________________________________________XXXXX
Uplink 1: X__________________________________________________________________________XXXXX
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: ________________________________________________________________________XXXXXX__
Uplink 5: ________________________________________________________________________XXXXXX__
Uplink 6: X_________________________________________________________________________XXXXXX
Uplink 7: X_________________________________________________________________________XXXXXX
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: ________________________________________________________________________XXXXXXXX
Uplink 13: ________________________________________________________________________XXXXXXXX
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
Uplink 1:
Optimal Phase: 32
Window Length: 36
Eye Window: ___________XXXX_________________________
Uplink 2:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 4:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 5:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 6:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 7:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 8:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 10:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 13:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 14:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 15:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
10:56:37:setup_element:INFO: Performing Elink synchronization
10:56:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:56:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:56:37:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:56:37:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:56:37:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
10:56:37:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:56:38:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
10:56:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:39:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 25.1 | 1224.5
10:56:39:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 25.1 | 1230.3
10:56:39:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 28.2 | 1212.7
10:56:39:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1195.1
10:56:39:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 28.2 | 1212.7
10:56:40:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 25.1 | 1218.6
10:56:40:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 21.9 | 1247.9
10:56:40:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1236.2
10:56:40:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:56:44:ST3_smx:INFO: chip: 0-0 34.556970 C 1189.190035 mV
10:56:44:ST3_smx:INFO: Electrons
10:56:44:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:56:46:ST3_smx:INFO: ----> Checking Analog response
10:56:46:ST3_smx:INFO: ----> Checking broken channels
10:56:46:ST3_smx:INFO: Total # broken ch: 2
10:56:46:ST3_smx:INFO: List FAST: [103, 115]
10:56:46:ST3_smx:INFO: List SLOW: []
10:56:46:ST3_smx:INFO: Holes
10:56:46:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:56:48:ST3_smx:INFO: ----> Checking Analog response
10:56:48:ST3_smx:INFO: ----> Checking broken channels
10:56:48:ST3_smx:INFO: Total # broken ch: 2
10:56:48:ST3_smx:INFO: List FAST: [103, 115]
10:56:48:ST3_smx:INFO: List SLOW: []
10:56:48:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:49:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1183.3
10:56:49:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 21.9 | 1230.3
10:56:49:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 28.2 | 1212.7
10:56:49:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1195.1
10:56:50:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 28.2 | 1212.7
10:56:50:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 28.2 | 1218.6
10:56:50:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 21.9 | 1247.9
10:56:50:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1236.2
10:56:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:56:55:ST3_smx:INFO: chip: 0-1 28.225000 C 1218.600960 mV
10:56:55:ST3_smx:INFO: Electrons
10:56:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:56:57:ST3_smx:INFO: ----> Checking Analog response
10:56:57:ST3_smx:INFO: ----> Checking broken channels
10:56:57:ST3_smx:INFO: Total # broken ch: 3
10:56:57:ST3_smx:INFO: List FAST: [50, 52, 55]
10:56:57:ST3_smx:INFO: List SLOW: []
10:56:57:ST3_smx:INFO: Holes
10:56:57:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:56:59:ST3_smx:INFO: ----> Checking Analog response
10:56:59:ST3_smx:INFO: ----> Checking broken channels
10:56:59:ST3_smx:INFO: Total # broken ch: 3
10:56:59:ST3_smx:INFO: List FAST: [50, 52, 55]
10:56:59:ST3_smx:INFO: List SLOW: []
10:56:59:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:59:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1183.3
10:57:00:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1212.7
10:57:00:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 28.2 | 1212.7
10:57:00:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1195.1
10:57:00:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 28.2 | 1212.7
10:57:00:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 28.2 | 1218.6
10:57:01:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 25.1 | 1247.9
10:57:01:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1230.3
10:57:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:05:ST3_smx:INFO: chip: 0-2 28.225000 C 1212.728715 mV
10:57:05:ST3_smx:INFO: Electrons
10:57:05:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:07:ST3_smx:INFO: ----> Checking Analog response
10:57:07:ST3_smx:INFO: ----> Checking broken channels
10:57:07:ST3_smx:INFO: Total # broken ch: 5
10:57:07:ST3_smx:INFO: List FAST: [16, 23, 76, 80, 93]
10:57:07:ST3_smx:INFO: List SLOW: []
10:57:07:ST3_smx:INFO: Holes
10:57:07:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:09:ST3_smx:INFO: ----> Checking Analog response
10:57:09:ST3_smx:INFO: ----> Checking broken channels
10:57:09:ST3_smx:INFO: Total # broken ch: 5
10:57:09:ST3_smx:INFO: List FAST: [16, 23, 76, 80, 93]
10:57:09:ST3_smx:INFO: List SLOW: []
10:57:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:10:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1183.3
10:57:10:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1212.7
10:57:10:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 31.4 | 1206.9
10:57:10:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1195.1
10:57:11:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 28.2 | 1218.6
10:57:11:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 28.2 | 1218.6
10:57:11:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 25.1 | 1253.7
10:57:11:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1230.3
10:57:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:15:ST3_smx:INFO: chip: 0-3 31.389742 C 1200.969315 mV
10:57:15:ST3_smx:INFO: Electrons
10:57:15:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:17:ST3_smx:INFO: ----> Checking Analog response
10:57:17:ST3_smx:INFO: ----> Checking broken channels
10:57:18:ST3_smx:INFO: Total # broken ch: 3
10:57:18:ST3_smx:INFO: List FAST: [38, 44, 83]
10:57:18:ST3_smx:INFO: List SLOW: []
10:57:18:ST3_smx:INFO: Holes
10:57:18:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:20:ST3_smx:INFO: ----> Checking Analog response
10:57:20:ST3_smx:INFO: ----> Checking broken channels
10:57:20:ST3_smx:INFO: Total # broken ch: 3
10:57:20:ST3_smx:INFO: List FAST: [38, 44, 83]
10:57:20:ST3_smx:INFO: List SLOW: []
10:57:20:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:20:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1183.3
10:57:20:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1212.7
10:57:21:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 31.4 | 1206.9
10:57:21:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1201.0
10:57:21:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 28.2 | 1218.6
10:57:21:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 28.2 | 1218.6
10:57:21:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 21.9 | 1253.7
10:57:22:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1230.3
10:57:22:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:26:ST3_smx:INFO: chip: 0-4 34.556970 C 1195.082160 mV
10:57:26:ST3_smx:INFO: Electrons
10:57:26:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:28:ST3_smx:INFO: ----> Checking Analog response
10:57:28:ST3_smx:INFO: ----> Checking broken channels
10:57:28:ST3_smx:INFO: Total # broken ch: 3
10:57:28:ST3_smx:INFO: List FAST: [77, 101, 121]
10:57:28:ST3_smx:INFO: List SLOW: []
10:57:28:ST3_smx:INFO: Holes
10:57:28:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:30:ST3_smx:INFO: ----> Checking Analog response
10:57:30:ST3_smx:INFO: ----> Checking broken channels
10:57:30:ST3_smx:INFO: Total # broken ch: 3
10:57:30:ST3_smx:INFO: List FAST: [77, 101, 121]
10:57:30:ST3_smx:INFO: List SLOW: []
10:57:30:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:30:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1183.3
10:57:31:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1212.7
10:57:31:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 31.4 | 1212.7
10:57:31:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1201.0
10:57:31:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 37.7 | 1189.2
10:57:32:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 28.2 | 1218.6
10:57:32:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 25.1 | 1253.7
10:57:32:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1230.3
10:57:32:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:36:ST3_smx:INFO: chip: 0-5 34.556970 C 1195.082160 mV
10:57:36:ST3_smx:INFO: Electrons
10:57:36:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:38:ST3_smx:INFO: ----> Checking Analog response
10:57:38:ST3_smx:INFO: ----> Checking broken channels
10:57:39:ST3_smx:INFO: Total # broken ch: 1
10:57:39:ST3_smx:INFO: List FAST: [4]
10:57:39:ST3_smx:INFO: List SLOW: []
10:57:39:ST3_smx:INFO: Holes
10:57:39:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:41:ST3_smx:INFO: ----> Checking Analog response
10:57:41:ST3_smx:INFO: ----> Checking broken channels
10:57:41:ST3_smx:INFO: Total # broken ch: 1
10:57:41:ST3_smx:INFO: List FAST: [4]
10:57:41:ST3_smx:INFO: List SLOW: []
10:57:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:41:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1183.3
10:57:41:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1212.7
10:57:42:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 31.4 | 1212.7
10:57:42:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1201.0
10:57:42:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 37.7 | 1195.1
10:57:42:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 37.7 | 1189.2
10:57:42:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 25.1 | 1253.7
10:57:43:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1236.2
10:57:43:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:47:ST3_smx:INFO: chip: 0-6 34.556970 C 1212.728715 mV
10:57:47:ST3_smx:INFO: Electrons
10:57:47:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:49:ST3_smx:INFO: ----> Checking Analog response
10:57:49:ST3_smx:INFO: ----> Checking broken channels
10:57:49:ST3_smx:INFO: Total # broken ch: 2
10:57:49:ST3_smx:INFO: List FAST: [16, 123]
10:57:49:ST3_smx:INFO: List SLOW: []
10:57:49:ST3_smx:INFO: Holes
10:57:50:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:57:52:ST3_smx:INFO: ----> Checking Analog response
10:57:52:ST3_smx:INFO: ----> Checking broken channels
10:57:52:ST3_smx:INFO: Total # broken ch: 2
10:57:52:ST3_smx:INFO: List FAST: [16, 123]
10:57:52:ST3_smx:INFO: List SLOW: []
10:57:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:52:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1189.2
10:57:52:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1212.7
10:57:53:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 31.4 | 1206.9
10:57:53:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1201.0
10:57:53:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 37.7 | 1195.1
10:57:53:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 34.6 | 1189.2
10:57:53:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 34.6 | 1212.7
10:57:54:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 25.1 | 1236.2
10:57:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:58:ST3_smx:INFO: chip: 0-7 34.556970 C 1206.851500 mV
10:57:58:ST3_smx:INFO: Electrons
10:57:58:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:58:00:ST3_smx:INFO: ----> Checking Analog response
10:58:00:ST3_smx:INFO: ----> Checking broken channels
10:58:00:ST3_smx:INFO: Total # broken ch: 2
10:58:00:ST3_smx:INFO: List FAST: [56, 103]
10:58:00:ST3_smx:INFO: List SLOW: []
10:58:00:ST3_smx:INFO: Holes
10:58:00:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:58:02:ST3_smx:INFO: ----> Checking Analog response
10:58:02:ST3_smx:INFO: ----> Checking broken channels
10:58:02:ST3_smx:INFO: Total # broken ch: 2
10:58:02:ST3_smx:INFO: List FAST: [56, 103]
10:58:02:ST3_smx:INFO: List SLOW: []
10:58:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:58:02:febtest:INFO: 0-0 | XA-000-08-003-000-000-019-03 | 37.7 | 1189.2
10:58:03:febtest:INFO: 0-1 | XA-000-08-002-000-003-229-01 | 28.2 | 1218.6
10:58:03:febtest:INFO: 0-2 | XA-000-08-002-000-003-199-15 | 31.4 | 1212.7
10:58:03:febtest:INFO: 0-3 | XA-000-08-002-001-006-225-02 | 34.6 | 1201.0
10:58:03:febtest:INFO: 0-4 | XA-000-08-002-000-003-198-15 | 34.6 | 1195.1
10:58:04:febtest:INFO: 0-5 | XA-000-08-002-000-003-234-01 | 37.7 | 1189.2
10:58:04:febtest:INFO: 0-6 | XA-000-08-002-000-003-225-01 | 34.6 | 1212.7
10:58:04:febtest:INFO: 0-7 | XA-000-08-002-000-003-193-15 | 34.6 | 1201.0
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_28-10_56_26', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-003-193-15', 'FUSED_ID': 6359364699116551199, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 2, 'N_BROKEN_FAST': '[56, 103]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 2, 'P_BROKEN_FAST': '[56, 103]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '1086', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.448', '1.4720', '1.846', '2.6390', '7.000', '1.5490', '7.000', '1.5490'], 'VI_aInit': ['2.450', '2.0440', '1.850', '0.3197', '7.000', '1.5550', '7.000', '1.5550'], 'VI_atEnd': ['2.450', '2.0440', '1.850', '0.3197', '7.000', '1.5550', '7.000', '1.5550'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_28-10_56_26
OPERATOR : Irakli K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1086
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.448', '1.4720', '1.846', '2.6390', '7.000', '1.5490', '7.000', '1.5490']
VI_after__Init : ['2.450', '1.9980', '1.850', '0.3207', '7.000', '1.5560', '7.000', '1.5560']
VI_at__the_End : ['2.450', '1.9980', '1.850', '0.3207', '7.000', '1.5560', '7.000', '1.5560']
10:58:16:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1020/TestDate_2023_11_28-10_56_26/
11:05:49:febtest:INFO: FEB 8-2 A @ GSI
11:06:02:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:06:02:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:06:02:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:06:02:febtest:INFO: Tsting FEB with SN 1017
11:06:03:smx_tester:INFO: Scanning setup
11:06:03:elinks:INFO: Disabling clock on downlink 0
11:06:03:elinks:INFO: Disabling clock on downlink 1
11:06:03:elinks:INFO: Disabling clock on downlink 2
11:06:03:elinks:INFO: Disabling clock on downlink 3
11:06:03:elinks:INFO: Disabling clock on downlink 4
11:06:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:06:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:06:04:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:06:04:elinks:INFO: Disabling clock on downlink 0
11:06:04:elinks:INFO: Disabling clock on downlink 1
11:06:04:elinks:INFO: Disabling clock on downlink 2
11:06:04:elinks:INFO: Disabling clock on downlink 3
11:06:04:elinks:INFO: Disabling clock on downlink 4
11:06:04:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
11:06:04:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
11:06:04:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:06:04:elinks:INFO: Disabling clock on downlink 0
11:06:04:elinks:INFO: Disabling clock on downlink 1
11:06:04:elinks:INFO: Disabling clock on downlink 2
11:06:04:elinks:INFO: Disabling clock on downlink 3
11:06:04:elinks:INFO: Disabling clock on downlink 4
11:06:04:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:06:04:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:06:04:elinks:INFO: Disabling clock on downlink 0
11:06:04:elinks:INFO: Disabling clock on downlink 1
11:06:04:elinks:INFO: Disabling clock on downlink 2
11:06:04:elinks:INFO: Disabling clock on downlink 3
11:06:04:elinks:INFO: Disabling clock on downlink 4
11:06:04:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:06:04:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:06:04:elinks:INFO: Disabling clock on downlink 0
11:06:04:elinks:INFO: Disabling clock on downlink 1
11:06:04:elinks:INFO: Disabling clock on downlink 2
11:06:04:elinks:INFO: Disabling clock on downlink 3
11:06:04:elinks:INFO: Disabling clock on downlink 4
11:06:04:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:06:04:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:06:04:setup_element:INFO: Scanning clock phase
11:06:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:06:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:06:05:setup_element:INFO: Clock phase scan results for group 0, downlink 1
11:06:05:setup_element:INFO: Eye window for uplink 0 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 1 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 2 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 3 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 4 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 5 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 6 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 7 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 8 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:06:05:setup_element:INFO: Eye window for uplink 9 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:06:05:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:06:05:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:06:05:setup_element:INFO: Eye window for uplink 12: X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 13: X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:06:05:setup_element:INFO: Eye window for uplink 14: _________________________________________________________________________XX_____
Clock Delay: 33
11:06:05:setup_element:INFO: Eye window for uplink 15: _________________________________________________________________________XX_____
Clock Delay: 33
11:06:05:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
11:06:05:setup_element:INFO: Scanning data phases
11:06:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:06:05:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:06:10:setup_element:INFO: Data phase scan results for group 0, downlink 1
11:06:10:setup_element:INFO: Eye window for uplink 0 : ____________XXXX________________________
Data delay found: 33
11:06:10:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
11:06:10:setup_element:INFO: Eye window for uplink 2 : _______XXXXX____________________________
Data delay found: 29
11:06:10:setup_element:INFO: Eye window for uplink 3 : _____XXXXX______________________________
Data delay found: 27
11:06:10:setup_element:INFO: Eye window for uplink 4 : _____XXXX_______________________________
Data delay found: 26
11:06:10:setup_element:INFO: Eye window for uplink 5 : _XXXX__________________________________X
Data delay found: 21
11:06:10:setup_element:INFO: Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
11:06:10:setup_element:INFO: Eye window for uplink 7 : _________________________________XXXXX__
Data delay found: 15
11:06:10:setup_element:INFO: Eye window for uplink 8 : __________________________XXXXX_________
Data delay found: 8
11:06:10:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXXX____
Data delay found: 12
11:06:10:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
11:06:10:setup_element:INFO: Eye window for uplink 11: ______________________________XXXXX_____
Data delay found: 12
11:06:10:setup_element:INFO: Eye window for uplink 12: ____________________________XXXXX_______
Data delay found: 10
11:06:10:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXXX___
Data delay found: 13
11:06:10:setup_element:INFO: Eye window for uplink 14: ___________________________XXXXX______XX
Data delay found: 13
11:06:10:setup_element:INFO: Eye window for uplink 15: _____________________________XXXXXXX__XX
Data delay found: 14
11:06:10:setup_element:INFO: Setting the data phase to 33 for uplink 0
11:06:10:setup_element:INFO: Setting the data phase to 30 for uplink 1
11:06:10:setup_element:INFO: Setting the data phase to 29 for uplink 2
11:06:10:setup_element:INFO: Setting the data phase to 27 for uplink 3
11:06:10:setup_element:INFO: Setting the data phase to 26 for uplink 4
11:06:10:setup_element:INFO: Setting the data phase to 21 for uplink 5
11:06:10:setup_element:INFO: Setting the data phase to 20 for uplink 6
11:06:10:setup_element:INFO: Setting the data phase to 15 for uplink 7
11:06:10:setup_element:INFO: Setting the data phase to 8 for uplink 8
11:06:10:setup_element:INFO: Setting the data phase to 12 for uplink 9
11:06:10:setup_element:INFO: Setting the data phase to 8 for uplink 10
11:06:10:setup_element:INFO: Setting the data phase to 12 for uplink 11
11:06:10:setup_element:INFO: Setting the data phase to 10 for uplink 12
11:06:10:setup_element:INFO: Setting the data phase to 13 for uplink 13
11:06:10:setup_element:INFO: Setting the data phase to 13 for uplink 14
11:06:10:setup_element:INFO: Setting the data phase to 14 for uplink 15
11:06:10:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: X________________________________________________________________________XXXXXXX
Uplink 5: X________________________________________________________________________XXXXXXX
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: ________________________________________________________________________XXXXXXXX
Uplink 9: ________________________________________________________________________XXXXXXXX
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: X________________________________________________________________________XXXXXXX
Uplink 13: X________________________________________________________________________XXXXXXX
Uplink 14: _________________________________________________________________________XX_____
Uplink 15: _________________________________________________________________________XX_____
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 4:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 5:
Optimal Phase: 21
Window Length: 34
Eye Window: _XXXX__________________________________X
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 14:
Optimal Phase: 13
Window Length: 27
Eye Window: ___________________________XXXXX______XX
Uplink 15:
Optimal Phase: 14
Window Length: 29
Eye Window: _____________________________XXXXXXX__XX
]
11:06:10:setup_element:INFO: Beginning SMX ASICs map scan
11:06:10:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:06:10:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:06:10:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:06:10:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:06:10:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:06:10:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
11:06:11:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
11:06:11:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
11:06:11:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
11:06:11:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
11:06:11:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
11:06:11:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
11:06:11:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
11:06:11:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
11:06:11:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
11:06:11:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
11:06:11:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
11:06:12:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
11:06:12:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
11:06:12:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
11:06:12:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
11:06:13:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: X________________________________________________________________________XXXXXXX
Uplink 5: X________________________________________________________________________XXXXXXX
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: ________________________________________________________________________XXXXXXXX
Uplink 9: ________________________________________________________________________XXXXXXXX
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: X________________________________________________________________________XXXXXXX
Uplink 13: X________________________________________________________________________XXXXXXX
Uplink 14: _________________________________________________________________________XX_____
Uplink 15: _________________________________________________________________________XX_____
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 4:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 5:
Optimal Phase: 21
Window Length: 34
Eye Window: _XXXX__________________________________X
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 14:
Optimal Phase: 13
Window Length: 27
Eye Window: ___________________________XXXXX______XX
Uplink 15:
Optimal Phase: 14
Window Length: 29
Eye Window: _____________________________XXXXXXX__XX
11:06:13:setup_element:INFO: Performing Elink synchronization
11:06:13:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:06:13:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:06:13:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:06:13:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:06:13:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
11:06:13:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:06:13:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0_1 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_0__upli_1
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_8 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_1__upli_8
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_2_3 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_2__upli_3
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3_10 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_3__upli_10
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_4_5 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_4__upli_5
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5_12 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_5__upli_12
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_6_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_6__upli_7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7_14 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_7__upli_14
11:06:14:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:06:15:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 25.1 | 1218.6
11:06:15:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 21.9 | 1230.3
11:06:15:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 28.2 | 1218.6
11:06:15:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 44.1 | 1159.7
11:06:15:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 25.1 | 1224.5
11:06:16:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 37.7 | 1165.6
11:06:16:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:06:16:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1189.2
11:06:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:06:20:ST3_smx:INFO: chip: 0-0 28.225000 C 1206.851500 mV
11:06:20:ST3_smx:INFO: Electrons
11:06:20:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:22:ST3_smx:INFO: ----> Checking Analog response
11:06:22:ST3_smx:INFO: ----> Checking broken channels
11:06:22:ST3_smx:INFO: Total # broken ch: 4
11:06:22:ST3_smx:INFO: List FAST: [65, 75, 88, 118]
11:06:22:ST3_smx:INFO: List SLOW: []
11:06:22:ST3_smx:INFO: Holes
11:06:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:24:ST3_smx:INFO: ----> Checking Analog response
11:06:24:ST3_smx:INFO: ----> Checking broken channels
11:06:25:ST3_smx:INFO: Total # broken ch: 4
11:06:25:ST3_smx:INFO: List FAST: [65, 75, 88, 118]
11:06:25:ST3_smx:INFO: List SLOW: []
11:06:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:06:25:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:06:25:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 21.9 | 1230.3
11:06:25:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 28.2 | 1218.6
11:06:26:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 44.1 | 1159.7
11:06:26:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 25.1 | 1224.5
11:06:26:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 37.7 | 1165.6
11:06:26:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:06:26:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1189.2
11:06:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:06:30:ST3_smx:INFO: chip: 0-1 15.590880 C 1259.567515 mV
11:06:30:ST3_smx:INFO: Electrons
11:06:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:33:ST3_smx:INFO: ----> Checking Analog response
11:06:33:ST3_smx:INFO: ----> Checking broken channels
11:06:33:ST3_smx:INFO: Total # broken ch: 1
11:06:33:ST3_smx:INFO: List FAST: [62]
11:06:33:ST3_smx:INFO: List SLOW: []
11:06:33:ST3_smx:INFO: Holes
11:06:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:35:ST3_smx:INFO: ----> Checking Analog response
11:06:35:ST3_smx:INFO: ----> Checking broken channels
11:06:35:ST3_smx:INFO: Total # broken ch: 1
11:06:35:ST3_smx:INFO: List FAST: [62]
11:06:35:ST3_smx:INFO: List SLOW: []
11:06:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:06:35:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:06:36:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1253.7
11:06:36:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 28.2 | 1218.6
11:06:36:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 44.1 | 1159.7
11:06:36:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 25.1 | 1224.5
11:06:37:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 37.7 | 1165.6
11:06:37:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:06:37:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1189.2
11:06:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:06:41:ST3_smx:INFO: chip: 0-2 31.389742 C 1206.851500 mV
11:06:41:ST3_smx:INFO: Electrons
11:06:41:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:43:ST3_smx:INFO: ----> Checking Analog response
11:06:43:ST3_smx:INFO: ----> Checking broken channels
11:06:43:ST3_smx:INFO: Total # broken ch: 4
11:06:43:ST3_smx:INFO: List FAST: [6, 34, 80, 82]
11:06:43:ST3_smx:INFO: List SLOW: []
11:06:43:ST3_smx:INFO: Holes
11:06:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:45:ST3_smx:INFO: ----> Checking Analog response
11:06:45:ST3_smx:INFO: ----> Checking broken channels
11:06:46:ST3_smx:INFO: Total # broken ch: 4
11:06:46:ST3_smx:INFO: List FAST: [6, 34, 80, 82]
11:06:46:ST3_smx:INFO: List SLOW: []
11:06:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:06:46:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:06:46:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1253.7
11:06:46:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 34.6 | 1201.0
11:06:47:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 44.1 | 1159.7
11:06:47:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 25.1 | 1224.5
11:06:47:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 40.9 | 1165.6
11:06:47:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:06:47:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1189.2
11:06:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:06:51:ST3_smx:INFO: chip: 0-3 47.250730 C 1153.732915 mV
11:06:51:ST3_smx:INFO: Electrons
11:06:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:53:ST3_smx:INFO: ----> Checking Analog response
11:06:53:ST3_smx:INFO: ----> Checking broken channels
11:06:54:ST3_smx:INFO: Total # broken ch: 1
11:06:54:ST3_smx:INFO: List FAST: [90]
11:06:54:ST3_smx:INFO: List SLOW: []
11:06:54:ST3_smx:INFO: Holes
11:06:54:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:06:56:ST3_smx:INFO: ----> Checking Analog response
11:06:56:ST3_smx:INFO: ----> Checking broken channels
11:06:56:ST3_smx:INFO: Total # broken ch: 1
11:06:56:ST3_smx:INFO: List FAST: [90]
11:06:56:ST3_smx:INFO: List SLOW: []
11:06:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:06:56:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:06:56:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1253.7
11:06:57:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 31.4 | 1206.9
11:06:57:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 50.4 | 1147.8
11:06:57:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 25.1 | 1224.5
11:06:57:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 40.9 | 1171.5
11:06:58:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:06:58:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1189.2
11:06:58:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:07:02:ST3_smx:INFO: chip: 0-4 25.062742 C 1224.468235 mV
11:07:02:ST3_smx:INFO: Electrons
11:07:02:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:04:ST3_smx:INFO: ----> Checking Analog response
11:07:04:ST3_smx:INFO: ----> Checking broken channels
11:07:04:ST3_smx:INFO: Total # broken ch: 4
11:07:04:ST3_smx:INFO: List FAST: [56, 57, 71, 72]
11:07:04:ST3_smx:INFO: List SLOW: []
11:07:04:ST3_smx:INFO: Holes
11:07:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:06:ST3_smx:INFO: ----> Checking Analog response
11:07:06:ST3_smx:INFO: ----> Checking broken channels
11:07:06:ST3_smx:INFO: Total # broken ch: 4
11:07:06:ST3_smx:INFO: List FAST: [56, 57, 71, 72]
11:07:06:ST3_smx:INFO: List SLOW: []
11:07:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:07:07:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:07:07:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1253.7
11:07:07:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 31.4 | 1206.9
11:07:07:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 50.4 | 1147.8
11:07:07:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 28.2 | 1218.6
11:07:08:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 40.9 | 1171.5
11:07:08:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:07:08:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1195.1
11:07:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:07:12:ST3_smx:INFO: chip: 0-5 34.556970 C 1195.082160 mV
11:07:12:ST3_smx:INFO: Electrons
11:07:12:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:14:ST3_smx:INFO: ----> Checking Analog response
11:07:14:ST3_smx:INFO: ----> Checking broken channels
11:07:14:ST3_smx:INFO: Total # broken ch: 3
11:07:14:ST3_smx:INFO: List FAST: [18, 53, 113]
11:07:14:ST3_smx:INFO: List SLOW: []
11:07:14:ST3_smx:INFO: Holes
11:07:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:16:ST3_smx:INFO: ----> Checking Analog response
11:07:16:ST3_smx:INFO: ----> Checking broken channels
11:07:16:ST3_smx:INFO: Total # broken ch: 3
11:07:16:ST3_smx:INFO: List FAST: [18, 53, 113]
11:07:16:ST3_smx:INFO: List SLOW: []
11:07:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:07:17:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:07:17:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1259.6
11:07:17:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 31.4 | 1206.9
11:07:17:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 50.4 | 1153.7
11:07:18:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 28.2 | 1218.6
11:07:18:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 34.6 | 1189.2
11:07:18:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 28.2 | 1218.6
11:07:18:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1195.1
11:07:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:07:22:ST3_smx:INFO: chip: 0-6 34.556970 C 1206.851500 mV
11:07:22:ST3_smx:INFO: Electrons
11:07:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:24:ST3_smx:INFO: ----> Checking Analog response
11:07:24:ST3_smx:INFO: ----> Checking broken channels
11:07:24:ST3_smx:INFO: Total # broken ch: 4
11:07:24:ST3_smx:INFO: List FAST: [29, 70, 84, 106]
11:07:24:ST3_smx:INFO: List SLOW: []
11:07:24:ST3_smx:INFO: Holes
11:07:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:26:ST3_smx:INFO: ----> Checking Analog response
11:07:26:ST3_smx:INFO: ----> Checking broken channels
11:07:27:ST3_smx:INFO: Total # broken ch: 4
11:07:27:ST3_smx:INFO: List FAST: [29, 70, 84, 106]
11:07:27:ST3_smx:INFO: List SLOW: []
11:07:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:07:27:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:07:27:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1259.6
11:07:27:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 31.4 | 1206.9
11:07:28:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 50.4 | 1147.8
11:07:28:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 28.2 | 1218.6
11:07:28:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 34.6 | 1189.2
11:07:28:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 34.6 | 1201.0
11:07:29:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1195.1
11:07:29:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:07:32:ST3_smx:INFO: chip: 0-7 34.556970 C 1200.969315 mV
11:07:33:ST3_smx:INFO: Electrons
11:07:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:35:ST3_smx:INFO: ----> Checking Analog response
11:07:35:ST3_smx:INFO: ----> Checking broken channels
11:07:35:ST3_smx:INFO: Total # broken ch: 2
11:07:35:ST3_smx:INFO: List FAST: [5, 16]
11:07:35:ST3_smx:INFO: List SLOW: []
11:07:35:ST3_smx:INFO: Holes
11:07:35:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
11:07:37:ST3_smx:INFO: ----> Checking Analog response
11:07:37:ST3_smx:INFO: ----> Checking broken channels
11:07:37:ST3_smx:INFO: Total # broken ch: 2
11:07:37:ST3_smx:INFO: List FAST: [5, 16]
11:07:37:ST3_smx:INFO: List SLOW: []
11:07:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:07:38:febtest:INFO: 0-0 | XA-000-08-002-001-006-226-02 | 31.4 | 1201.0
11:07:38:febtest:INFO: 0-1 | XA-000-08-002-001-006-239-02 | 15.6 | 1259.6
11:07:38:febtest:INFO: 0-2 | XA-000-08-002-001-006-230-02 | 31.4 | 1206.9
11:07:38:febtest:INFO: 0-3 | XA-000-08-002-001-006-241-05 | 50.4 | 1147.8
11:07:38:febtest:INFO: 0-4 | XA-000-08-002-001-006-228-02 | 28.2 | 1218.6
11:07:39:febtest:INFO: 0-5 | XA-000-08-002-001-006-222-11 | 34.6 | 1195.1
11:07:39:febtest:INFO: 0-6 | XA-000-08-002-001-006-233-02 | 34.6 | 1201.0
11:07:39:febtest:INFO: 0-7 | XA-000-08-002-001-006-224-02 | 34.6 | 1195.1
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_28-11_06_02', 'OPERATOR': 'Irakli K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-006-224-02', 'FUSED_ID': 6359364699117612546, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 2, 'N_BROKEN_FAST': '[5, 16]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 2, 'P_BROKEN_FAST': '[5, 16]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '1086', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.447', '2.0270', '1.846', '2.3780', '7.000', '1.5600', '7.000', '1.5600'], 'VI_aInit': ['2.450', '1.9980', '1.850', '0.3207', '7.000', '1.5560', '7.000', '1.5560'], 'VI_atEnd': ['2.450', '1.9980', '1.850', '0.3207', '7.000', '1.5560', '7.000', '1.5560'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_28-11_06_02
OPERATOR : Irakli K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1086
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.447', '2.0270', '1.846', '2.3780', '7.000', '1.5600', '7.000', '1.5600']
VI_after__Init : ['2.450', '1.9990', '1.850', '0.3154', '7.000', '1.5560', '7.000', '1.5560']
VI_at__the_End : ['2.450', '1.9990', '1.850', '0.3153', '7.000', '1.5560', '7.000', '1.5560']
11:08:06:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1017/TestDate_2023_11_28-11_06_02/