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FEB_1027 20.11.23 15:46:19
TextEdit.txt
15:46:17:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:46:18:febtest:INFO: FEB8.2 selected
15:46:18:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:46:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:46:19:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:46:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:46:20:febtest:INFO: Tsting FEB with SN 1029
15:46:21:smx_tester:INFO: Scanning setup
15:46:21:elinks:INFO: Disabling clock on downlink 0
15:46:21:elinks:INFO: Disabling clock on downlink 1
15:46:21:elinks:INFO: Disabling clock on downlink 2
15:46:21:elinks:INFO: Disabling clock on downlink 3
15:46:21:elinks:INFO: Disabling clock on downlink 4
15:46:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:46:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:21:elinks:INFO: Disabling clock on downlink 0
15:46:21:elinks:INFO: Disabling clock on downlink 1
15:46:21:elinks:INFO: Disabling clock on downlink 2
15:46:21:elinks:INFO: Disabling clock on downlink 3
15:46:21:elinks:INFO: Disabling clock on downlink 4
15:46:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
15:46:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
15:46:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:21:elinks:INFO: Disabling clock on downlink 0
15:46:21:elinks:INFO: Disabling clock on downlink 1
15:46:21:elinks:INFO: Disabling clock on downlink 2
15:46:21:elinks:INFO: Disabling clock on downlink 3
15:46:21:elinks:INFO: Disabling clock on downlink 4
15:46:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:46:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:21:elinks:INFO: Disabling clock on downlink 0
15:46:21:elinks:INFO: Disabling clock on downlink 1
15:46:21:elinks:INFO: Disabling clock on downlink 2
15:46:21:elinks:INFO: Disabling clock on downlink 3
15:46:21:elinks:INFO: Disabling clock on downlink 4
15:46:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:46:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:21:elinks:INFO: Disabling clock on downlink 0
15:46:21:elinks:INFO: Disabling clock on downlink 1
15:46:22:elinks:INFO: Disabling clock on downlink 2
15:46:22:elinks:INFO: Disabling clock on downlink 3
15:46:22:elinks:INFO: Disabling clock on downlink 4
15:46:22:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:46:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:46:22:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:46:22:setup_element:INFO: Scanning clock phase
15:46:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:46:22:setup_element:INFO: Clock phase scan results for group 0, downlink 1
15:46:22:setup_element:INFO: Eye window for uplink 0 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
15:46:22:setup_element:INFO: Eye window for uplink 1 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
15:46:22:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:46:22:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:46:22:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:22:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:22:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:46:22:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:46:22:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
15:46:22:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
15:46:22:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:46:22:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:46:22:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:46:22:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:46:22:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:22:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:46:22:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
15:46:22:setup_element:INFO: Scanning data phases
15:46:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:46:28:setup_element:INFO: Data phase scan results for group 0, downlink 1
15:46:28:setup_element:INFO: Eye window for uplink 0 : ___________XXXXXX_______________________
Data delay found: 33
15:46:28:setup_element:INFO: Eye window for uplink 1 : _______XXXXXX___________________________
Data delay found: 29
15:46:28:setup_element:INFO: Eye window for uplink 2 : _____XXXXXX_____________________________
Data delay found: 27
15:46:28:setup_element:INFO: Eye window for uplink 3 : ___XXXXX________________________________
Data delay found: 25
15:46:28:setup_element:INFO: Eye window for uplink 4 : ___XXXXXX_______________________________
Data delay found: 25
15:46:28:setup_element:INFO: Eye window for uplink 5 : XXXX__________________________________XX
Data delay found: 20
15:46:28:setup_element:INFO: Eye window for uplink 6 : ___________________________________XXXXX
Data delay found: 17
15:46:28:setup_element:INFO: Eye window for uplink 7 : ______________________________XXXXXX____
Data delay found: 12
15:46:28:setup_element:INFO: Eye window for uplink 8 : _______________________XXXX_____________
Data delay found: 4
15:46:28:setup_element:INFO: Eye window for uplink 9 : ___________________________XXXXXX_______
Data delay found: 9
15:46:28:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
15:46:28:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXX____
Data delay found: 13
15:46:28:setup_element:INFO: Eye window for uplink 12: _________________________XXXXX__________
Data delay found: 7
15:46:28:setup_element:INFO: Eye window for uplink 13: _____________________________XXXX_______
Data delay found: 10
15:46:28:setup_element:INFO: Eye window for uplink 14: ________________________XXXXX___________
Data delay found: 6
15:46:28:setup_element:INFO: Eye window for uplink 15: ___________________________XXXXX________
Data delay found: 9
15:46:28:setup_element:INFO: Setting the data phase to 33 for uplink 0
15:46:28:setup_element:INFO: Setting the data phase to 29 for uplink 1
15:46:28:setup_element:INFO: Setting the data phase to 27 for uplink 2
15:46:28:setup_element:INFO: Setting the data phase to 25 for uplink 3
15:46:28:setup_element:INFO: Setting the data phase to 25 for uplink 4
15:46:28:setup_element:INFO: Setting the data phase to 20 for uplink 5
15:46:28:setup_element:INFO: Setting the data phase to 17 for uplink 6
15:46:28:setup_element:INFO: Setting the data phase to 12 for uplink 7
15:46:28:setup_element:INFO: Setting the data phase to 4 for uplink 8
15:46:28:setup_element:INFO: Setting the data phase to 9 for uplink 9
15:46:28:setup_element:INFO: Setting the data phase to 8 for uplink 10
15:46:28:setup_element:INFO: Setting the data phase to 13 for uplink 11
15:46:28:setup_element:INFO: Setting the data phase to 7 for uplink 12
15:46:28:setup_element:INFO: Setting the data phase to 10 for uplink 13
15:46:28:setup_element:INFO: Setting the data phase to 6 for uplink 14
15:46:28:setup_element:INFO: Setting the data phase to 9 for uplink 15
15:46:28:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 68
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: _____________________________________________________________________XXXXXXXXX__
Uplink 9: _____________________________________________________________________XXXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 1:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 2:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 4:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 7:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 8:
Optimal Phase: 4
Window Length: 36
Eye Window: _______________________XXXX_____________
Uplink 9:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 13:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 14:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
]
15:46:28:setup_element:INFO: Beginning SMX ASICs map scan
15:46:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:46:28:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:46:28:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:46:28:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:46:28:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
15:46:28:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
15:46:28:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
15:46:28:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
15:46:28:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
15:46:28:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
15:46:28:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
15:46:28:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
15:46:29:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
15:46:29:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
15:46:29:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
15:46:29:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
15:46:29:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
15:46:29:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
15:46:29:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
15:46:29:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
15:46:30:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 68
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: _____________________________________________________________________XXXXXXXXX__
Uplink 9: _____________________________________________________________________XXXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 1:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 2:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 4:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 7:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 8:
Optimal Phase: 4
Window Length: 36
Eye Window: _______________________XXXX_____________
Uplink 9:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 13:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 14:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
15:46:30:setup_element:INFO: Performing Elink synchronization
15:46:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:46:30:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:46:30:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:46:30:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:46:30:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
15:46:30:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:46:31:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
15:46:32:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:32:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 40.9 | 1195.1
15:46:32:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 40.9 | 1195.1
15:46:32:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 44.1 | 1183.3
15:46:33:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1171.5
15:46:33:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1201.0
15:46:33:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
15:46:33:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
15:46:34:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1236.2
15:46:34:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:37:ST3_smx:INFO: chip: 0-0 47.250730 C 1171.483840 mV
15:46:37:ST3_smx:INFO: Electrons
15:46:37:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:46:40:ST3_smx:INFO: ----> Checking Analog response
15:46:40:ST3_smx:INFO: ----> Checking broken channels
15:46:40:ST3_smx:INFO: Total # broken ch: 0
15:46:40:ST3_smx:INFO: List FAST: []
15:46:40:ST3_smx:INFO: List SLOW: []
15:46:40:ST3_smx:INFO: Holes
15:46:40:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:46:42:ST3_smx:INFO: ----> Checking Analog response
15:46:42:ST3_smx:INFO: ----> Checking broken channels
15:46:42:ST3_smx:INFO: Total # broken ch: 0
15:46:42:ST3_smx:INFO: List FAST: []
15:46:42:ST3_smx:INFO: List SLOW: []
15:46:42:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:43:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:46:43:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 40.9 | 1189.2
15:46:43:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 44.1 | 1183.3
15:46:43:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1171.5
15:46:43:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1201.0
15:46:44:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
15:46:44:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
15:46:44:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1236.2
15:46:44:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:48:ST3_smx:INFO: chip: 0-1 47.250730 C 1177.390875 mV
15:46:48:ST3_smx:INFO: Electrons
15:46:48:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:46:50:ST3_smx:INFO: ----> Checking Analog response
15:46:50:ST3_smx:INFO: ----> Checking broken channels
15:46:50:ST3_smx:INFO: Total # broken ch: 0
15:46:50:ST3_smx:INFO: List FAST: []
15:46:50:ST3_smx:INFO: List SLOW: []
15:46:50:ST3_smx:INFO: Holes
15:46:50:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:46:52:ST3_smx:INFO: ----> Checking Analog response
15:46:52:ST3_smx:INFO: ----> Checking broken channels
15:46:53:ST3_smx:INFO: Total # broken ch: 0
15:46:53:ST3_smx:INFO: List FAST: []
15:46:53:ST3_smx:INFO: List SLOW: []
15:46:53:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:46:53:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:46:53:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
15:46:53:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 44.1 | 1183.3
15:46:53:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1171.5
15:46:54:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1201.0
15:46:54:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
15:46:54:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
15:46:54:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1242.0
15:46:55:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:46:58:ST3_smx:INFO: chip: 0-2 37.726682 C 1206.851500 mV
15:46:58:ST3_smx:INFO: Electrons
15:46:58:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:00:ST3_smx:INFO: ----> Checking Analog response
15:47:00:ST3_smx:INFO: ----> Checking broken channels
15:47:01:ST3_smx:INFO: Total # broken ch: 2
15:47:01:ST3_smx:INFO: List FAST: [96, 110]
15:47:01:ST3_smx:INFO: List SLOW: []
15:47:01:ST3_smx:INFO: Holes
15:47:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:03:ST3_smx:INFO: ----> Checking Analog response
15:47:03:ST3_smx:INFO: ----> Checking broken channels
15:47:03:ST3_smx:INFO: Total # broken ch: 2
15:47:03:ST3_smx:INFO: List FAST: [96, 110]
15:47:03:ST3_smx:INFO: List SLOW: []
15:47:03:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:03:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:47:03:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1177.4
15:47:04:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
15:47:04:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1171.5
15:47:04:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1201.0
15:47:04:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
15:47:05:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
15:47:05:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1242.0
15:47:05:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:09:ST3_smx:INFO: chip: 0-3 50.430383 C 1171.483840 mV
15:47:09:ST3_smx:INFO: Electrons
15:47:09:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:11:ST3_smx:INFO: ----> Checking Analog response
15:47:11:ST3_smx:INFO: ----> Checking broken channels
15:47:11:ST3_smx:INFO: Total # broken ch: 0
15:47:11:ST3_smx:INFO: List FAST: []
15:47:11:ST3_smx:INFO: List SLOW: []
15:47:11:ST3_smx:INFO: Holes
15:47:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:13:ST3_smx:INFO: ----> Checking Analog response
15:47:13:ST3_smx:INFO: ----> Checking broken channels
15:47:13:ST3_smx:INFO: Total # broken ch: 0
15:47:13:ST3_smx:INFO: List FAST: []
15:47:13:ST3_smx:INFO: List SLOW: []
15:47:13:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:14:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:47:14:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
15:47:14:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
15:47:14:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
15:47:14:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1201.0
15:47:15:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
15:47:15:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
15:47:15:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1236.2
15:47:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:19:ST3_smx:INFO: chip: 0-4 47.250730 C 1177.390875 mV
15:47:19:ST3_smx:INFO: Electrons
15:47:19:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:21:ST3_smx:INFO: ----> Checking Analog response
15:47:21:ST3_smx:INFO: ----> Checking broken channels
15:47:22:ST3_smx:INFO: Total # broken ch: 0
15:47:22:ST3_smx:INFO: List FAST: []
15:47:22:ST3_smx:INFO: List SLOW: []
15:47:22:ST3_smx:INFO: Holes
15:47:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:24:ST3_smx:INFO: ----> Checking Analog response
15:47:24:ST3_smx:INFO: ----> Checking broken channels
15:47:24:ST3_smx:INFO: Total # broken ch: 0
15:47:24:ST3_smx:INFO: List FAST: []
15:47:24:ST3_smx:INFO: List SLOW: []
15:47:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:24:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:47:24:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1177.4
15:47:24:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 37.7 | 1201.0
15:47:25:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
15:47:25:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
15:47:25:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
15:47:25:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
15:47:26:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1236.2
15:47:26:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:30:ST3_smx:INFO: chip: 0-5 53.612520 C 1153.732915 mV
15:47:30:ST3_smx:INFO: Electrons
15:47:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:32:ST3_smx:INFO: ----> Checking Analog response
15:47:32:ST3_smx:INFO: ----> Checking broken channels
15:47:32:ST3_smx:INFO: Total # broken ch: 0
15:47:32:ST3_smx:INFO: List FAST: []
15:47:32:ST3_smx:INFO: List SLOW: []
15:47:32:ST3_smx:INFO: Holes
15:47:32:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:34:ST3_smx:INFO: ----> Checking Analog response
15:47:34:ST3_smx:INFO: ----> Checking broken channels
15:47:34:ST3_smx:INFO: Total # broken ch: 0
15:47:34:ST3_smx:INFO: List FAST: []
15:47:34:ST3_smx:INFO: List SLOW: []
15:47:34:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:34:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:47:35:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
15:47:35:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
15:47:35:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
15:47:35:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
15:47:35:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 53.6 | 1147.8
15:47:36:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1201.0
15:47:36:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1236.2
15:47:36:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:41:ST3_smx:INFO: chip: 0-6 44.073563 C 1189.190035 mV
15:47:41:ST3_smx:INFO: Electrons
15:47:41:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:44:ST3_smx:INFO: ----> Checking Analog response
15:47:44:ST3_smx:INFO: ----> Checking broken channels
15:47:44:ST3_smx:INFO: Total # broken ch: 0
15:47:44:ST3_smx:INFO: List FAST: []
15:47:44:ST3_smx:INFO: List SLOW: []
15:47:44:ST3_smx:INFO: Holes
15:47:44:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:47:ST3_smx:INFO: ----> Checking Analog response
15:47:47:ST3_smx:INFO: ----> Checking broken channels
15:47:47:ST3_smx:INFO: Total # broken ch: 0
15:47:47:ST3_smx:INFO: List FAST: []
15:47:47:ST3_smx:INFO: List SLOW: []
15:47:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:48:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:47:48:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1177.4
15:47:48:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
15:47:48:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
15:47:48:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
15:47:49:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 53.6 | 1153.7
15:47:49:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 44.1 | 1183.3
15:47:49:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 28.2 | 1236.2
15:47:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:47:53:ST3_smx:INFO: chip: 0-7 44.073563 C 1183.292940 mV
15:47:53:ST3_smx:INFO: Electrons
15:47:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:56:ST3_smx:INFO: ----> Checking Analog response
15:47:56:ST3_smx:INFO: ----> Checking broken channels
15:47:56:ST3_smx:INFO: Total # broken ch: 1
15:47:56:ST3_smx:INFO: List FAST: [127]
15:47:56:ST3_smx:INFO: List SLOW: []
15:47:56:ST3_smx:INFO: Holes
15:47:56:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:47:58:ST3_smx:INFO: ----> Checking Analog response
15:47:58:ST3_smx:INFO: ----> Checking broken channels
15:47:58:ST3_smx:INFO: Total # broken ch: 1
15:47:58:ST3_smx:INFO: List FAST: [127]
15:47:58:ST3_smx:INFO: List SLOW: []
15:47:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:47:59:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
15:47:59:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1177.4
15:47:59:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
15:47:59:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
15:47:59:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
15:48:00:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 53.6 | 1147.8
15:48:00:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 44.1 | 1189.2
15:48:00:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 47.3 | 1177.4
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-15_46_19', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-001-218-11', 'FUSED_ID': 6359364699116543403, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 1, 'N_BROKEN_FAST': '[127]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 1, 'P_BROKEN_FAST': '[127]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.447', '1.9170', '1.845', '2.8660', '7.000', '1.5550', '7.000', '1.5550'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-15_46_19
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.447', '1.9170', '1.845', '2.8660', '7.000', '1.5550', '7.000', '1.5550']
VI_after__Init : ['2.450', '2.0040', '1.850', '0.3189', '7.000', '1.5520', '7.000', '1.5520']
VI_at__the_End : ['2.450', '2.0040', '1.850', '0.3189', '7.000', '1.5520', '7.000', '1.5520']
15:48:09:febtest:INFO: FEB 8-2 A @ GSI
15:48:17:ST3_Shared:INFO: Listo of operators:Irakli K.;