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FEB_1027 20.11.23 16:02:53
Info
16:02:28:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
16:02:29:febtest:INFO: FEB8.2 selected
16:02:30:ST3_Shared:INFO: Listo of operators:Irakli K.;
16:02:31:ST3_Shared:INFO: Listo of operators:Irakli K.; Ralf K.;
16:02:46:smx_tester:INFO: Setting Elink clock mode to 160 MHz
16:02:53:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:02:53:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
16:02:53:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:02:53:febtest:INFO: Tsting FEB with SN 2027
16:02:54:smx_tester:INFO: Scanning setup
16:02:54:elinks:INFO: Disabling clock on downlink 0
16:02:54:elinks:INFO: Disabling clock on downlink 1
16:02:54:elinks:INFO: Disabling clock on downlink 2
16:02:54:elinks:INFO: Disabling clock on downlink 3
16:02:54:elinks:INFO: Disabling clock on downlink 4
16:02:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:02:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
16:02:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:02:54:elinks:INFO: Disabling clock on downlink 0
16:02:54:elinks:INFO: Disabling clock on downlink 1
16:02:54:elinks:INFO: Disabling clock on downlink 2
16:02:54:elinks:INFO: Disabling clock on downlink 3
16:02:54:elinks:INFO: Disabling clock on downlink 4
16:02:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:02:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
16:02:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
16:02:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:02:54:elinks:INFO: Disabling clock on downlink 0
16:02:54:elinks:INFO: Disabling clock on downlink 1
16:02:54:elinks:INFO: Disabling clock on downlink 2
16:02:54:elinks:INFO: Disabling clock on downlink 3
16:02:54:elinks:INFO: Disabling clock on downlink 4
16:02:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:02:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:02:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:02:55:elinks:INFO: Disabling clock on downlink 0
16:02:55:elinks:INFO: Disabling clock on downlink 1
16:02:55:elinks:INFO: Disabling clock on downlink 2
16:02:55:elinks:INFO: Disabling clock on downlink 3
16:02:55:elinks:INFO: Disabling clock on downlink 4
16:02:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:02:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
16:02:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:02:55:elinks:INFO: Disabling clock on downlink 0
16:02:55:elinks:INFO: Disabling clock on downlink 1
16:02:55:elinks:INFO: Disabling clock on downlink 2
16:02:55:elinks:INFO: Disabling clock on downlink 3
16:02:55:elinks:INFO: Disabling clock on downlink 4
16:02:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:02:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
16:02:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:02:55:setup_element:INFO: Scanning clock phase
16:02:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:02:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:02:55:setup_element:INFO: Clock phase scan results for group 0, downlink 1
16:02:55:setup_element:INFO: Eye window for uplink 0 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
16:02:55:setup_element:INFO: Eye window for uplink 1 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
16:02:55:setup_element:INFO: Eye window for uplink 2 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
16:02:55:setup_element:INFO: Eye window for uplink 3 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
16:02:55:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:02:55:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:02:55:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
16:02:55:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
16:02:55:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:02:55:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:02:55:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
16:02:55:setup_element:INFO: Scanning data phases
16:02:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:02:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:03:01:setup_element:INFO: Data phase scan results for group 0, downlink 1
16:03:01:setup_element:INFO: Eye window for uplink 0 : _________XXXXXX_________________________
Data delay found: 31
16:03:01:setup_element:INFO: Eye window for uplink 1 : ______XXXXX_____________________________
Data delay found: 28
16:03:01:setup_element:INFO: Eye window for uplink 2 : _____XXXXX______________________________
Data delay found: 27
16:03:01:setup_element:INFO: Eye window for uplink 3 : __XXXXX_________________________________
Data delay found: 24
16:03:01:setup_element:INFO: Eye window for uplink 4 : ___XXXXX________________________________
Data delay found: 25
16:03:01:setup_element:INFO: Eye window for uplink 5 : XXXX__________________________________XX
Data delay found: 20
16:03:01:setup_element:INFO: Eye window for uplink 6 : __________________________________XXXXX_
Data delay found: 16
16:03:01:setup_element:INFO: Eye window for uplink 7 : ______________________________XXXXX_____
Data delay found: 12
16:03:01:setup_element:INFO: Eye window for uplink 8 : ______________________XXXXX_____________
Data delay found: 4
16:03:01:setup_element:INFO: Eye window for uplink 9 : ___________________________XXXXX________
Data delay found: 9
16:03:01:setup_element:INFO: Eye window for uplink 10: _________________________XXXXXX_________
Data delay found: 7
16:03:01:setup_element:INFO: Eye window for uplink 11: _____________________________XXXXX______
Data delay found: 11
16:03:01:setup_element:INFO: Eye window for uplink 12: ________________________XXXXX___________
Data delay found: 6
16:03:01:setup_element:INFO: Eye window for uplink 13: ____________________________XXXX________
Data delay found: 9
16:03:01:setup_element:INFO: Eye window for uplink 14: _______________________XXXXX____________
Data delay found: 5
16:03:01:setup_element:INFO: Eye window for uplink 15: _________________________XXXXXX_________
Data delay found: 7
16:03:01:setup_element:INFO: Setting the data phase to 31 for uplink 0
16:03:01:setup_element:INFO: Setting the data phase to 28 for uplink 1
16:03:01:setup_element:INFO: Setting the data phase to 27 for uplink 2
16:03:01:setup_element:INFO: Setting the data phase to 24 for uplink 3
16:03:01:setup_element:INFO: Setting the data phase to 25 for uplink 4
16:03:01:setup_element:INFO: Setting the data phase to 20 for uplink 5
16:03:01:setup_element:INFO: Setting the data phase to 16 for uplink 6
16:03:01:setup_element:INFO: Setting the data phase to 12 for uplink 7
16:03:01:setup_element:INFO: Setting the data phase to 4 for uplink 8
16:03:01:setup_element:INFO: Setting the data phase to 9 for uplink 9
16:03:01:setup_element:INFO: Setting the data phase to 7 for uplink 10
16:03:01:setup_element:INFO: Setting the data phase to 11 for uplink 11
16:03:01:setup_element:INFO: Setting the data phase to 6 for uplink 12
16:03:01:setup_element:INFO: Setting the data phase to 9 for uplink 13
16:03:01:setup_element:INFO: Setting the data phase to 5 for uplink 14
16:03:01:setup_element:INFO: Setting the data phase to 7 for uplink 15
16:03:01:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: _________________________________________________________________________XXXXXX_
Uplink 3: _________________________________________________________________________XXXXXX_
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXXXX_
Uplink 7: _______________________________________________________________________XXXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 1:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 2:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 4:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 7:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 8:
Optimal Phase: 4
Window Length: 35
Eye Window: ______________________XXXXX_____________
Uplink 9:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 10:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 11:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 12:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 13:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 14:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 15:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
]
16:03:01:setup_element:INFO: Beginning SMX ASICs map scan
16:03:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:03:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:03:01:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:03:01:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:03:01:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:03:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
16:03:01:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
16:03:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
16:03:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
16:03:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
16:03:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
16:03:01:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
16:03:01:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
16:03:01:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
16:03:01:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
16:03:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
16:03:02:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
16:03:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
16:03:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
16:03:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
16:03:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
16:03:03:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: _________________________________________________________________________XXXXXX_
Uplink 3: _________________________________________________________________________XXXXXX_
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXXXX_
Uplink 7: _______________________________________________________________________XXXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 1:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 2:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 4:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 7:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 8:
Optimal Phase: 4
Window Length: 35
Eye Window: ______________________XXXXX_____________
Uplink 9:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 10:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 11:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 12:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 13:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 14:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 15:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
16:03:03:setup_element:INFO: Performing Elink synchronization
16:03:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:03:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:03:03:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:03:03:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:03:03:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
16:03:03:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:03:04:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
16:03:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:03:05:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 34.6 | 1206.9
16:03:05:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 40.9 | 1189.2
16:03:05:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 44.1 | 1177.4
16:03:06:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 47.3 | 1177.4
16:03:06:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1206.9
16:03:06:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
16:03:06:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1195.1
16:03:07:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:03:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:03:10:ST3_smx:INFO: chip: 0-0 44.073563 C 1177.390875 mV
16:03:10:ST3_smx:INFO: Electrons
16:03:10:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:12:ST3_smx:INFO: ----> Checking Analog response
16:03:12:ST3_smx:INFO: ----> Checking broken channels
16:03:13:ST3_smx:INFO: Total # broken ch: 0
16:03:13:ST3_smx:INFO: List FAST: []
16:03:13:ST3_smx:INFO: List SLOW: []
16:03:13:ST3_smx:INFO: Holes
16:03:13:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:15:ST3_smx:INFO: ----> Checking Analog response
16:03:15:ST3_smx:INFO: ----> Checking broken channels
16:03:15:ST3_smx:INFO: Total # broken ch: 0
16:03:15:ST3_smx:INFO: List FAST: []
16:03:15:ST3_smx:INFO: List SLOW: []
16:03:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:03:15:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
16:03:15:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 40.9 | 1189.2
16:03:16:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 44.1 | 1183.3
16:03:16:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 47.3 | 1177.4
16:03:16:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 34.6 | 1206.9
16:03:16:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
16:03:17:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 37.7 | 1201.0
16:03:17:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:03:17:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:03:21:ST3_smx:INFO: chip: 0-1 44.073563 C 1177.390875 mV
16:03:21:ST3_smx:INFO: Electrons
16:03:21:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:23:ST3_smx:INFO: ----> Checking Analog response
16:03:23:ST3_smx:INFO: ----> Checking broken channels
16:03:23:ST3_smx:INFO: Total # broken ch: 0
16:03:23:ST3_smx:INFO: List FAST: []
16:03:23:ST3_smx:INFO: List SLOW: []
16:03:23:ST3_smx:INFO: Holes
16:03:23:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:25:ST3_smx:INFO: ----> Checking Analog response
16:03:25:ST3_smx:INFO: ----> Checking broken channels
16:03:25:ST3_smx:INFO: Total # broken ch: 0
16:03:25:ST3_smx:INFO: List FAST: []
16:03:25:ST3_smx:INFO: List SLOW: []
16:03:25:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:03:25:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
16:03:26:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
16:03:26:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 44.1 | 1183.3
16:03:26:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 47.3 | 1177.4
16:03:26:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1206.9
16:03:27:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
16:03:27:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1201.0
16:03:27:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:03:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:03:31:ST3_smx:INFO: chip: 0-2 37.726682 C 1206.851500 mV
16:03:31:ST3_smx:INFO: Electrons
16:03:31:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:33:ST3_smx:INFO: ----> Checking Analog response
16:03:33:ST3_smx:INFO: ----> Checking broken channels
16:03:33:ST3_smx:INFO: Total # broken ch: 0
16:03:33:ST3_smx:INFO: List FAST: []
16:03:33:ST3_smx:INFO: List SLOW: []
16:03:33:ST3_smx:INFO: Holes
16:03:33:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:35:ST3_smx:INFO: ----> Checking Analog response
16:03:35:ST3_smx:INFO: ----> Checking broken channels
16:03:35:ST3_smx:INFO: Total # broken ch: 0
16:03:35:ST3_smx:INFO: List FAST: []
16:03:35:ST3_smx:INFO: List SLOW: []
16:03:35:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:03:35:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
16:03:36:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
16:03:36:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 37.7 | 1201.0
16:03:36:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 47.3 | 1177.4
16:03:36:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1206.9
16:03:37:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
16:03:37:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1195.1
16:03:37:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:03:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:03:41:ST3_smx:INFO: chip: 0-3 50.430383 C 1171.483840 mV
16:03:41:ST3_smx:INFO: Electrons
16:03:41:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:43:ST3_smx:INFO: ----> Checking Analog response
16:03:43:ST3_smx:INFO: ----> Checking broken channels
16:03:43:ST3_smx:INFO: Total # broken ch: 0
16:03:43:ST3_smx:INFO: List FAST: []
16:03:43:ST3_smx:INFO: List SLOW: []
16:03:43:ST3_smx:INFO: Holes
16:03:43:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:45:ST3_smx:INFO: ----> Checking Analog response
16:03:45:ST3_smx:INFO: ----> Checking broken channels
16:03:46:ST3_smx:INFO: Total # broken ch: 0
16:03:46:ST3_smx:INFO: List FAST: []
16:03:46:ST3_smx:INFO: List SLOW: []
16:03:46:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:03:46:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
16:03:46:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
16:03:46:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 37.7 | 1201.0
16:03:46:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
16:03:47:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 37.7 | 1206.9
16:03:47:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
16:03:47:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1201.0
16:03:47:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:03:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:03:51:ST3_smx:INFO: chip: 0-4 47.250730 C 1177.390875 mV
16:03:51:ST3_smx:INFO: Electrons
16:03:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:53:ST3_smx:INFO: ----> Checking Analog response
16:03:53:ST3_smx:INFO: ----> Checking broken channels
16:03:53:ST3_smx:INFO: Total # broken ch: 0
16:03:53:ST3_smx:INFO: List FAST: []
16:03:53:ST3_smx:INFO: List SLOW: []
16:03:53:ST3_smx:INFO: Holes
16:03:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:03:55:ST3_smx:INFO: ----> Checking Analog response
16:03:55:ST3_smx:INFO: ----> Checking broken channels
16:03:56:ST3_smx:INFO: Total # broken ch: 0
16:03:56:ST3_smx:INFO: List FAST: []
16:03:56:ST3_smx:INFO: List SLOW: []
16:03:56:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:03:56:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1177.4
16:03:56:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1177.4
16:03:56:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
16:03:56:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1171.5
16:03:57:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
16:03:57:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 60.0 | 1130.0
16:03:57:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1201.0
16:03:57:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1224.5
16:03:58:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:04:01:ST3_smx:INFO: chip: 0-5 53.612520 C 1153.732915 mV
16:04:01:ST3_smx:INFO: Electrons
16:04:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:04:03:ST3_smx:INFO: ----> Checking Analog response
16:04:03:ST3_smx:INFO: ----> Checking broken channels
16:04:03:ST3_smx:INFO: Total # broken ch: 0
16:04:03:ST3_smx:INFO: List FAST: []
16:04:03:ST3_smx:INFO: List SLOW: []
16:04:03:ST3_smx:INFO: Holes
16:04:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:04:05:ST3_smx:INFO: ----> Checking Analog response
16:04:05:ST3_smx:INFO: ----> Checking broken channels
16:04:06:ST3_smx:INFO: Total # broken ch: 0
16:04:06:ST3_smx:INFO: List FAST: []
16:04:06:ST3_smx:INFO: List SLOW: []
16:04:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:04:06:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
16:04:06:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1177.4
16:04:06:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
16:04:07:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
16:04:07:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
16:04:07:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 56.8 | 1147.8
16:04:07:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 40.9 | 1195.1
16:04:07:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:04:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:04:11:ST3_smx:INFO: chip: 0-6 44.073563 C 1189.190035 mV
16:04:11:ST3_smx:INFO: Electrons
16:04:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:04:13:ST3_smx:INFO: ----> Checking Analog response
16:04:13:ST3_smx:INFO: ----> Checking broken channels
16:04:14:ST3_smx:INFO: Total # broken ch: 0
16:04:14:ST3_smx:INFO: List FAST: []
16:04:14:ST3_smx:INFO: List SLOW: []
16:04:14:ST3_smx:INFO: Holes
16:04:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:04:16:ST3_smx:INFO: ----> Checking Analog response
16:04:16:ST3_smx:INFO: ----> Checking broken channels
16:04:16:ST3_smx:INFO: Total # broken ch: 0
16:04:16:ST3_smx:INFO: List FAST: []
16:04:16:ST3_smx:INFO: List SLOW: []
16:04:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:04:16:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1177.4
16:04:16:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
16:04:16:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
16:04:17:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
16:04:17:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
16:04:17:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 53.6 | 1153.7
16:04:17:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 44.1 | 1183.3
16:04:18:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 34.6 | 1218.6
16:04:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:04:21:ST3_smx:INFO: chip: 0-7 44.073563 C 1183.292940 mV
16:04:21:ST3_smx:INFO: Electrons
16:04:21:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:04:23:ST3_smx:INFO: ----> Checking Analog response
16:04:23:ST3_smx:INFO: ----> Checking broken channels
16:04:24:ST3_smx:INFO: Total # broken ch: 0
16:04:24:ST3_smx:INFO: List FAST: []
16:04:24:ST3_smx:INFO: List SLOW: []
16:04:24:ST3_smx:INFO: Holes
16:04:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:04:26:ST3_smx:INFO: ----> Checking Analog response
16:04:26:ST3_smx:INFO: ----> Checking broken channels
16:04:26:ST3_smx:INFO: Total # broken ch: 0
16:04:26:ST3_smx:INFO: List FAST: []
16:04:26:ST3_smx:INFO: List SLOW: []
16:04:26:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:04:26:febtest:INFO: 0-0 | XA-000-08-002-000-001-216-11 | 47.3 | 1171.5
16:04:26:febtest:INFO: 0-1 | XA-000-08-002-000-001-225-02 | 47.3 | 1171.5
16:04:26:febtest:INFO: 0-2 | XA-000-08-002-000-001-220-11 | 40.9 | 1201.0
16:04:27:febtest:INFO: 0-3 | XA-000-08-002-000-001-222-11 | 50.4 | 1165.6
16:04:27:febtest:INFO: 0-4 | XA-000-08-002-000-001-223-11 | 47.3 | 1171.5
16:04:27:febtest:INFO: 0-5 | XA-000-08-002-000-001-214-11 | 56.8 | 1153.7
16:04:27:febtest:INFO: 0-6 | XA-000-08-002-000-001-226-02 | 44.1 | 1189.2
16:04:28:febtest:INFO: 0-7 | XA-000-08-002-000-001-218-11 | 47.3 | 1177.4
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-16_02_53', 'OPERATOR': 'Irakli K.; Ralf K.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-001-218-11', 'FUSED_ID': 6359364699116543403, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.448', '1.5740', '1.845', '2.8560', '7.000', '1.5450', '7.000', '1.5450'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-16_02_53
OPERATOR : Irakli K.; Ralf K.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.448', '1.5740', '1.845', '2.8560', '7.000', '1.5450', '7.000', '1.5450']
VI_after__Init : ['2.450', '2.0050', '1.850', '0.3189', '7.000', '1.5510', '7.000', '1.5510']
VI_at__the_End : ['2.450', '2.0050', '1.850', '0.3189', '7.000', '1.5510', '7.000', '1.5510']
16:04:52:febtest:INFO: FEB 8-2 A @ GSI
16:05:02:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1027/TestDate_2023_11_20-16_02_53/