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FEB_1029 20.11.23 16:24:19
TextEdit.txt
16:24:15:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
16:24:16:febtest:INFO: FEB8.2 selected
16:24:16:smx_tester:INFO: Setting Elink clock mode to 160 MHz
16:24:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:24:19:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
16:24:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:24:19:febtest:INFO: Tsting FEB with SN 1029
16:24:20:smx_tester:INFO: Scanning setup
16:24:20:elinks:INFO: Disabling clock on downlink 0
16:24:20:elinks:INFO: Disabling clock on downlink 1
16:24:20:elinks:INFO: Disabling clock on downlink 2
16:24:20:elinks:INFO: Disabling clock on downlink 3
16:24:20:elinks:INFO: Disabling clock on downlink 4
16:24:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:24:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
16:24:20:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:24:20:elinks:INFO: Disabling clock on downlink 0
16:24:20:elinks:INFO: Disabling clock on downlink 1
16:24:20:elinks:INFO: Disabling clock on downlink 2
16:24:20:elinks:INFO: Disabling clock on downlink 3
16:24:20:elinks:INFO: Disabling clock on downlink 4
16:24:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:24:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
16:24:21:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
16:24:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:24:21:elinks:INFO: Disabling clock on downlink 0
16:24:21:elinks:INFO: Disabling clock on downlink 1
16:24:21:elinks:INFO: Disabling clock on downlink 2
16:24:21:elinks:INFO: Disabling clock on downlink 3
16:24:21:elinks:INFO: Disabling clock on downlink 4
16:24:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:24:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:24:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:24:21:elinks:INFO: Disabling clock on downlink 0
16:24:21:elinks:INFO: Disabling clock on downlink 1
16:24:21:elinks:INFO: Disabling clock on downlink 2
16:24:21:elinks:INFO: Disabling clock on downlink 3
16:24:21:elinks:INFO: Disabling clock on downlink 4
16:24:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:24:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
16:24:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:24:21:elinks:INFO: Disabling clock on downlink 0
16:24:21:elinks:INFO: Disabling clock on downlink 1
16:24:21:elinks:INFO: Disabling clock on downlink 2
16:24:21:elinks:INFO: Disabling clock on downlink 3
16:24:21:elinks:INFO: Disabling clock on downlink 4
16:24:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:24:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
16:24:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:24:21:setup_element:INFO: Scanning clock phase
16:24:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:24:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:24:22:setup_element:INFO: Clock phase scan results for group 0, downlink 1
16:24:22:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
16:24:22:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
16:24:22:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
16:24:22:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
16:24:22:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:24:22:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:24:22:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:24:22:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:24:22:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:24:22:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:24:22:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:24:22:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:24:22:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:24:22:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:24:22:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:24:22:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:24:22:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
16:24:22:setup_element:INFO: Scanning data phases
16:24:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:24:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:24:27:setup_element:INFO: Data phase scan results for group 0, downlink 1
16:24:27:setup_element:INFO: Eye window for uplink 0 : ________XXXXXX__________________________
Data delay found: 30
16:24:28:setup_element:INFO: Eye window for uplink 1 : _____XXXXX______________________________
Data delay found: 27
16:24:28:setup_element:INFO: Eye window for uplink 2 : _____XXXXX______________________________
Data delay found: 27
16:24:28:setup_element:INFO: Eye window for uplink 3 : __XXXXXX________________________________
Data delay found: 24
16:24:28:setup_element:INFO: Eye window for uplink 4 : XXXXX__________________________________X
Data delay found: 21
16:24:28:setup_element:INFO: Eye window for uplink 5 : X__________________________________XXXXX
Data delay found: 17
16:24:28:setup_element:INFO: Eye window for uplink 6 : X___________________________________XXXX
Data delay found: 18
16:24:28:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXX____
Data delay found: 13
16:24:28:setup_element:INFO: Eye window for uplink 8 : _____________________XXXXX______________
Data delay found: 3
16:24:28:setup_element:INFO: Eye window for uplink 9 : _________________________XXXXXX_________
Data delay found: 7
16:24:28:setup_element:INFO: Eye window for uplink 10: _______________________XXXXX____________
Data delay found: 5
16:24:28:setup_element:INFO: Eye window for uplink 11: ___________________________XXXXX________
Data delay found: 9
16:24:28:setup_element:INFO: Eye window for uplink 12: _______________________XXXXX____________
Data delay found: 5
16:24:28:setup_element:INFO: Eye window for uplink 13: __________________________XXXXX_________
Data delay found: 8
16:24:28:setup_element:INFO: Eye window for uplink 14: _________________________XXXX___________
Data delay found: 6
16:24:28:setup_element:INFO: Eye window for uplink 15: ___________________________XXXXXX_______
Data delay found: 9
16:24:28:setup_element:INFO: Setting the data phase to 30 for uplink 0
16:24:28:setup_element:INFO: Setting the data phase to 27 for uplink 1
16:24:28:setup_element:INFO: Setting the data phase to 27 for uplink 2
16:24:28:setup_element:INFO: Setting the data phase to 24 for uplink 3
16:24:28:setup_element:INFO: Setting the data phase to 21 for uplink 4
16:24:28:setup_element:INFO: Setting the data phase to 17 for uplink 5
16:24:28:setup_element:INFO: Setting the data phase to 18 for uplink 6
16:24:28:setup_element:INFO: Setting the data phase to 13 for uplink 7
16:24:28:setup_element:INFO: Setting the data phase to 3 for uplink 8
16:24:28:setup_element:INFO: Setting the data phase to 7 for uplink 9
16:24:28:setup_element:INFO: Setting the data phase to 5 for uplink 10
16:24:28:setup_element:INFO: Setting the data phase to 9 for uplink 11
16:24:28:setup_element:INFO: Setting the data phase to 5 for uplink 12
16:24:28:setup_element:INFO: Setting the data phase to 8 for uplink 13
16:24:28:setup_element:INFO: Setting the data phase to 6 for uplink 14
16:24:28:setup_element:INFO: Setting the data phase to 9 for uplink 15
16:24:28:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 1:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 2:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 4:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 5:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 6:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 10:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 11:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 12:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 13:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 14:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
]
16:24:28:setup_element:INFO: Beginning SMX ASICs map scan
16:24:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:24:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:24:28:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:24:28:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:24:28:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:24:28:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
16:24:28:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
16:24:28:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
16:24:28:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
16:24:28:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
16:24:28:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
16:24:28:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
16:24:28:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
16:24:28:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
16:24:29:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
16:24:29:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
16:24:29:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
16:24:29:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
16:24:29:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
16:24:29:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
16:24:29:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
16:24:30:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 1:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 2:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 4:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 5:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 6:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 10:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 11:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 12:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 13:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 14:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
16:24:30:setup_element:INFO: Performing Elink synchronization
16:24:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:24:30:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:24:30:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:24:30:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:24:30:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
16:24:30:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:24:31:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
16:24:32:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:24:32:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1147.8
16:24:32:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
16:24:32:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 56.8 | 1147.8
16:24:33:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1195.1
16:24:33:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
16:24:33:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:24:33:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:24:34:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:24:34:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:24:37:ST3_smx:INFO: chip: 0-0 53.612520 C 1159.654860 mV
16:24:37:ST3_smx:INFO: Electrons
16:24:37:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:24:39:ST3_smx:INFO: ----> Checking Analog response
16:24:39:ST3_smx:INFO: ----> Checking broken channels
16:24:40:ST3_smx:INFO: Total # broken ch: 0
16:24:40:ST3_smx:INFO: List FAST: []
16:24:40:ST3_smx:INFO: List SLOW: []
16:24:40:ST3_smx:INFO: Holes
16:24:40:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:24:41:ST3_smx:INFO: ----> Checking Analog response
16:24:41:ST3_smx:INFO: ----> Checking broken channels
16:24:42:ST3_smx:INFO: Total # broken ch: 0
16:24:42:ST3_smx:INFO: List FAST: []
16:24:42:ST3_smx:INFO: List SLOW: []
16:24:42:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:24:42:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:24:42:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
16:24:42:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 56.8 | 1147.8
16:24:43:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1195.1
16:24:43:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1153.7
16:24:43:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:24:43:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:24:44:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:24:44:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:24:47:ST3_smx:INFO: chip: 0-1 53.612520 C 1177.390875 mV
16:24:47:ST3_smx:INFO: Electrons
16:24:47:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:24:49:ST3_smx:INFO: ----> Checking Analog response
16:24:49:ST3_smx:INFO: ----> Checking broken channels
16:24:49:ST3_smx:INFO: Total # broken ch: 0
16:24:49:ST3_smx:INFO: List FAST: []
16:24:49:ST3_smx:INFO: List SLOW: []
16:24:49:ST3_smx:INFO: Holes
16:24:49:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:24:51:ST3_smx:INFO: ----> Checking Analog response
16:24:51:ST3_smx:INFO: ----> Checking broken channels
16:24:52:ST3_smx:INFO: Total # broken ch: 0
16:24:52:ST3_smx:INFO: List FAST: []
16:24:52:ST3_smx:INFO: List SLOW: []
16:24:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:24:52:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:24:52:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:24:52:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 56.8 | 1147.8
16:24:53:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1195.1
16:24:53:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
16:24:53:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1135.9
16:24:53:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:24:54:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:24:54:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:24:58:ST3_smx:INFO: chip: 0-2 63.173842 C 1135.937260 mV
16:24:58:ST3_smx:INFO: Electrons
16:24:58:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:00:ST3_smx:INFO: ----> Checking Analog response
16:25:00:ST3_smx:INFO: ----> Checking broken channels
16:25:00:ST3_smx:INFO: Total # broken ch: 0
16:25:00:ST3_smx:INFO: List FAST: []
16:25:00:ST3_smx:INFO: List SLOW: []
16:25:00:ST3_smx:INFO: Holes
16:25:00:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:02:ST3_smx:INFO: ----> Checking Analog response
16:25:02:ST3_smx:INFO: ----> Checking broken channels
16:25:02:ST3_smx:INFO: Total # broken ch: 0
16:25:02:ST3_smx:INFO: List FAST: []
16:25:02:ST3_smx:INFO: List SLOW: []
16:25:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:25:02:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:25:03:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:25:03:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1130.0
16:25:03:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1195.1
16:25:03:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
16:25:03:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:25:04:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:25:04:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:25:04:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:25:08:ST3_smx:INFO: chip: 0-3 56.797143 C 1153.732915 mV
16:25:08:ST3_smx:INFO: Electrons
16:25:08:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:10:ST3_smx:INFO: ----> Checking Analog response
16:25:10:ST3_smx:INFO: ----> Checking broken channels
16:25:10:ST3_smx:INFO: Total # broken ch: 0
16:25:10:ST3_smx:INFO: List FAST: []
16:25:10:ST3_smx:INFO: List SLOW: []
16:25:10:ST3_smx:INFO: Holes
16:25:10:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:12:ST3_smx:INFO: ----> Checking Analog response
16:25:12:ST3_smx:INFO: ----> Checking broken channels
16:25:12:ST3_smx:INFO: Total # broken ch: 0
16:25:12:ST3_smx:INFO: List FAST: []
16:25:12:ST3_smx:INFO: List SLOW: []
16:25:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:25:12:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:25:13:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:25:13:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1135.9
16:25:13:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:25:13:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1153.7
16:25:14:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:25:14:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:25:14:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1230.3
16:25:14:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:25:18:ST3_smx:INFO: chip: 0-4 63.173842 C 1129.995435 mV
16:25:18:ST3_smx:INFO: Electrons
16:25:18:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:20:ST3_smx:INFO: ----> Checking Analog response
16:25:20:ST3_smx:INFO: ----> Checking broken channels
16:25:20:ST3_smx:INFO: Total # broken ch: 0
16:25:20:ST3_smx:INFO: List FAST: []
16:25:20:ST3_smx:INFO: List SLOW: []
16:25:20:ST3_smx:INFO: Holes
16:25:20:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:22:ST3_smx:INFO: ----> Checking Analog response
16:25:22:ST3_smx:INFO: ----> Checking broken channels
16:25:22:ST3_smx:INFO: Total # broken ch: 0
16:25:22:ST3_smx:INFO: List FAST: []
16:25:22:ST3_smx:INFO: List SLOW: []
16:25:22:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:25:22:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:25:23:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:25:23:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1135.9
16:25:23:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:25:23:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 63.2 | 1124.0
16:25:23:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:25:24:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:25:24:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1230.3
16:25:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:25:28:ST3_smx:INFO: chip: 0-5 63.173842 C 1147.806000 mV
16:25:28:ST3_smx:INFO: Electrons
16:25:28:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:30:ST3_smx:INFO: ----> Checking Analog response
16:25:30:ST3_smx:INFO: ----> Checking broken channels
16:25:30:ST3_smx:INFO: Total # broken ch: 0
16:25:30:ST3_smx:INFO: List FAST: []
16:25:30:ST3_smx:INFO: List SLOW: []
16:25:30:ST3_smx:INFO: Holes
16:25:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:32:ST3_smx:INFO: ----> Checking Analog response
16:25:32:ST3_smx:INFO: ----> Checking broken channels
16:25:32:ST3_smx:INFO: Total # broken ch: 0
16:25:32:ST3_smx:INFO: List FAST: []
16:25:32:ST3_smx:INFO: List SLOW: []
16:25:32:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:25:32:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:25:33:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:25:33:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1135.9
16:25:33:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:25:33:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 63.2 | 1124.0
16:25:34:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1147.8
16:25:34:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:25:34:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:25:34:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:25:38:ST3_smx:INFO: chip: 0-6 66.365920 C 1135.937260 mV
16:25:38:ST3_smx:INFO: Electrons
16:25:38:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:40:ST3_smx:INFO: ----> Checking Analog response
16:25:40:ST3_smx:INFO: ----> Checking broken channels
16:25:40:ST3_smx:INFO: Total # broken ch: 0
16:25:40:ST3_smx:INFO: List FAST: []
16:25:40:ST3_smx:INFO: List SLOW: []
16:25:40:ST3_smx:INFO: Holes
16:25:40:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:42:ST3_smx:INFO: ----> Checking Analog response
16:25:42:ST3_smx:INFO: ----> Checking broken channels
16:25:42:ST3_smx:INFO: Total # broken ch: 0
16:25:42:ST3_smx:INFO: List FAST: []
16:25:42:ST3_smx:INFO: List SLOW: []
16:25:42:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:25:42:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:25:43:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:25:43:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1135.9
16:25:43:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:25:43:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 63.2 | 1130.0
16:25:44:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1147.8
16:25:44:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:25:44:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1230.3
16:25:44:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:25:48:ST3_smx:INFO: chip: 0-7 56.797143 C 1171.483840 mV
16:25:48:ST3_smx:INFO: Electrons
16:25:48:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:49:ST3_smx:INFO: ----> Checking Analog response
16:25:49:ST3_smx:INFO: ----> Checking broken channels
16:25:50:ST3_smx:INFO: Total # broken ch: 0
16:25:50:ST3_smx:INFO: List FAST: []
16:25:50:ST3_smx:INFO: List SLOW: []
16:25:50:ST3_smx:INFO: Holes
16:25:50:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:25:52:ST3_smx:INFO: ----> Checking Analog response
16:25:52:ST3_smx:INFO: ----> Checking broken channels
16:25:52:ST3_smx:INFO: Total # broken ch: 0
16:25:52:ST3_smx:INFO: List FAST: []
16:25:52:ST3_smx:INFO: List SLOW: []
16:25:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:25:52:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:25:52:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:25:53:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1135.9
16:25:53:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:25:53:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 63.2 | 1130.0
16:25:53:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:25:53:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:25:54:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 56.8 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-16_24_19', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-001-036-13', 'FUSED_ID': 6359364699116540493, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.447', '1.8770', '1.846', '2.3470', '7.001', '1.5590', '7.001', '1.5590'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-16_24_19
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.447', '1.8770', '1.846', '2.3470', '7.001', '1.5590', '7.001', '1.5590']
VI_after__Init : ['2.450', '2.0450', '1.850', '0.3258', '7.000', '1.5530', '7.000', '1.5530']
VI_at__the_End : ['2.450', '2.0450', '1.850', '0.3258', '7.000', '1.5530', '7.000', '1.5530']
16:25:57:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1029/TestDate_2023_11_20-16_24_19/