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FEB_1029 20.11.23 15:04:59
TextEdit.txt
15:04:52:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
15:04:53:febtest:INFO: FEB8.2 selected
15:04:53:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:04:59:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:04:59:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
15:04:59:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:04:59:febtest:INFO: Tsting FEB with SN 1029
15:05:00:smx_tester:INFO: Scanning setup
15:05:00:elinks:INFO: Disabling clock on downlink 0
15:05:00:elinks:INFO: Disabling clock on downlink 1
15:05:00:elinks:INFO: Disabling clock on downlink 2
15:05:00:elinks:INFO: Disabling clock on downlink 3
15:05:00:elinks:INFO: Disabling clock on downlink 4
15:05:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:05:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:05:00:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:05:00:elinks:INFO: Disabling clock on downlink 0
15:05:00:elinks:INFO: Disabling clock on downlink 1
15:05:00:elinks:INFO: Disabling clock on downlink 2
15:05:00:elinks:INFO: Disabling clock on downlink 3
15:05:00:elinks:INFO: Disabling clock on downlink 4
15:05:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:05:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
15:05:00:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:05:00:elinks:INFO: Disabling clock on downlink 0
15:05:00:elinks:INFO: Disabling clock on downlink 1
15:05:00:elinks:INFO: Disabling clock on downlink 2
15:05:00:elinks:INFO: Disabling clock on downlink 3
15:05:00:elinks:INFO: Disabling clock on downlink 4
15:05:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:05:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:05:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
15:05:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
15:05:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:05:01:elinks:INFO: Disabling clock on downlink 0
15:05:01:elinks:INFO: Disabling clock on downlink 1
15:05:01:elinks:INFO: Disabling clock on downlink 2
15:05:01:elinks:INFO: Disabling clock on downlink 3
15:05:01:elinks:INFO: Disabling clock on downlink 4
15:05:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:05:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:05:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:05:01:elinks:INFO: Disabling clock on downlink 0
15:05:01:elinks:INFO: Disabling clock on downlink 1
15:05:01:elinks:INFO: Disabling clock on downlink 2
15:05:01:elinks:INFO: Disabling clock on downlink 3
15:05:01:elinks:INFO: Disabling clock on downlink 4
15:05:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:05:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:05:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:05:01:setup_element:INFO: Scanning clock phase
15:05:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:05:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:05:01:setup_element:INFO: Clock phase scan results for group 0, downlink 1
15:05:01:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:05:01:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
15:05:01:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:05:01:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
15:05:01:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:05:01:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:05:01:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:05:01:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:05:01:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:05:01:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:05:01:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:01:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:01:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:01:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:01:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:05:01:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:05:01:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
15:05:01:setup_element:INFO: Scanning clock phase
15:05:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:05:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:05:02:setup_element:INFO: Clock phase scan results for group 0, downlink 2
15:05:02:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:05:02:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
15:05:02:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 24: ________________________________________________________________________________
Clock Delay: 40
15:05:02:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________________________
Clock Delay: 40
15:05:02:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:05:02:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:05:02:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:05:02:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:05:02:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:05:02:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
15:05:02:setup_element:INFO: Scanning data phases
15:05:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:05:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:05:07:setup_element:INFO: Data phase scan results for group 0, downlink 1
15:05:07:setup_element:INFO: Eye window for uplink 0 : _______XXXXXX___________________________
Data delay found: 29
15:05:07:setup_element:INFO: Eye window for uplink 1 : ____XXXXXX______________________________
Data delay found: 26
15:05:07:setup_element:INFO: Eye window for uplink 2 : ____XXXXXX______________________________
Data delay found: 26
15:05:07:setup_element:INFO: Eye window for uplink 3 : __XXXXXX________________________________
Data delay found: 24
15:05:07:setup_element:INFO: Eye window for uplink 4 : _XXXXX_________________________________X
Data delay found: 22
15:05:07:setup_element:INFO: Eye window for uplink 5 : XX_________________________________XXXXX
Data delay found: 18
15:05:07:setup_element:INFO: Eye window for uplink 6 : X___________________________________XXXX
Data delay found: 18
15:05:07:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXX____
Data delay found: 13
15:05:07:setup_element:INFO: Eye window for uplink 8 : _____________________XXXXX______________
Data delay found: 3
15:05:07:setup_element:INFO: Eye window for uplink 9 : _________________________XXXXXX_________
Data delay found: 7
15:05:07:setup_element:INFO: Eye window for uplink 10: _______________________XXXXXX___________
Data delay found: 5
15:05:07:setup_element:INFO: Eye window for uplink 11: ___________________________XXXXX________
Data delay found: 9
15:05:07:setup_element:INFO: Eye window for uplink 12: _______________________XXXXXX___________
Data delay found: 5
15:05:07:setup_element:INFO: Eye window for uplink 13: ___________________________XXXXX________
Data delay found: 9
15:05:07:setup_element:INFO: Eye window for uplink 14: _________________________XXXX___________
Data delay found: 6
15:05:07:setup_element:INFO: Eye window for uplink 15: ____________________________XXXX________
Data delay found: 9
15:05:07:setup_element:INFO: Setting the data phase to 29 for uplink 0
15:05:07:setup_element:INFO: Setting the data phase to 26 for uplink 1
15:05:07:setup_element:INFO: Setting the data phase to 26 for uplink 2
15:05:07:setup_element:INFO: Setting the data phase to 24 for uplink 3
15:05:07:setup_element:INFO: Setting the data phase to 22 for uplink 4
15:05:07:setup_element:INFO: Setting the data phase to 18 for uplink 5
15:05:07:setup_element:INFO: Setting the data phase to 18 for uplink 6
15:05:07:setup_element:INFO: Setting the data phase to 13 for uplink 7
15:05:07:setup_element:INFO: Setting the data phase to 3 for uplink 8
15:05:07:setup_element:INFO: Setting the data phase to 7 for uplink 9
15:05:07:setup_element:INFO: Setting the data phase to 5 for uplink 10
15:05:07:setup_element:INFO: Setting the data phase to 9 for uplink 11
15:05:07:setup_element:INFO: Setting the data phase to 5 for uplink 12
15:05:07:setup_element:INFO: Setting the data phase to 9 for uplink 13
15:05:07:setup_element:INFO: Setting the data phase to 6 for uplink 14
15:05:07:setup_element:INFO: Setting the data phase to 9 for uplink 15
15:05:07:setup_element:INFO: Scanning data phases
15:05:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:05:07:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:05:13:setup_element:INFO: Data phase scan results for group 0, downlink 2
15:05:13:setup_element:INFO: Eye window for uplink 16: X__________________________________XXXXX
Data delay found: 17
15:05:13:setup_element:INFO: Eye window for uplink 17: ________________________________XXXXX___
Data delay found: 14
15:05:13:setup_element:INFO: Eye window for uplink 18: _______________________________XXXXXX___
Data delay found: 13
15:05:13:setup_element:INFO: Eye window for uplink 19: _____________________________XXXXXX_____
Data delay found: 11
15:05:13:setup_element:INFO: Eye window for uplink 20: _______________________________XXXXX____
Data delay found: 13
15:05:13:setup_element:INFO: Eye window for uplink 21: ______________________________XXXXXX____
Data delay found: 12
15:05:13:setup_element:INFO: Eye window for uplink 22: _______________________________XXXXX____
Data delay found: 13
15:05:13:setup_element:INFO: Eye window for uplink 23: ______________________________XXXX______
Data delay found: 11
15:05:13:setup_element:INFO: Eye window for uplink 24: __XXXX__________________________________
Data delay found: 23
15:05:13:setup_element:INFO: Eye window for uplink 25: _____XXXXX______________________________
Data delay found: 27
15:05:13:setup_element:INFO: Eye window for uplink 26: ___XXXXX________________________________
Data delay found: 25
15:05:13:setup_element:INFO: Eye window for uplink 27: ______XXXXXX____________________________
Data delay found: 28
15:05:13:setup_element:INFO: Eye window for uplink 28: __________XXXXX_________________________
Data delay found: 32
15:05:13:setup_element:INFO: Eye window for uplink 29: ____________XXXXX_______________________
Data delay found: 34
15:05:13:setup_element:INFO: Eye window for uplink 30: ___________XXXXXXX______________________
Data delay found: 34
15:05:13:setup_element:INFO: Eye window for uplink 31: __________XXXXXX________________________
Data delay found: 32
15:05:13:setup_element:INFO: Setting the data phase to 17 for uplink 16
15:05:13:setup_element:INFO: Setting the data phase to 14 for uplink 17
15:05:13:setup_element:INFO: Setting the data phase to 13 for uplink 18
15:05:13:setup_element:INFO: Setting the data phase to 11 for uplink 19
15:05:13:setup_element:INFO: Setting the data phase to 13 for uplink 20
15:05:13:setup_element:INFO: Setting the data phase to 12 for uplink 21
15:05:13:setup_element:INFO: Setting the data phase to 13 for uplink 22
15:05:13:setup_element:INFO: Setting the data phase to 11 for uplink 23
15:05:13:setup_element:INFO: Setting the data phase to 23 for uplink 24
15:05:13:setup_element:INFO: Setting the data phase to 27 for uplink 25
15:05:13:setup_element:INFO: Setting the data phase to 25 for uplink 26
15:05:13:setup_element:INFO: Setting the data phase to 28 for uplink 27
15:05:13:setup_element:INFO: Setting the data phase to 32 for uplink 28
15:05:13:setup_element:INFO: Setting the data phase to 34 for uplink 29
15:05:13:setup_element:INFO: Setting the data phase to 34 for uplink 30
15:05:13:setup_element:INFO: Setting the data phase to 32 for uplink 31
15:05:13:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 1:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 2:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 4:
Optimal Phase: 22
Window Length: 33
Eye Window: _XXXXX_________________________________X
Uplink 5:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 6:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 10:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 11:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 12:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 13:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 14:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
,
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXX_
Uplink 17: ________________________________________________________________________XXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXX___
Uplink 21: ______________________________________________________________________XXXXXXX___
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ________________________________________________________________________________
Uplink 25: ________________________________________________________________________________
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 19:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 20:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 21:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 22:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 25:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 34
Window Length: 33
Eye Window: ___________XXXXXXX______________________
Uplink 31:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
]
15:05:13:setup_element:INFO: Beginning SMX ASICs map scan
15:05:13:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:05:13:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:05:13:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:05:13:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:05:13:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:05:13:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
15:05:13:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
15:05:13:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
15:05:13:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
15:05:14:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
15:05:14:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
15:05:14:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
15:05:14:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
15:05:14:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
15:05:14:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
15:05:14:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
15:05:14:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
15:05:14:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
15:05:14:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
15:05:14:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
15:05:14:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
15:05:16:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 1:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 2:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 4:
Optimal Phase: 22
Window Length: 33
Eye Window: _XXXXX_________________________________X
Uplink 5:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 6:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 10:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 11:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 12:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 13:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 14:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 15:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
15:05:16:setup_element:INFO: Beginning SMX ASICs map scan
15:05:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:05:16:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:05:16:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:05:16:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:05:16:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:05:16:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:05:16:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:05:16:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:05:16:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:05:16:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:05:16:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:05:16:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:05:16:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:05:17:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:05:17:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:05:17:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:05:17:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:05:17:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:05:17:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:05:17:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:05:17:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:05:18:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: ________________________________________________________________________XXXXXXX_
Uplink 17: ________________________________________________________________________XXXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXX___
Uplink 21: ______________________________________________________________________XXXXXXX___
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ________________________________________________________________________________
Uplink 25: ________________________________________________________________________________
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXX__
Uplink 31: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 19:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 20:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 21:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 22:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 25:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 34
Window Length: 33
Eye Window: ___________XXXXXXX______________________
Uplink 31:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
15:05:18:setup_element:INFO: Performing Elink synchronization
15:05:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:05:18:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:05:19:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:05:19:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:05:19:setup_element:INFO: Performing Elink synchronization
15:05:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:05:19:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:05:19:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
15:05:19:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
15:05:19:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
15:05:19:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:05:19:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
15:05:19:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:05:19:ST3_emu:INFO: Number of chips: 16
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
15:05:21:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:05:21:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:05:21:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
15:05:21:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 56.8 | 1147.8
15:05:22:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1183.3
15:05:22:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
15:05:22:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
15:05:22:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 53.6 | 1165.6
15:05:22:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
15:05:23:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 50.4 | 1159.7
15:05:23:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 53.6 | 1159.7
15:05:23:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
15:05:23:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1165.6
15:05:23:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
15:05:24:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 53.6 | 1165.6
15:05:24:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
15:05:24:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 69.6 | 1100.2
15:05:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:05:28:ST3_smx:INFO: chip: 0-0 50.430383 C 1153.732915 mV
15:05:28:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:05:28:ST3_smx:INFO: Electrons
15:05:28:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:05:30:ST3_smx:INFO: ----> Checking Analog response
15:05:30:ST3_smx:INFO: ----> Checking broken channels
15:05:30:ST3_smx:INFO: Total # broken ch: 1
15:05:30:ST3_smx:INFO: List FAST: [88]
15:05:30:ST3_smx:INFO: List SLOW: []
15:05:30:ST3_smx:INFO: Holes
15:05:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:05:32:ST3_smx:INFO: ----> Checking Analog response
15:05:32:ST3_smx:INFO: ----> Checking broken channels
15:05:33:ST3_smx:INFO: Total # broken ch: 1
15:05:33:ST3_smx:INFO: List FAST: [88]
15:05:33:ST3_smx:INFO: List SLOW: []
15:05:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:05:33:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:05:33:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1195.1
15:05:33:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 56.8 | 1147.8
15:05:34:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1183.3
15:05:34:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
15:05:34:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
15:05:34:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
15:05:34:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
15:05:35:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 50.4 | 1165.6
15:05:35:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1159.7
15:05:35:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
15:05:35:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1171.5
15:05:35:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
15:05:36:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 53.6 | 1165.6
15:05:36:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
15:05:36:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
15:05:36:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:05:40:ST3_smx:INFO: chip: 0-5 59.984250 C 1135.937260 mV
15:05:40:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:05:40:ST3_smx:INFO: Electrons
15:05:40:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:05:42:ST3_smx:INFO: ----> Checking Analog response
15:05:42:ST3_smx:INFO: ----> Checking broken channels
15:05:42:ST3_smx:INFO: Total # broken ch: 2
15:05:42:ST3_smx:INFO: List FAST: [27, 54]
15:05:42:ST3_smx:INFO: List SLOW: []
15:05:42:ST3_smx:INFO: Holes
15:05:42:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:05:44:ST3_smx:INFO: ----> Checking Analog response
15:05:44:ST3_smx:INFO: ----> Checking broken channels
15:05:45:ST3_smx:INFO: Total # broken ch: 2
15:05:45:ST3_smx:INFO: List FAST: [27, 54]
15:05:45:ST3_smx:INFO: List SLOW: []
15:05:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:05:45:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:05:45:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
15:05:45:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1141.9
15:05:46:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1177.4
15:05:46:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
15:05:46:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1130.0
15:05:46:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 53.6 | 1165.6
15:05:46:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
15:05:47:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 50.4 | 1159.7
15:05:47:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1159.7
15:05:47:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
15:05:47:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1165.6
15:05:48:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
15:05:48:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 53.6 | 1165.6
15:05:48:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
15:05:48:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
15:05:48:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:05:52:ST3_smx:INFO: chip: 0-7 56.797143 C 1159.654860 mV
15:05:52:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:05:52:ST3_smx:INFO: Electrons
15:05:52:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:05:54:ST3_smx:INFO: ----> Checking Analog response
15:05:54:ST3_smx:INFO: ----> Checking broken channels
15:05:54:ST3_smx:INFO: Total # broken ch: 5
15:05:54:ST3_smx:INFO: List FAST: [6, 66, 101, 115, 117]
15:05:54:ST3_smx:INFO: List SLOW: []
15:05:54:ST3_smx:INFO: Holes
15:05:54:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:05:56:ST3_smx:INFO: ----> Checking Analog response
15:05:56:ST3_smx:INFO: ----> Checking broken channels
15:05:57:ST3_smx:INFO: Total # broken ch: 5
15:05:57:ST3_smx:INFO: List FAST: [6, 66, 101, 115, 117]
15:05:57:ST3_smx:INFO: List SLOW: []
15:05:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:05:57:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:05:57:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
15:05:57:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1141.9
15:05:58:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1177.4
15:05:58:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
15:05:58:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1130.0
15:05:58:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
15:05:58:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 56.8 | 1153.7
15:05:59:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
15:05:59:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1159.7
15:05:59:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
15:05:59:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1165.6
15:05:59:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
15:06:00:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
15:06:00:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
15:06:00:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
15:06:00:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:06:04:ST3_smx:INFO: chip: 0-0 56.797143 C 1135.937260 mV
15:06:04:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:06:04:ST3_smx:INFO: Electrons
15:06:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:06:06:ST3_smx:INFO: ----> Checking Analog response
15:06:06:ST3_smx:INFO: ----> Checking broken channels
15:06:06:ST3_smx:INFO: Total # broken ch: 3
15:06:06:ST3_smx:INFO: List FAST: [17, 27, 122]
15:06:06:ST3_smx:INFO: List SLOW: []
15:06:06:ST3_smx:INFO: Holes
15:06:06:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:06:08:ST3_smx:INFO: ----> Checking Analog response
15:06:08:ST3_smx:INFO: ----> Checking broken channels
15:06:09:ST3_smx:INFO: Total # broken ch: 3
15:06:09:ST3_smx:INFO: List FAST: [17, 27, 122]
15:06:09:ST3_smx:INFO: List SLOW: []
15:06:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:06:09:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:06:09:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
15:06:09:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1141.9
15:06:09:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1177.4
15:06:10:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 60.0 | 1147.8
15:06:10:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1130.0
15:06:10:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1159.7
15:06:10:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 56.8 | 1153.7
15:06:11:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1130.0
15:06:11:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1153.7
15:06:11:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1130.0
15:06:11:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1165.6
15:06:11:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1177.4
15:06:12:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
15:06:12:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
15:06:12:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
15:06:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:06:16:ST3_smx:INFO: chip: 0-5 56.797143 C 1147.806000 mV
15:06:16:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:06:16:ST3_smx:INFO: Electrons
15:06:16:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:06:18:ST3_smx:INFO: ----> Checking Analog response
15:06:18:ST3_smx:INFO: ----> Checking broken channels
15:06:18:ST3_smx:INFO: Total # broken ch: 1
15:06:18:ST3_smx:INFO: List FAST: [31]
15:06:18:ST3_smx:INFO: List SLOW: []
15:06:18:ST3_smx:INFO: Holes
15:06:18:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:06:20:ST3_smx:INFO: ----> Checking Analog response
15:06:20:ST3_smx:INFO: ----> Checking broken channels
15:06:21:ST3_smx:INFO: Total # broken ch: 1
15:06:21:ST3_smx:INFO: List FAST: [31]
15:06:21:ST3_smx:INFO: List SLOW: []
15:06:21:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:06:21:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:06:21:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 50.4 | 1189.2
15:06:21:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1141.9
15:06:21:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 53.6 | 1177.4
15:06:22:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 60.0 | 1147.8
15:06:22:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1130.0
15:06:22:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
15:06:22:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1153.7
15:06:23:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1130.0
15:06:23:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1153.7
15:06:23:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1130.0
15:06:23:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1165.6
15:06:23:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1177.4
15:06:24:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1147.8
15:06:24:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1171.5
15:06:24:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1094.2
15:06:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
15:06:28:ST3_smx:INFO: chip: 0-7 69.560482 C 1100.211760 mV
15:06:28:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
15:06:28:ST3_smx:INFO: Electrons
15:06:28:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:06:30:ST3_smx:INFO: ----> Checking Analog response
15:06:30:ST3_smx:INFO: ----> Checking broken channels
15:06:30:ST3_smx:INFO: Total # broken ch: 2
15:06:30:ST3_smx:INFO: List FAST: [27, 67]
15:06:30:ST3_smx:INFO: List SLOW: []
15:06:30:ST3_smx:INFO: Holes
15:06:30:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
15:06:32:ST3_smx:INFO: ----> Checking Analog response
15:06:32:ST3_smx:INFO: ----> Checking broken channels
15:06:33:ST3_smx:INFO: Total # broken ch: 2
15:06:33:ST3_smx:INFO: List FAST: [27, 67]
15:06:33:ST3_smx:INFO: List SLOW: []
15:06:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:06:33:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
15:06:33:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 50.4 | 1183.3
15:06:33:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1141.9
15:06:34:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1177.4
15:06:34:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 60.0 | 1147.8
15:06:34:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1130.0
15:06:34:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1159.7
15:06:35:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1153.7
15:06:35:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1130.0
15:06:35:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1147.8
15:06:35:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1130.0
15:06:35:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 56.8 | 1165.6
15:06:36:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1177.4
15:06:36:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1141.9
15:06:36:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1171.5
15:06:36:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1094.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-15_04_59', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-001-016-04', 'FUSED_ID': 6359364699116540164, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 2, 'N_BROKEN_FAST': '[27, 67]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 2, 'P_BROKEN_FAST': '[27, 67]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.445', '3.8340', '1.842', '4.9260', '7.000', '1.5690', '7.000', '1.5690'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': '33 FAST ', 'P_ANA_FAIL_CH': '1'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 1, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 1, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-15_04_59
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.445', '3.8340', '1.842', '4.9260', '7.000', '1.5690', '7.000', '1.5690']
VI_after__Init : ['2.450', '3.8120', '1.850', '1.7620', '7.000', '1.5610', '7.000', '1.5610']
VI_at__the_End : ['2.450', '3.8120', '1.850', '1.7620', '7.000', '1.5610', '7.000', '1.5610']
15:07:07:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1029/TestDate_2023_11_20-15_04_59/