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FEB_1029 20.11.23 16:13:40
Info
16:13:14:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
16:13:14:febtest:INFO: FEB8.2 selected
16:13:14:smx_tester:INFO: Setting Elink clock mode to 160 MHz
16:13:37:febtest:INFO: FEB 8-2 A @ GSI
16:13:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:13:40:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
16:13:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
16:13:40:febtest:INFO: Tsting FEB with SN 1029
16:13:41:smx_tester:INFO: Scanning setup
16:13:41:elinks:INFO: Disabling clock on downlink 0
16:13:41:elinks:INFO: Disabling clock on downlink 1
16:13:41:elinks:INFO: Disabling clock on downlink 2
16:13:41:elinks:INFO: Disabling clock on downlink 3
16:13:41:elinks:INFO: Disabling clock on downlink 4
16:13:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:13:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
16:13:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:13:41:elinks:INFO: Disabling clock on downlink 0
16:13:41:elinks:INFO: Disabling clock on downlink 1
16:13:41:elinks:INFO: Disabling clock on downlink 2
16:13:41:elinks:INFO: Disabling clock on downlink 3
16:13:41:elinks:INFO: Disabling clock on downlink 4
16:13:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:13:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
16:13:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
16:13:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:13:41:elinks:INFO: Disabling clock on downlink 0
16:13:41:elinks:INFO: Disabling clock on downlink 1
16:13:41:elinks:INFO: Disabling clock on downlink 2
16:13:41:elinks:INFO: Disabling clock on downlink 3
16:13:41:elinks:INFO: Disabling clock on downlink 4
16:13:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:13:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
16:13:42:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
16:13:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:13:42:elinks:INFO: Disabling clock on downlink 0
16:13:42:elinks:INFO: Disabling clock on downlink 1
16:13:42:elinks:INFO: Disabling clock on downlink 2
16:13:42:elinks:INFO: Disabling clock on downlink 3
16:13:42:elinks:INFO: Disabling clock on downlink 4
16:13:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:13:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
16:13:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:13:42:elinks:INFO: Disabling clock on downlink 0
16:13:42:elinks:INFO: Disabling clock on downlink 1
16:13:42:elinks:INFO: Disabling clock on downlink 2
16:13:42:elinks:INFO: Disabling clock on downlink 3
16:13:42:elinks:INFO: Disabling clock on downlink 4
16:13:42:setup_element:INFO: Checking SOS, encoding_mode: SOS
16:13:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
16:13:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
16:13:42:setup_element:INFO: Scanning clock phase
16:13:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:13:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:13:42:setup_element:INFO: Clock phase scan results for group 0, downlink 1
16:13:42:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
16:13:42:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
16:13:42:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
16:13:42:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
16:13:42:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:13:42:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:13:42:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:13:42:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
16:13:42:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:13:42:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
16:13:42:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:42:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:42:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:42:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:42:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:13:42:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:13:42:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
16:13:42:setup_element:INFO: Scanning clock phase
16:13:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:13:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:13:43:setup_element:INFO: Clock phase scan results for group 0, downlink 2
16:13:43:setup_element:INFO: Eye window for uplink 16: _________________________________________________________________________XXXXXX_
Clock Delay: 35
16:13:43:setup_element:INFO: Eye window for uplink 17: _________________________________________________________________________XXXXXX_
Clock Delay: 35
16:13:43:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 22: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 23: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 25: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
16:13:43:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:13:43:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
16:13:43:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:13:43:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
16:13:43:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
16:13:43:setup_element:INFO: Scanning data phases
16:13:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:13:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:13:48:setup_element:INFO: Data phase scan results for group 0, downlink 1
16:13:48:setup_element:INFO: Eye window for uplink 0 : _______XXXXXXX__________________________
Data delay found: 30
16:13:48:setup_element:INFO: Eye window for uplink 1 : ____XXXXXX______________________________
Data delay found: 26
16:13:48:setup_element:INFO: Eye window for uplink 2 : ______XXXXX_____________________________
Data delay found: 28
16:13:48:setup_element:INFO: Eye window for uplink 3 : __XXXXXXX_______________________________
Data delay found: 25
16:13:48:setup_element:INFO: Eye window for uplink 4 : XXXXXX__________________________________
Data delay found: 22
16:13:48:setup_element:INFO: Eye window for uplink 5 : X__________________________________XXXXX
Data delay found: 17
16:13:48:setup_element:INFO: Eye window for uplink 6 : X____________________________________XXX
Data delay found: 18
16:13:48:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXXX___
Data delay found: 14
16:13:48:setup_element:INFO: Eye window for uplink 8 : _____________________XXXXX______________
Data delay found: 3
16:13:48:setup_element:INFO: Eye window for uplink 9 : _________________________XXXXXX_________
Data delay found: 7
16:13:48:setup_element:INFO: Eye window for uplink 10: _______________________XXXXXX___________
Data delay found: 5
16:13:48:setup_element:INFO: Eye window for uplink 11: ___________________________XXXXXX_______
Data delay found: 9
16:13:48:setup_element:INFO: Eye window for uplink 12: ________________________XXXXX___________
Data delay found: 6
16:13:48:setup_element:INFO: Eye window for uplink 13: ___________________________XXXXX________
Data delay found: 9
16:13:48:setup_element:INFO: Eye window for uplink 14: _________________________XXXXX__________
Data delay found: 7
16:13:48:setup_element:INFO: Eye window for uplink 15: ____________________________XXXXX_______
Data delay found: 10
16:13:48:setup_element:INFO: Setting the data phase to 30 for uplink 0
16:13:48:setup_element:INFO: Setting the data phase to 26 for uplink 1
16:13:48:setup_element:INFO: Setting the data phase to 28 for uplink 2
16:13:48:setup_element:INFO: Setting the data phase to 25 for uplink 3
16:13:48:setup_element:INFO: Setting the data phase to 22 for uplink 4
16:13:48:setup_element:INFO: Setting the data phase to 17 for uplink 5
16:13:48:setup_element:INFO: Setting the data phase to 18 for uplink 6
16:13:48:setup_element:INFO: Setting the data phase to 14 for uplink 7
16:13:48:setup_element:INFO: Setting the data phase to 3 for uplink 8
16:13:48:setup_element:INFO: Setting the data phase to 7 for uplink 9
16:13:48:setup_element:INFO: Setting the data phase to 5 for uplink 10
16:13:48:setup_element:INFO: Setting the data phase to 9 for uplink 11
16:13:48:setup_element:INFO: Setting the data phase to 6 for uplink 12
16:13:48:setup_element:INFO: Setting the data phase to 9 for uplink 13
16:13:48:setup_element:INFO: Setting the data phase to 7 for uplink 14
16:13:48:setup_element:INFO: Setting the data phase to 10 for uplink 15
16:13:48:setup_element:INFO: Scanning data phases
16:13:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:13:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:13:54:setup_element:INFO: Data phase scan results for group 0, downlink 2
16:13:54:setup_element:INFO: Eye window for uplink 16: XX_________________________________XXXXX
Data delay found: 18
16:13:54:setup_element:INFO: Eye window for uplink 17: ________________________________XXXXX___
Data delay found: 14
16:13:54:setup_element:INFO: Eye window for uplink 18: _______________________________XXXXXX___
Data delay found: 13
16:13:54:setup_element:INFO: Eye window for uplink 19: _____________________________XXXXXX_____
Data delay found: 11
16:13:54:setup_element:INFO: Eye window for uplink 20: ________________________________XXXX____
Data delay found: 13
16:13:54:setup_element:INFO: Eye window for uplink 21: ______________________________XXXXXX____
Data delay found: 12
16:13:54:setup_element:INFO: Eye window for uplink 22: ________________________________XXXX____
Data delay found: 13
16:13:54:setup_element:INFO: Eye window for uplink 23: ______________________________XXXX______
Data delay found: 11
16:13:54:setup_element:INFO: Eye window for uplink 24: __XXXXX_______________XXXXXXXXXXXXXXXXXX
Data delay found: 14
16:13:54:setup_element:INFO: Eye window for uplink 25: _____XXXX_____________XXXXXXXXXXXXXXXXXX
Data delay found: 15
16:13:54:setup_element:INFO: Eye window for uplink 26: ___XXXXX________________________________
Data delay found: 25
16:13:54:setup_element:INFO: Eye window for uplink 27: _______XXXXX____________________________
Data delay found: 29
16:13:54:setup_element:INFO: Eye window for uplink 28: __________XXXXX_________________________
Data delay found: 32
16:13:54:setup_element:INFO: Eye window for uplink 29: ___________XXXXXX_______________________
Data delay found: 33
16:13:54:setup_element:INFO: Eye window for uplink 30: ____________XXXXX_______________________
Data delay found: 34
16:13:54:setup_element:INFO: Eye window for uplink 31: __________XXXXXX________________________
Data delay found: 32
16:13:54:setup_element:INFO: Setting the data phase to 18 for uplink 16
16:13:54:setup_element:INFO: Setting the data phase to 14 for uplink 17
16:13:54:setup_element:INFO: Setting the data phase to 13 for uplink 18
16:13:54:setup_element:INFO: Setting the data phase to 11 for uplink 19
16:13:54:setup_element:INFO: Setting the data phase to 13 for uplink 20
16:13:54:setup_element:INFO: Setting the data phase to 12 for uplink 21
16:13:54:setup_element:INFO: Setting the data phase to 13 for uplink 22
16:13:54:setup_element:INFO: Setting the data phase to 11 for uplink 23
16:13:54:setup_element:INFO: Setting the data phase to 14 for uplink 24
16:13:54:setup_element:INFO: Setting the data phase to 15 for uplink 25
16:13:54:setup_element:INFO: Setting the data phase to 25 for uplink 26
16:13:54:setup_element:INFO: Setting the data phase to 29 for uplink 27
16:13:54:setup_element:INFO: Setting the data phase to 32 for uplink 28
16:13:54:setup_element:INFO: Setting the data phase to 33 for uplink 29
16:13:54:setup_element:INFO: Setting the data phase to 34 for uplink 30
16:13:54:setup_element:INFO: Setting the data phase to 32 for uplink 31
16:13:54:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 1:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 2:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 33
Eye Window: __XXXXXXX_______________________________
Uplink 4:
Optimal Phase: 22
Window Length: 34
Eye Window: XXXXXX__________________________________
Uplink 5:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 6:
Optimal Phase: 18
Window Length: 36
Eye Window: X____________________________________XXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 10:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 11:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 12:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 13:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 14:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 15:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
,
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: _________________________________________________________________________XXXXXX_
Uplink 17: _________________________________________________________________________XXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXXX__
Uplink 21: ______________________________________________________________________XXXXXXXX__
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXXX__
Uplink 25: ______________________________________________________________________XXXXXXXX__
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 19:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 20:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 21:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 22:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 14
Window Length: 15
Eye Window: __XXXXX_______________XXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 15
Window Length: 13
Eye Window: _____XXXX_____________XXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 30:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 31:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
]
16:13:54:setup_element:INFO: Beginning SMX ASICs map scan
16:13:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:13:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:13:54:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:13:54:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:13:54:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:13:54:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
16:13:54:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
16:13:54:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
16:13:54:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
16:13:55:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
16:13:55:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
16:13:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
16:13:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
16:13:55:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
16:13:55:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
16:13:55:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
16:13:55:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
16:13:55:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
16:13:55:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
16:13:56:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
16:13:56:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
16:13:57:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXX___
Uplink 9: ______________________________________________________________________XXXXXXX___
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 1:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 2:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 33
Eye Window: __XXXXXXX_______________________________
Uplink 4:
Optimal Phase: 22
Window Length: 34
Eye Window: XXXXXX__________________________________
Uplink 5:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 6:
Optimal Phase: 18
Window Length: 36
Eye Window: X____________________________________XXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 3
Window Length: 35
Eye Window: _____________________XXXXX______________
Uplink 9:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 10:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 11:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 12:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 13:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 14:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 15:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
16:13:57:setup_element:INFO: Beginning SMX ASICs map scan
16:13:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:13:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:13:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:13:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:13:57:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
16:13:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
16:13:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
16:13:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
16:13:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
16:13:57:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
16:13:57:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
16:13:57:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
16:13:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
16:13:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
16:13:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
16:13:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
16:13:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
16:13:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
16:13:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
16:13:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
16:13:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
16:13:59:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 16: _________________________________________________________________________XXXXXX_
Uplink 17: _________________________________________________________________________XXXXXX_
Uplink 18: ______________________________________________________________________XXXXXXXX__
Uplink 19: ______________________________________________________________________XXXXXXXX__
Uplink 20: ______________________________________________________________________XXXXXXXX__
Uplink 21: ______________________________________________________________________XXXXXXXX__
Uplink 22: ______________________________________________________________________XXXXXXXX__
Uplink 23: ______________________________________________________________________XXXXXXXX__
Uplink 24: ______________________________________________________________________XXXXXXXX__
Uplink 25: ______________________________________________________________________XXXXXXXX__
Uplink 26: ______________________________________________________________________XXXXXXXX__
Uplink 27: ______________________________________________________________________XXXXXXXX__
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _______________________________________________________________________XXXXXXXX_
Uplink 31: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 17:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 18:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 19:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 20:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 21:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 22:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 14
Window Length: 15
Eye Window: __XXXXX_______________XXXXXXXXXXXXXXXXXX
Uplink 25:
Optimal Phase: 15
Window Length: 13
Eye Window: _____XXXX_____________XXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 30:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 31:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
16:13:59:setup_element:INFO: Performing Elink synchronization
16:14:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
16:14:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
16:14:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
16:14:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
16:14:00:setup_element:INFO: Performing Elink synchronization
16:14:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
16:14:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
16:14:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
16:14:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
16:14:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
16:14:00:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
16:14:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
16:14:00:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
16:14:00:ST3_emu:INFO: Number of chips: 16
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
16:14:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:14:02:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1147.8
16:14:02:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1189.2
16:14:02:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1135.9
16:14:03:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1177.4
16:14:03:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 53.6 | 1147.8
16:14:03:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 60.0 | 1141.9
16:14:03:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 53.6 | 1165.6
16:14:03:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 37.7 | 1230.3
16:14:04:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 50.4 | 1159.7
16:14:04:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 53.6 | 1159.7
16:14:04:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
16:14:04:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 50.4 | 1177.4
16:14:04:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
16:14:05:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 53.6 | 1171.5
16:14:05:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 47.3 | 1177.4
16:14:05:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 69.6 | 1100.2
16:14:05:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:14:09:ST3_smx:INFO: chip: 0-0 50.430383 C 1165.571835 mV
16:14:09:ST3_smx:INFO: Electrons
16:14:09:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:11:ST3_smx:INFO: ----> Checking Analog response
16:14:11:ST3_smx:INFO: ----> Checking broken channels
16:14:12:ST3_smx:INFO: Total # broken ch: 2
16:14:12:ST3_smx:INFO: List FAST: [28, 53]
16:14:12:ST3_smx:INFO: List SLOW: []
16:14:12:ST3_smx:INFO: Holes
16:14:12:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:14:ST3_smx:INFO: ----> Checking Analog response
16:14:14:ST3_smx:INFO: ----> Checking broken channels
16:14:14:ST3_smx:INFO: Total # broken ch: 2
16:14:14:ST3_smx:INFO: List FAST: [28, 53]
16:14:14:ST3_smx:INFO: List SLOW: []
16:14:14:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:14:14:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:14:14:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 47.3 | 1183.3
16:14:15:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1135.9
16:14:15:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 47.3 | 1177.4
16:14:15:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
16:14:15:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 60.0 | 1141.9
16:14:16:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 53.6 | 1165.6
16:14:16:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 37.7 | 1224.5
16:14:16:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 50.4 | 1159.7
16:14:16:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1159.7
16:14:17:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
16:14:17:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 50.4 | 1177.4
16:14:17:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
16:14:17:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 53.6 | 1171.5
16:14:17:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 47.3 | 1177.4
16:14:18:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 69.6 | 1100.2
16:14:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:14:22:ST3_smx:INFO: chip: 0-1 50.430383 C 1177.390875 mV
16:14:22:ST3_smx:INFO: Electrons
16:14:22:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:24:ST3_smx:INFO: ----> Checking Analog response
16:14:24:ST3_smx:INFO: ----> Checking broken channels
16:14:24:ST3_smx:INFO: Total # broken ch: 0
16:14:24:ST3_smx:INFO: List FAST: []
16:14:24:ST3_smx:INFO: List SLOW: []
16:14:24:ST3_smx:INFO: Holes
16:14:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:26:ST3_smx:INFO: ----> Checking Analog response
16:14:26:ST3_smx:INFO: ----> Checking broken channels
16:14:26:ST3_smx:INFO: Total # broken ch: 0
16:14:26:ST3_smx:INFO: List FAST: []
16:14:26:ST3_smx:INFO: List SLOW: []
16:14:26:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:14:26:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:14:27:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:14:27:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 60.0 | 1135.9
16:14:27:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1183.3
16:14:27:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
16:14:28:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:14:28:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 53.6 | 1165.6
16:14:28:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 37.7 | 1230.3
16:14:28:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 50.4 | 1159.7
16:14:29:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1153.7
16:14:29:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
16:14:29:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 50.4 | 1177.4
16:14:29:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
16:14:30:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 53.6 | 1165.6
16:14:30:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 47.3 | 1177.4
16:14:30:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 69.6 | 1100.2
16:14:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:14:34:ST3_smx:INFO: chip: 0-2 63.173842 C 1135.937260 mV
16:14:34:ST3_smx:INFO: Electrons
16:14:34:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:36:ST3_smx:INFO: ----> Checking Analog response
16:14:36:ST3_smx:INFO: ----> Checking broken channels
16:14:36:ST3_smx:INFO: Total # broken ch: 2
16:14:36:ST3_smx:INFO: List FAST: [25, 71]
16:14:36:ST3_smx:INFO: List SLOW: []
16:14:36:ST3_smx:INFO: Holes
16:14:36:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:38:ST3_smx:INFO: ----> Checking Analog response
16:14:38:ST3_smx:INFO: ----> Checking broken channels
16:14:38:ST3_smx:INFO: Total # broken ch: 2
16:14:38:ST3_smx:INFO: List FAST: [25, 71]
16:14:38:ST3_smx:INFO: List SLOW: []
16:14:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:14:39:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:14:39:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:14:39:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1130.0
16:14:39:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 50.4 | 1183.3
16:14:40:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1153.7
16:14:40:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:14:40:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:14:40:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1230.3
16:14:41:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
16:14:41:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1153.7
16:14:41:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 60.0 | 1135.9
16:14:41:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 50.4 | 1177.4
16:14:42:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
16:14:42:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:14:42:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:14:42:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 69.6 | 1100.2
16:14:43:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:14:46:ST3_smx:INFO: chip: 0-3 56.797143 C 1159.654860 mV
16:14:46:ST3_smx:INFO: Electrons
16:14:46:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:48:ST3_smx:INFO: ----> Checking Analog response
16:14:48:ST3_smx:INFO: ----> Checking broken channels
16:14:48:ST3_smx:INFO: Total # broken ch: 5
16:14:48:ST3_smx:INFO: List FAST: [4, 25, 52, 84, 99]
16:14:48:ST3_smx:INFO: List SLOW: []
16:14:48:ST3_smx:INFO: Holes
16:14:48:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:14:50:ST3_smx:INFO: ----> Checking Analog response
16:14:50:ST3_smx:INFO: ----> Checking broken channels
16:14:51:ST3_smx:INFO: Total # broken ch: 5
16:14:51:ST3_smx:INFO: List FAST: [4, 25, 52, 84, 99]
16:14:51:ST3_smx:INFO: List SLOW: []
16:14:51:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:14:51:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:14:51:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:14:51:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1130.0
16:14:52:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:14:52:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 56.8 | 1147.8
16:14:52:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:14:52:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:14:53:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:14:53:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
16:14:53:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 56.8 | 1153.7
16:14:53:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
16:14:54:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 50.4 | 1177.4
16:14:54:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
16:14:54:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:14:54:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1183.3
16:14:55:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:14:55:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:14:58:ST3_smx:INFO: chip: 0-4 63.173842 C 1129.995435 mV
16:14:58:ST3_smx:INFO: Electrons
16:14:58:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:00:ST3_smx:INFO: ----> Checking Analog response
16:15:00:ST3_smx:INFO: ----> Checking broken channels
16:15:01:ST3_smx:INFO: Total # broken ch: 2
16:15:01:ST3_smx:INFO: List FAST: [60, 66]
16:15:01:ST3_smx:INFO: List SLOW: []
16:15:01:ST3_smx:INFO: Holes
16:15:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:02:ST3_smx:INFO: ----> Checking Analog response
16:15:02:ST3_smx:INFO: ----> Checking broken channels
16:15:03:ST3_smx:INFO: Total # broken ch: 2
16:15:03:ST3_smx:INFO: List FAST: [60, 66]
16:15:03:ST3_smx:INFO: List SLOW: []
16:15:03:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:15:03:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:15:03:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:15:03:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1130.0
16:15:04:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:15:04:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:15:04:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1141.9
16:15:04:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:15:05:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1230.3
16:15:05:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
16:15:05:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:15:05:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
16:15:06:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:15:06:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 47.3 | 1183.3
16:15:06:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:15:06:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:15:07:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:15:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:15:11:ST3_smx:INFO: chip: 0-5 63.173842 C 1147.806000 mV
16:15:11:ST3_smx:INFO: Electrons
16:15:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:13:ST3_smx:INFO: ----> Checking Analog response
16:15:13:ST3_smx:INFO: ----> Checking broken channels
16:15:13:ST3_smx:INFO: Total # broken ch: 4
16:15:13:ST3_smx:INFO: List FAST: [36, 37, 102, 109]
16:15:13:ST3_smx:INFO: List SLOW: []
16:15:13:ST3_smx:INFO: Holes
16:15:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:15:ST3_smx:INFO: ----> Checking Analog response
16:15:15:ST3_smx:INFO: ----> Checking broken channels
16:15:16:ST3_smx:INFO: Total # broken ch: 4
16:15:16:ST3_smx:INFO: List FAST: [36, 37, 102, 109]
16:15:16:ST3_smx:INFO: List SLOW: []
16:15:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:15:16:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:15:16:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:15:16:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1130.0
16:15:17:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:15:17:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:15:17:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1147.8
16:15:17:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 56.8 | 1165.6
16:15:18:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1230.3
16:15:18:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
16:15:18:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:15:18:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
16:15:19:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:15:19:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:15:19:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:15:19:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:15:19:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:15:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:15:23:ST3_smx:INFO: chip: 0-6 66.365920 C 1135.937260 mV
16:15:23:ST3_smx:INFO: Electrons
16:15:23:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:25:ST3_smx:INFO: ----> Checking Analog response
16:15:25:ST3_smx:INFO: ----> Checking broken channels
16:15:25:ST3_smx:INFO: Total # broken ch: 0
16:15:25:ST3_smx:INFO: List FAST: []
16:15:25:ST3_smx:INFO: List SLOW: []
16:15:25:ST3_smx:INFO: Holes
16:15:25:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:27:ST3_smx:INFO: ----> Checking Analog response
16:15:27:ST3_smx:INFO: ----> Checking broken channels
16:15:28:ST3_smx:INFO: Total # broken ch: 0
16:15:28:ST3_smx:INFO: List FAST: []
16:15:28:ST3_smx:INFO: List SLOW: []
16:15:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:15:28:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:15:28:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 53.6 | 1171.5
16:15:28:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 63.2 | 1130.0
16:15:29:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:15:29:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1130.0
16:15:29:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1147.8
16:15:29:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:15:30:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 40.9 | 1224.5
16:15:30:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
16:15:30:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:15:30:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
16:15:31:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:15:31:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:15:31:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:15:31:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:15:32:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:15:32:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:15:35:ST3_smx:INFO: chip: 0-7 56.797143 C 1171.483840 mV
16:15:35:ST3_smx:INFO: Electrons
16:15:35:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:38:ST3_smx:INFO: ----> Checking Analog response
16:15:38:ST3_smx:INFO: ----> Checking broken channels
16:15:38:ST3_smx:INFO: Total # broken ch: 1
16:15:38:ST3_smx:INFO: List FAST: [96]
16:15:38:ST3_smx:INFO: List SLOW: []
16:15:38:ST3_smx:INFO: Holes
16:15:38:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:40:ST3_smx:INFO: ----> Checking Analog response
16:15:40:ST3_smx:INFO: ----> Checking broken channels
16:15:40:ST3_smx:INFO: Total # broken ch: 1
16:15:40:ST3_smx:INFO: List FAST: [96]
16:15:40:ST3_smx:INFO: List SLOW: []
16:15:40:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:15:40:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 53.6 | 1159.7
16:15:41:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:15:41:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:15:41:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:15:41:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:15:41:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1147.8
16:15:42:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:15:42:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1171.5
16:15:42:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 53.6 | 1159.7
16:15:42:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:15:43:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
16:15:43:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:15:43:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:15:43:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:15:44:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:15:44:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:15:44:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:15:48:ST3_smx:INFO: chip: 0-0 59.984250 C 1147.806000 mV
16:15:48:ST3_smx:INFO: Electrons
16:15:48:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:50:ST3_smx:INFO: ----> Checking Analog response
16:15:50:ST3_smx:INFO: ----> Checking broken channels
16:15:50:ST3_smx:INFO: Total # broken ch: 1
16:15:50:ST3_smx:INFO: List FAST: [32]
16:15:50:ST3_smx:INFO: List SLOW: []
16:15:50:ST3_smx:INFO: Holes
16:15:50:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:15:52:ST3_smx:INFO: ----> Checking Analog response
16:15:52:ST3_smx:INFO: ----> Checking broken channels
16:15:52:ST3_smx:INFO: Total # broken ch: 1
16:15:52:ST3_smx:INFO: List FAST: [32]
16:15:52:ST3_smx:INFO: List SLOW: []
16:15:52:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:15:52:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:15:53:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:15:53:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:15:53:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:15:53:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1130.0
16:15:54:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 63.2 | 1147.8
16:15:54:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:15:54:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1171.5
16:15:54:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1141.9
16:15:55:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 60.0 | 1153.7
16:15:55:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1135.9
16:15:55:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:15:55:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:15:56:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:15:56:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:15:56:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:15:56:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:16:00:ST3_smx:INFO: chip: 0-1 59.984250 C 1153.732915 mV
16:16:00:ST3_smx:INFO: Electrons
16:16:00:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:02:ST3_smx:INFO: ----> Checking Analog response
16:16:02:ST3_smx:INFO: ----> Checking broken channels
16:16:02:ST3_smx:INFO: Total # broken ch: 2
16:16:02:ST3_smx:INFO: List FAST: [88, 93]
16:16:02:ST3_smx:INFO: List SLOW: []
16:16:02:ST3_smx:INFO: Holes
16:16:02:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:04:ST3_smx:INFO: ----> Checking Analog response
16:16:04:ST3_smx:INFO: ----> Checking broken channels
16:16:04:ST3_smx:INFO: Total # broken ch: 2
16:16:04:ST3_smx:INFO: List FAST: [88, 93]
16:16:04:ST3_smx:INFO: List SLOW: []
16:16:04:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:16:05:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:16:05:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:16:05:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:16:05:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 60.0 | 1153.7
16:16:06:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1130.0
16:16:06:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1141.9
16:16:06:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:16:06:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1171.5
16:16:07:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1141.9
16:16:07:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1147.8
16:16:07:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1130.0
16:16:07:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:16:08:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:16:08:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:16:08:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:16:08:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:16:09:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:16:12:ST3_smx:INFO: chip: 0-2 63.173842 C 1147.806000 mV
16:16:12:ST3_smx:INFO: Electrons
16:16:12:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:14:ST3_smx:INFO: ----> Checking Analog response
16:16:14:ST3_smx:INFO: ----> Checking broken channels
16:16:14:ST3_smx:INFO: Total # broken ch: 2
16:16:14:ST3_smx:INFO: List FAST: [0, 54]
16:16:14:ST3_smx:INFO: List SLOW: []
16:16:14:ST3_smx:INFO: Holes
16:16:14:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:16:ST3_smx:INFO: ----> Checking Analog response
16:16:16:ST3_smx:INFO: ----> Checking broken channels
16:16:16:ST3_smx:INFO: Total # broken ch: 2
16:16:16:ST3_smx:INFO: List FAST: [0, 54]
16:16:16:ST3_smx:INFO: List SLOW: []
16:16:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:16:17:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:16:17:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:16:17:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:16:17:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:16:18:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:16:18:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1147.8
16:16:18:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:16:18:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1165.6
16:16:19:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1141.9
16:16:19:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:16:19:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1141.9
16:16:19:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 53.6 | 1177.4
16:16:20:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:16:20:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:16:20:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1183.3
16:16:20:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1106.2
16:16:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:16:24:ST3_smx:INFO: chip: 0-3 59.984250 C 1159.654860 mV
16:16:24:ST3_smx:INFO: Electrons
16:16:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:26:ST3_smx:INFO: ----> Checking Analog response
16:16:26:ST3_smx:INFO: ----> Checking broken channels
16:16:26:ST3_smx:INFO: Total # broken ch: 2
16:16:26:ST3_smx:INFO: List FAST: [48, 53]
16:16:26:ST3_smx:INFO: List SLOW: []
16:16:26:ST3_smx:INFO: Holes
16:16:26:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:28:ST3_smx:INFO: ----> Checking Analog response
16:16:28:ST3_smx:INFO: ----> Checking broken channels
16:16:28:ST3_smx:INFO: Total # broken ch: 2
16:16:28:ST3_smx:INFO: List FAST: [48, 53]
16:16:28:ST3_smx:INFO: List SLOW: []
16:16:28:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:16:29:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:16:29:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:16:29:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:16:29:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:16:30:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:16:30:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1147.8
16:16:30:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 66.4 | 1130.0
16:16:30:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1171.5
16:16:31:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1141.9
16:16:31:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:16:31:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1141.9
16:16:31:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 63.2 | 1153.7
16:16:32:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:16:32:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:16:32:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 50.4 | 1177.4
16:16:32:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:16:33:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:16:36:ST3_smx:INFO: chip: 0-4 50.430383 C 1189.190035 mV
16:16:36:ST3_smx:INFO: Electrons
16:16:36:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:38:ST3_smx:INFO: ----> Checking Analog response
16:16:38:ST3_smx:INFO: ----> Checking broken channels
16:16:38:ST3_smx:INFO: Total # broken ch: 3
16:16:38:ST3_smx:INFO: List FAST: [19, 50, 121]
16:16:38:ST3_smx:INFO: List SLOW: []
16:16:38:ST3_smx:INFO: Holes
16:16:38:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:40:ST3_smx:INFO: ----> Checking Analog response
16:16:40:ST3_smx:INFO: ----> Checking broken channels
16:16:41:ST3_smx:INFO: Total # broken ch: 3
16:16:41:ST3_smx:INFO: List FAST: [19, 50, 121]
16:16:41:ST3_smx:INFO: List SLOW: []
16:16:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:16:41:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:16:41:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:16:41:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:16:42:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:16:42:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:16:42:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1147.8
16:16:42:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 69.6 | 1130.0
16:16:43:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1171.5
16:16:43:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 60.0 | 1141.9
16:16:43:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:16:43:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1141.9
16:16:44:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 63.2 | 1159.7
16:16:44:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:16:44:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 56.8 | 1165.6
16:16:44:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1177.4
16:16:45:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1100.2
16:16:45:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:16:48:ST3_smx:INFO: chip: 0-5 59.984250 C 1165.571835 mV
16:16:48:ST3_smx:INFO: Electrons
16:16:48:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:50:ST3_smx:INFO: ----> Checking Analog response
16:16:50:ST3_smx:INFO: ----> Checking broken channels
16:16:51:ST3_smx:INFO: Total # broken ch: 7
16:16:51:ST3_smx:INFO: List FAST: [14, 19, 20, 55, 56, 81, 112]
16:16:51:ST3_smx:INFO: List SLOW: []
16:16:51:ST3_smx:INFO: Holes
16:16:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:16:53:ST3_smx:INFO: ----> Checking Analog response
16:16:53:ST3_smx:INFO: ----> Checking broken channels
16:16:53:ST3_smx:INFO: Total # broken ch: 7
16:16:53:ST3_smx:INFO: List FAST: [14, 19, 20, 55, 56, 81, 112]
16:16:53:ST3_smx:INFO: List SLOW: []
16:16:53:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:16:53:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:16:53:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:16:54:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:16:54:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:16:54:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1130.0
16:16:54:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1147.8
16:16:55:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 69.6 | 1130.0
16:16:55:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1171.5
16:16:55:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 63.2 | 1141.9
16:16:55:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:16:56:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1141.9
16:16:56:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 63.2 | 1159.7
16:16:56:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:16:56:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1159.7
16:16:56:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 53.6 | 1177.4
16:16:57:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:16:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:17:01:ST3_smx:INFO: chip: 0-6 63.173842 C 1135.937260 mV
16:17:01:ST3_smx:INFO: Electrons
16:17:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:17:03:ST3_smx:INFO: ----> Checking Analog response
16:17:03:ST3_smx:INFO: ----> Checking broken channels
16:17:03:ST3_smx:INFO: Total # broken ch: 1
16:17:03:ST3_smx:INFO: List FAST: [127]
16:17:04:ST3_smx:INFO: List SLOW: []
16:17:04:ST3_smx:INFO: Holes
16:17:04:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:17:05:ST3_smx:INFO: ----> Checking Analog response
16:17:05:ST3_smx:INFO: ----> Checking broken channels
16:17:06:ST3_smx:INFO: Total # broken ch: 1
16:17:06:ST3_smx:INFO: List FAST: [127]
16:17:06:ST3_smx:INFO: List SLOW: []
16:17:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:17:06:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:17:06:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:17:06:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:17:07:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:17:07:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1130.0
16:17:07:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1147.8
16:17:07:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 69.6 | 1130.0
16:17:08:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1165.6
16:17:08:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 63.2 | 1141.9
16:17:08:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:17:08:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1141.9
16:17:09:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 63.2 | 1159.7
16:17:09:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 53.6 | 1183.3
16:17:09:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1159.7
16:17:09:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 63.2 | 1135.9
16:17:10:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 76.0 | 1100.2
16:17:10:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
16:17:13:ST3_smx:INFO: chip: 0-7 72.757530 C 1112.140140 mV
16:17:13:ST3_smx:INFO: Electrons
16:17:13:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:17:15:ST3_smx:INFO: ----> Checking Analog response
16:17:15:ST3_smx:INFO: ----> Checking broken channels
16:17:16:ST3_smx:INFO: Total # broken ch: 2
16:17:16:ST3_smx:INFO: List FAST: [5, 88]
16:17:16:ST3_smx:INFO: List SLOW: []
16:17:16:ST3_smx:INFO: Holes
16:17:16:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
16:17:18:ST3_smx:INFO: ----> Checking Analog response
16:17:18:ST3_smx:INFO: ----> Checking broken channels
16:17:18:ST3_smx:INFO: Total # broken ch: 2
16:17:18:ST3_smx:INFO: List FAST: [5, 88]
16:17:18:ST3_smx:INFO: List SLOW: []
16:17:18:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
16:17:18:febtest:INFO: 0-0 | XA-000-08-002-000-001-022-04 | 56.8 | 1159.7
16:17:18:febtest:INFO: 0-1 | XA-000-08-002-000-001-018-04 | 56.8 | 1171.5
16:17:19:febtest:INFO: 0-2 | XA-000-08-002-000-001-025-04 | 66.4 | 1130.0
16:17:19:febtest:INFO: 0-3 | XA-000-08-002-000-001-023-04 | 63.2 | 1153.7
16:17:19:febtest:INFO: 0-4 | XA-000-08-002-000-001-037-13 | 66.4 | 1124.0
16:17:19:febtest:INFO: 0-5 | XA-000-08-002-000-001-020-04 | 66.4 | 1147.8
16:17:20:febtest:INFO: 0-6 | XA-000-08-002-000-001-034-13 | 69.6 | 1130.0
16:17:20:febtest:INFO: 0-7 | XA-000-08-002-000-001-036-13 | 60.0 | 1165.6
16:17:20:febtest:INFO: 0-0 | XA-000-08-002-000-001-021-04 | 63.2 | 1141.9
16:17:20:febtest:INFO: 0-1 | XA-000-08-002-000-002-021-10 | 63.2 | 1153.7
16:17:20:febtest:INFO: 0-2 | XA-000-08-002-000-001-024-04 | 63.2 | 1141.9
16:17:21:febtest:INFO: 0-3 | XA-000-08-002-000-002-019-10 | 63.2 | 1159.7
16:17:21:febtest:INFO: 0-4 | XA-000-08-002-000-001-019-04 | 50.4 | 1183.3
16:17:21:febtest:INFO: 0-5 | XA-000-08-002-000-001-017-04 | 60.0 | 1159.7
16:17:21:febtest:INFO: 0-6 | XA-000-08-002-000-001-015-03 | 63.2 | 1135.9
16:17:21:febtest:INFO: 0-7 | XA-000-08-002-000-001-016-04 | 72.8 | 1106.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_20-16_13_40', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-001-016-04', 'FUSED_ID': 6359364699116540164, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 2, 'N_BROKEN_FAST': '[5, 88]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 2, 'P_BROKEN_FAST': '[5, 88]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.444', '3.8410', '1.842', '4.8560', '7.000', '1.5670', '7.000', '1.5670'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_20-16_13_40
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.444', '3.8410', '1.842', '4.8560', '7.000', '1.5670', '7.000', '1.5670']
VI_after__Init : ['2.450', '4.1240', '1.850', '0.6508', '7.000', '1.5620', '7.000', '1.5620']
VI_at__the_End : ['2.450', '4.1240', '1.850', '0.6508', '7.000', '1.5620', '7.000', '1.5620']
16:17:42:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1029/TestDate_2023_11_20-16_13_40/