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FEB_1036 30.11.23 10:32:33
Info
10:30:51:febtest:INFO: FEB 8-2 selected
10:30:51:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:30:54:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Robert V.;
10:30:54:ST3_Shared:INFO: Listo of operators:Robert V.;
10:31:03:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:31:03:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:31:03:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:31:03:febtest:INFO: Testing FEB with SN 1036
10:31:05:smx_tester:INFO: Scanning setup
10:31:05:elinks:INFO: Disabling clock on downlink 0
10:31:05:elinks:INFO: Disabling clock on downlink 1
10:31:05:elinks:INFO: Disabling clock on downlink 2
10:31:05:elinks:INFO: Disabling clock on downlink 3
10:31:05:elinks:INFO: Disabling clock on downlink 4
10:31:05:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:31:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:31:05:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:31:05:elinks:INFO: Disabling clock on downlink 0
10:31:05:elinks:INFO: Disabling clock on downlink 1
10:31:05:elinks:INFO: Disabling clock on downlink 2
10:31:05:elinks:INFO: Disabling clock on downlink 3
10:31:05:elinks:INFO: Disabling clock on downlink 4
10:31:05:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:31:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
10:31:05:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
10:31:05:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:31:05:elinks:INFO: Disabling clock on downlink 0
10:31:05:elinks:INFO: Disabling clock on downlink 1
10:31:05:elinks:INFO: Disabling clock on downlink 2
10:31:05:elinks:INFO: Disabling clock on downlink 3
10:31:05:elinks:INFO: Disabling clock on downlink 4
10:31:05:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:31:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:31:05:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:31:05:elinks:INFO: Disabling clock on downlink 0
10:31:05:elinks:INFO: Disabling clock on downlink 1
10:31:05:elinks:INFO: Disabling clock on downlink 2
10:31:05:elinks:INFO: Disabling clock on downlink 3
10:31:05:elinks:INFO: Disabling clock on downlink 4
10:31:05:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:31:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:31:05:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:31:05:elinks:INFO: Disabling clock on downlink 0
10:31:05:elinks:INFO: Disabling clock on downlink 1
10:31:05:elinks:INFO: Disabling clock on downlink 2
10:31:05:elinks:INFO: Disabling clock on downlink 3
10:31:05:elinks:INFO: Disabling clock on downlink 4
10:31:05:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:31:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:31:06:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:31:06:setup_element:INFO: Scanning clock phase
10:31:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:31:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:31:06:setup_element:INFO: Clock phase scan results for group 0, downlink 1
10:31:06:setup_element:INFO: Eye window for uplink 0 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:31:06:setup_element:INFO: Eye window for uplink 1 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:31:06:setup_element:INFO: Eye window for uplink 2 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:31:06:setup_element:INFO: Eye window for uplink 3 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:31:06:setup_element:INFO: Eye window for uplink 4 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:31:06:setup_element:INFO: Eye window for uplink 5 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:31:06:setup_element:INFO: Eye window for uplink 6 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:31:06:setup_element:INFO: Eye window for uplink 7 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:31:06:setup_element:INFO: Eye window for uplink 8 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:31:06:setup_element:INFO: Eye window for uplink 9 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:31:06:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:31:06:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:31:06:setup_element:INFO: Eye window for uplink 12: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:31:06:setup_element:INFO: Eye window for uplink 13: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:31:06:setup_element:INFO: Eye window for uplink 14: X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:31:06:setup_element:INFO: Eye window for uplink 15: X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:31:06:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
10:31:06:setup_element:INFO: Scanning data phases
10:31:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:31:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:31:12:setup_element:INFO: Data phase scan results for group 0, downlink 1
10:31:12:setup_element:INFO: Eye window for uplink 0 : ___________XXXXX________________________
Data delay found: 33
10:31:12:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
10:31:12:setup_element:INFO: Eye window for uplink 2 : _________XXXXX__________________________
Data delay found: 31
10:31:12:setup_element:INFO: Eye window for uplink 3 : _______XXXXX____________________________
Data delay found: 29
10:31:12:setup_element:INFO: Eye window for uplink 4 : _______XXXXX____________________________
Data delay found: 29
10:31:12:setup_element:INFO: Eye window for uplink 5 : ___XXXX_________________________________
Data delay found: 24
10:31:12:setup_element:INFO: Eye window for uplink 6 : XXXX__________________________________XX
Data delay found: 20
10:31:12:setup_element:INFO: Eye window for uplink 7 : __________________________________XXXXX_
Data delay found: 16
10:31:12:setup_element:INFO: Eye window for uplink 8 : __________________________XXXXX_________
Data delay found: 8
10:31:12:setup_element:INFO: Eye window for uplink 9 : _______________________________XXXXX____
Data delay found: 13
10:31:12:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
10:31:12:setup_element:INFO: Eye window for uplink 11: ______________________________XXXXX_____
Data delay found: 12
10:31:12:setup_element:INFO: Eye window for uplink 12: ____________________________XXXXX_______
Data delay found: 10
10:31:12:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
10:31:12:setup_element:INFO: Eye window for uplink 14: _____________________________XXXXX______
Data delay found: 11
10:31:12:setup_element:INFO: Eye window for uplink 15: ________________________________XXXXX___
Data delay found: 14
10:31:12:setup_element:INFO: Setting the data phase to 33 for uplink 0
10:31:12:setup_element:INFO: Setting the data phase to 30 for uplink 1
10:31:12:setup_element:INFO: Setting the data phase to 31 for uplink 2
10:31:12:setup_element:INFO: Setting the data phase to 29 for uplink 3
10:31:12:setup_element:INFO: Setting the data phase to 29 for uplink 4
10:31:12:setup_element:INFO: Setting the data phase to 24 for uplink 5
10:31:12:setup_element:INFO: Setting the data phase to 20 for uplink 6
10:31:12:setup_element:INFO: Setting the data phase to 16 for uplink 7
10:31:12:setup_element:INFO: Setting the data phase to 8 for uplink 8
10:31:12:setup_element:INFO: Setting the data phase to 13 for uplink 9
10:31:12:setup_element:INFO: Setting the data phase to 8 for uplink 10
10:31:12:setup_element:INFO: Setting the data phase to 12 for uplink 11
10:31:12:setup_element:INFO: Setting the data phase to 10 for uplink 12
10:31:12:setup_element:INFO: Setting the data phase to 13 for uplink 13
10:31:12:setup_element:INFO: Setting the data phase to 11 for uplink 14
10:31:12:setup_element:INFO: Setting the data phase to 14 for uplink 15
10:31:12:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: X_________________________________________________________________________XXXXXX
Uplink 3: X_________________________________________________________________________XXXXXX
Uplink 4: X________________________________________________________________________XXXXXXX
Uplink 5: X________________________________________________________________________XXXXXXX
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: ________________________________________________________________________XXXXXXX_
Uplink 9: ________________________________________________________________________XXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: X________________________________________________________________________XXXXXXX
Uplink 15: X________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 7:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 15:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
]
10:31:12:setup_element:INFO: Beginning SMX ASICs map scan
10:31:12:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:31:12:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:31:12:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:31:12:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:31:12:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:31:12:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
10:31:12:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
10:31:12:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
10:31:12:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
10:31:12:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
10:31:12:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
10:31:13:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
10:31:13:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
10:31:13:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
10:31:13:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
10:31:13:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
10:31:13:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
10:31:13:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
10:31:13:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
10:31:13:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
10:31:13:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
10:31:15:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: X_________________________________________________________________________XXXXXX
Uplink 3: X_________________________________________________________________________XXXXXX
Uplink 4: X________________________________________________________________________XXXXXXX
Uplink 5: X________________________________________________________________________XXXXXXX
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: ________________________________________________________________________XXXXXXX_
Uplink 9: ________________________________________________________________________XXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: X________________________________________________________________________XXXXXXX
Uplink 15: X________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 7:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 15:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
10:31:15:setup_element:INFO: Performing Elink synchronization
10:31:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:31:15:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:31:15:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:31:15:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:31:15:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
10:31:15:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:31:15:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
10:31:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:31:16:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 31.4 | 1183.3
10:31:16:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 18.7 | 1212.7
10:31:16:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 3.0 | 1277.1
10:31:17:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 12.4 | 1230.3
10:31:17:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 9.3 | 1259.6
10:31:17:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1195.1
10:31:17:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:31:18:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1224.5
10:31:18:ST3_smx:INFO: Configuring SMX FAST
10:31:20:ST3_smx:INFO: chip: 1-0 37.726682 C 1159.654860 mV
10:31:20:ST3_smx:INFO: Electrons
10:31:20:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:22:ST3_smx:INFO: ----> Checking Analog response
10:31:22:ST3_smx:INFO: ----> Checking broken channels
10:31:22:ST3_smx:INFO: Total # broken ch: 1
10:31:22:ST3_smx:INFO: List FAST: [75]
10:31:22:ST3_smx:INFO: List SLOW: []
10:31:22:ST3_smx:INFO: Holes
10:31:22:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:24:ST3_smx:INFO: ----> Checking Analog response
10:31:24:ST3_smx:INFO: ----> Checking broken channels
10:31:24:ST3_smx:INFO: Total # broken ch: 1
10:31:24:ST3_smx:INFO: List FAST: [75]
10:31:24:ST3_smx:INFO: List SLOW: []
10:31:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:31:24:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1153.7
10:31:25:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 18.7 | 1212.7
10:31:25:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 3.0 | 1277.1
10:31:25:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 12.4 | 1230.3
10:31:25:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 6.1 | 1265.4
10:31:26:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1195.1
10:31:26:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:31:26:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1224.5
10:31:26:ST3_smx:INFO: Configuring SMX FAST
10:31:28:ST3_smx:INFO: chip: 8-1 28.225000 C 1183.292940 mV
10:31:28:ST3_smx:INFO: Electrons
10:31:28:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:30:ST3_smx:INFO: ----> Checking Analog response
10:31:30:ST3_smx:INFO: ----> Checking broken channels
10:31:30:ST3_smx:INFO: Total # broken ch: 0
10:31:30:ST3_smx:INFO: List FAST: []
10:31:30:ST3_smx:INFO: List SLOW: []
10:31:30:ST3_smx:INFO: Holes
10:31:30:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:32:ST3_smx:INFO: ----> Checking Analog response
10:31:32:ST3_smx:INFO: ----> Checking broken channels
10:31:33:ST3_smx:INFO: Total # broken ch: 0
10:31:33:ST3_smx:INFO: List FAST: []
10:31:33:ST3_smx:INFO: List SLOW: []
10:31:33:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:31:33:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 37.7 | 1159.7
10:31:33:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1177.4
10:31:33:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 3.0 | 1277.1
10:31:34:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 12.4 | 1230.3
10:31:34:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 6.1 | 1259.6
10:31:34:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1195.1
10:31:34:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:31:35:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1224.5
10:31:35:ST3_smx:INFO: Configuring SMX FAST
10:31:37:ST3_smx:INFO: chip: 3-2 15.590880 C 1236.187875 mV
10:31:37:ST3_smx:INFO: Electrons
10:31:37:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:39:ST3_smx:INFO: ----> Checking Analog response
10:31:39:ST3_smx:INFO: ----> Checking broken channels
10:31:39:ST3_smx:INFO: Total # broken ch: 1
10:31:39:ST3_smx:INFO: List FAST: [21]
10:31:39:ST3_smx:INFO: List SLOW: []
10:31:39:ST3_smx:INFO: Holes
10:31:39:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:41:ST3_smx:INFO: ----> Checking Analog response
10:31:41:ST3_smx:INFO: ----> Checking broken channels
10:31:41:ST3_smx:INFO: Total # broken ch: 1
10:31:41:ST3_smx:INFO: List FAST: [21]
10:31:41:ST3_smx:INFO: List SLOW: []
10:31:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:31:41:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 37.7 | 1159.7
10:31:42:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1177.4
10:31:42:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1236.2
10:31:42:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 12.4 | 1236.2
10:31:42:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 9.3 | 1259.6
10:31:43:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1195.1
10:31:43:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:31:43:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1224.5
10:31:43:ST3_smx:INFO: Configuring SMX FAST
10:31:45:ST3_smx:INFO: chip: 10-3 21.902970 C 1206.851500 mV
10:31:45:ST3_smx:INFO: Electrons
10:31:45:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:47:ST3_smx:INFO: ----> Checking Analog response
10:31:47:ST3_smx:INFO: ----> Checking broken channels
10:31:47:ST3_smx:INFO: Total # broken ch: 5
10:31:47:ST3_smx:INFO: List FAST: [2, 50, 52, 106, 119]
10:31:48:ST3_smx:INFO: List SLOW: []
10:31:48:ST3_smx:INFO: Holes
10:31:48:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:49:ST3_smx:INFO: ----> Checking Analog response
10:31:49:ST3_smx:INFO: ----> Checking broken channels
10:31:50:ST3_smx:INFO: Total # broken ch: 5
10:31:50:ST3_smx:INFO: List FAST: [2, 50, 52, 106, 119]
10:31:50:ST3_smx:INFO: List SLOW: []
10:31:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:31:50:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1159.7
10:31:50:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1183.3
10:31:50:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1236.2
10:31:51:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1201.0
10:31:51:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 9.3 | 1265.4
10:31:51:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1195.1
10:31:51:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:31:52:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1230.3
10:31:52:ST3_smx:INFO: Configuring SMX FAST
10:31:54:ST3_smx:INFO: chip: 5-4 18.745682 C 1224.468235 mV
10:31:54:ST3_smx:INFO: Electrons
10:31:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:56:ST3_smx:INFO: ----> Checking Analog response
10:31:56:ST3_smx:INFO: ----> Checking broken channels
10:31:56:ST3_smx:INFO: Total # broken ch: 2
10:31:56:ST3_smx:INFO: List FAST: [11, 79]
10:31:56:ST3_smx:INFO: List SLOW: []
10:31:56:ST3_smx:INFO: Holes
10:31:56:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:31:58:ST3_smx:INFO: ----> Checking Analog response
10:31:58:ST3_smx:INFO: ----> Checking broken channels
10:31:58:ST3_smx:INFO: Total # broken ch: 2
10:31:58:ST3_smx:INFO: List FAST: [11, 79]
10:31:58:ST3_smx:INFO: List SLOW: []
10:31:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:31:58:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1159.7
10:31:59:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1177.4
10:31:59:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1236.2
10:31:59:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1201.0
10:31:59:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 21.9 | 1224.5
10:32:00:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1195.1
10:32:00:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1195.1
10:32:00:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1224.5
10:32:00:ST3_smx:INFO: Configuring SMX FAST
10:32:02:ST3_smx:INFO: chip: 12-5 25.062742 C 1206.851500 mV
10:32:02:ST3_smx:INFO: Electrons
10:32:02:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:32:04:ST3_smx:INFO: ----> Checking Analog response
10:32:04:ST3_smx:INFO: ----> Checking broken channels
10:32:05:ST3_smx:INFO: Total # broken ch: 2
10:32:05:ST3_smx:INFO: List FAST: [9, 101]
10:32:05:ST3_smx:INFO: List SLOW: []
10:32:05:ST3_smx:INFO: Holes
10:32:05:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:32:07:ST3_smx:INFO: ----> Checking Analog response
10:32:07:ST3_smx:INFO: ----> Checking broken channels
10:32:07:ST3_smx:INFO: Total # broken ch: 2
10:32:07:ST3_smx:INFO: List FAST: [9, 101]
10:32:07:ST3_smx:INFO: List SLOW: []
10:32:07:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:32:07:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1159.7
10:32:07:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1183.3
10:32:08:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1236.2
10:32:08:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1201.0
10:32:08:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 21.9 | 1224.5
10:32:08:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1201.0
10:32:09:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:32:09:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1224.5
10:32:09:ST3_smx:INFO: Configuring SMX FAST
10:32:11:ST3_smx:INFO: chip: 7-6 28.225000 C 1200.969315 mV
10:32:11:ST3_smx:INFO: Electrons
10:32:11:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:32:13:ST3_smx:INFO: ----> Checking Analog response
10:32:13:ST3_smx:INFO: ----> Checking broken channels
10:32:13:ST3_smx:INFO: Total # broken ch: 1
10:32:13:ST3_smx:INFO: List FAST: [14]
10:32:13:ST3_smx:INFO: List SLOW: []
10:32:13:ST3_smx:INFO: Holes
10:32:13:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:32:15:ST3_smx:INFO: ----> Checking Analog response
10:32:15:ST3_smx:INFO: ----> Checking broken channels
10:32:16:ST3_smx:INFO: Total # broken ch: 1
10:32:16:ST3_smx:INFO: List FAST: [14]
10:32:16:ST3_smx:INFO: List SLOW: []
10:32:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:32:16:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1159.7
10:32:16:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1183.3
10:32:16:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1236.2
10:32:17:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1201.0
10:32:17:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 21.9 | 1224.5
10:32:17:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1201.0
10:32:17:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 31.4 | 1201.0
10:32:17:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1230.3
10:32:18:ST3_smx:INFO: Configuring SMX FAST
10:32:20:ST3_smx:INFO: chip: 14-7 18.745682 C 1236.187875 mV
10:32:20:ST3_smx:INFO: Electrons
10:32:20:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:32:22:ST3_smx:INFO: ----> Checking Analog response
10:32:22:ST3_smx:INFO: ----> Checking broken channels
10:32:22:ST3_smx:INFO: Total # broken ch: 3
10:32:22:ST3_smx:INFO: List FAST: [18, 31, 35]
10:32:22:ST3_smx:INFO: List SLOW: []
10:32:22:ST3_smx:INFO: Holes
10:32:22:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:32:24:ST3_smx:INFO: ----> Checking Analog response
10:32:24:ST3_smx:INFO: ----> Checking broken channels
10:32:24:ST3_smx:INFO: Total # broken ch: 3
10:32:24:ST3_smx:INFO: List FAST: [18, 31, 35]
10:32:24:ST3_smx:INFO: List SLOW: []
10:32:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:32:24:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1159.7
10:32:25:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1183.3
10:32:25:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1236.2
10:32:25:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1201.0
10:32:25:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 21.9 | 1224.5
10:32:26:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 25.1 | 1206.9
10:32:26:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 31.4 | 1201.0
10:32:26:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 18.7 | 1230.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_30-10_31_03', 'OPERATOR': 'Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-001-007-237-15', 'FUSED_ID': 6359364699117616863, 'HW_ADDR': 7, 'UPLINK': 14, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 3, 'N_BROKEN_FAST': '[18, 31, 35]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 3, 'P_BROKEN_FAST': '[18, 31, 35]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': 0, 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '15403\n', 'MODULE_NAME': 'L3DL500114 M3DL5T1001141A2 62 C\n', 'MODULE_LADDER': 'L3DL500114', 'MODULE_MODULE': 'M3DL5T1001141A2', 'MODULE_SIZE': 62, 'MODULE_GRADE': 'C', 'MODULE_TYPE': '', 'VI_bInit': ['2.447', '1.8710', '1.846', '2.2660', '7.000', '1.5550', '7.000', '1.5550'], 'VI_aInit': ['2.450', '2.0170', '1.850', '0.6156', '7.000', '1.5510', '7.000', '1.5510'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 200, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_30-10_31_03
OPERATOR : Robert V.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME : L3DL500114 M3DL5T1001141A2 62 C
FEB_SN : 0
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAMEL3DL500114 M3DL5T1001141A2 62 C
---------------------------------------
VI_before_Init : ['2.447', '1.8710', '1.846', '2.2660', '7.000', '1.5550', '7.000', '1.5550']
VI_after__Init : ['2.450', '2.0170', '1.850', '0.3185', '7.000', '1.5510', '7.000', '1.5510']
VI_at__the_End : ['2.450', '2.0170', '1.850', '0.3185', '7.000', '1.5510', '7.000', '1.5510']
10:32:33:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:32:33:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
10:32:33:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:32:33:febtest:INFO: Testing FEB with SN 1036
10:32:34:smx_tester:INFO: Scanning setup
10:32:34:elinks:INFO: Disabling clock on downlink 0
10:32:34:elinks:INFO: Disabling clock on downlink 1
10:32:34:elinks:INFO: Disabling clock on downlink 2
10:32:34:elinks:INFO: Disabling clock on downlink 3
10:32:34:elinks:INFO: Disabling clock on downlink 4
10:32:34:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:32:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:32:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:32:35:elinks:INFO: Disabling clock on downlink 0
10:32:35:elinks:INFO: Disabling clock on downlink 1
10:32:35:elinks:INFO: Disabling clock on downlink 2
10:32:35:elinks:INFO: Disabling clock on downlink 3
10:32:35:elinks:INFO: Disabling clock on downlink 4
10:32:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:32:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
10:32:35:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
10:32:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:32:35:elinks:INFO: Disabling clock on downlink 0
10:32:35:elinks:INFO: Disabling clock on downlink 1
10:32:35:elinks:INFO: Disabling clock on downlink 2
10:32:35:elinks:INFO: Disabling clock on downlink 3
10:32:35:elinks:INFO: Disabling clock on downlink 4
10:32:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:32:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:32:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:32:35:elinks:INFO: Disabling clock on downlink 0
10:32:35:elinks:INFO: Disabling clock on downlink 1
10:32:35:elinks:INFO: Disabling clock on downlink 2
10:32:35:elinks:INFO: Disabling clock on downlink 3
10:32:35:elinks:INFO: Disabling clock on downlink 4
10:32:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:32:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:32:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:32:35:elinks:INFO: Disabling clock on downlink 0
10:32:35:elinks:INFO: Disabling clock on downlink 1
10:32:35:elinks:INFO: Disabling clock on downlink 2
10:32:35:elinks:INFO: Disabling clock on downlink 3
10:32:35:elinks:INFO: Disabling clock on downlink 4
10:32:35:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:32:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:32:35:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:32:35:setup_element:INFO: Scanning clock phase
10:32:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:32:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:32:35:setup_element:INFO: Clock phase scan results for group 0, downlink 1
10:32:35:setup_element:INFO: Eye window for uplink 0 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:32:35:setup_element:INFO: Eye window for uplink 1 : X_________________________________________________________________________XXXXXX
Clock Delay: 37
10:32:35:setup_element:INFO: Eye window for uplink 2 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:35:setup_element:INFO: Eye window for uplink 3 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:35:setup_element:INFO: Eye window for uplink 4 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:35:setup_element:INFO: Eye window for uplink 5 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:35:setup_element:INFO: Eye window for uplink 6 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:35:setup_element:INFO: Eye window for uplink 7 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:36:setup_element:INFO: Eye window for uplink 8 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:32:36:setup_element:INFO: Eye window for uplink 9 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:32:36:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:32:36:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
10:32:36:setup_element:INFO: Eye window for uplink 12: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:32:36:setup_element:INFO: Eye window for uplink 13: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
10:32:36:setup_element:INFO: Eye window for uplink 14: _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:36:setup_element:INFO: Eye window for uplink 15: _________________________________________________________________________XXXXXXX
Clock Delay: 36
10:32:36:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
10:32:36:setup_element:INFO: Scanning data phases
10:32:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:32:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:32:40:setup_element:INFO: Data phase scan results for group 0, downlink 1
10:32:40:setup_element:INFO: Eye window for uplink 0 : ___________XXXXX________________________
Data delay found: 33
10:32:41:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
10:32:41:setup_element:INFO: Eye window for uplink 2 : ________XXXXXX__________________________
Data delay found: 30
10:32:41:setup_element:INFO: Eye window for uplink 3 : ______XXXXX_____________________________
Data delay found: 28
10:32:41:setup_element:INFO: Eye window for uplink 4 : ______XXXXX_____________________________
Data delay found: 28
10:32:41:setup_element:INFO: Eye window for uplink 5 : __XXXXX_________________________________
Data delay found: 24
10:32:41:setup_element:INFO: Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
10:32:41:setup_element:INFO: Eye window for uplink 7 : _________________________________XXXXX__
Data delay found: 15
10:32:41:setup_element:INFO: Eye window for uplink 8 : __________________________XXXX__________
Data delay found: 7
10:32:41:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
10:32:41:setup_element:INFO: Eye window for uplink 10: __________________________XXXXX_________
Data delay found: 8
10:32:41:setup_element:INFO: Eye window for uplink 11: ______________________________XXXX______
Data delay found: 11
10:32:41:setup_element:INFO: Eye window for uplink 12: ___________________________XXXXX________
Data delay found: 9
10:32:41:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
10:32:41:setup_element:INFO: Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
10:32:41:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXXX___
Data delay found: 13
10:32:41:setup_element:INFO: Setting the data phase to 33 for uplink 0
10:32:41:setup_element:INFO: Setting the data phase to 30 for uplink 1
10:32:41:setup_element:INFO: Setting the data phase to 30 for uplink 2
10:32:41:setup_element:INFO: Setting the data phase to 28 for uplink 3
10:32:41:setup_element:INFO: Setting the data phase to 28 for uplink 4
10:32:41:setup_element:INFO: Setting the data phase to 24 for uplink 5
10:32:41:setup_element:INFO: Setting the data phase to 20 for uplink 6
10:32:41:setup_element:INFO: Setting the data phase to 15 for uplink 7
10:32:41:setup_element:INFO: Setting the data phase to 7 for uplink 8
10:32:41:setup_element:INFO: Setting the data phase to 12 for uplink 9
10:32:41:setup_element:INFO: Setting the data phase to 8 for uplink 10
10:32:41:setup_element:INFO: Setting the data phase to 11 for uplink 11
10:32:41:setup_element:INFO: Setting the data phase to 9 for uplink 12
10:32:41:setup_element:INFO: Setting the data phase to 13 for uplink 13
10:32:41:setup_element:INFO: Setting the data phase to 10 for uplink 14
10:32:41:setup_element:INFO: Setting the data phase to 13 for uplink 15
10:32:41:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: X________________________________________________________________________XXXXXXX
Uplink 5: X________________________________________________________________________XXXXXXX
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: _______________________________________________________________________XXXXXXXX_
Uplink 9: _______________________________________________________________________XXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: _________________________________________________________________________XXXXXXX
Uplink 15: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 11:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
]
10:32:41:setup_element:INFO: Beginning SMX ASICs map scan
10:32:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:32:41:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:32:41:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:32:41:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:32:41:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:32:41:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
10:32:41:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
10:32:41:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
10:32:41:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
10:32:41:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
10:32:41:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
10:32:41:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
10:32:41:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
10:32:41:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
10:32:41:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
10:32:42:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
10:32:42:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
10:32:42:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
10:32:42:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
10:32:42:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
10:32:42:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
10:32:43:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 70
Eye Windows:
Uplink 0: X_________________________________________________________________________XXXXXX
Uplink 1: X_________________________________________________________________________XXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: X________________________________________________________________________XXXXXXX
Uplink 5: X________________________________________________________________________XXXXXXX
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: _______________________________________________________________________XXXXXXXX_
Uplink 9: _______________________________________________________________________XXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: _________________________________________________________________________XXXXXXX
Uplink 15: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 11:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
10:32:43:setup_element:INFO: Performing Elink synchronization
10:32:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:32:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:32:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:32:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:32:43:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
10:32:43:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
10:32:43:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0_1 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_0__upli_1
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_8 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_1__upli_8
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_2_3 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_2__upli_3
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3_10 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_3__upli_10
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_4_5 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_4_5 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_4__upli_5
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5_12 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_5__upli_12
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_6_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_6_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_6__upli_7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7_14 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_7__upli_14
10:32:44:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:32:45:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 34.6 | 1183.3
10:32:45:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 18.7 | 1218.6
10:32:45:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 6.1 | 1282.9
10:32:45:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1206.9
10:32:45:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 12.4 | 1247.9
10:32:46:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 28.2 | 1195.1
10:32:46:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 28.2 | 1201.0
10:32:46:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 21.9 | 1224.5
10:32:46:ST3_smx:INFO: Configuring SMX FAST
10:32:48:ST3_smx:INFO: chip: 1-0 40.898880 C 1159.654860 mV
10:32:48:ST3_smx:INFO: Electrons
10:32:48:ST3_smx:INFO: # loops 0
10:32:50:ST3_smx:INFO: # loops 1
10:32:52:ST3_smx:INFO: # loops 2
10:32:53:ST3_smx:INFO: # loops 3
10:32:55:ST3_smx:INFO: # loops 4
10:32:56:ST3_smx:INFO: Total # of broken channels: 0
10:32:56:ST3_smx:INFO: List of broken channels: []
10:32:56:ST3_smx:INFO: Total # of broken channels: 0
10:32:56:ST3_smx:INFO: List of broken channels: []
10:32:57:ST3_smx:INFO: Configuring SMX FAST
10:32:59:ST3_smx:INFO: chip: 8-1 28.225000 C 1183.292940 mV
10:32:59:ST3_smx:INFO: Electrons
10:32:59:ST3_smx:INFO: # loops 0
10:33:01:ST3_smx:INFO: # loops 1
10:33:02:ST3_smx:INFO: # loops 2
10:33:04:ST3_smx:INFO: # loops 3
10:33:05:ST3_smx:INFO: # loops 4
10:33:07:ST3_smx:INFO: Total # of broken channels: 0
10:33:07:ST3_smx:INFO: List of broken channels: []
10:33:07:ST3_smx:INFO: Total # of broken channels: 0
10:33:07:ST3_smx:INFO: List of broken channels: []
10:33:08:ST3_smx:INFO: Configuring SMX FAST
10:33:10:ST3_smx:INFO: chip: 3-2 18.745682 C 1236.187875 mV
10:33:10:ST3_smx:INFO: Electrons
10:33:10:ST3_smx:INFO: # loops 0
10:33:11:ST3_smx:INFO: # loops 1
10:33:13:ST3_smx:INFO: # loops 2
10:33:14:ST3_smx:INFO: # loops 3
10:33:16:ST3_smx:INFO: # loops 4
10:33:18:ST3_smx:INFO: Total # of broken channels: 0
10:33:18:ST3_smx:INFO: List of broken channels: []
10:33:18:ST3_smx:INFO: Total # of broken channels: 12
10:33:18:ST3_smx:INFO: List of broken channels: [2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 26]
10:33:18:ST3_smx:INFO: Configuring SMX FAST
10:33:20:ST3_smx:INFO: chip: 10-3 25.062742 C 1206.851500 mV
10:33:20:ST3_smx:INFO: Electrons
10:33:20:ST3_smx:INFO: # loops 0
10:33:22:ST3_smx:INFO: # loops 1
10:33:23:ST3_smx:INFO: # loops 2
10:33:25:ST3_smx:INFO: # loops 3
10:33:27:ST3_smx:INFO: # loops 4
10:33:28:ST3_smx:INFO: Total # of broken channels: 0
10:33:28:ST3_smx:INFO: List of broken channels: []
10:33:28:ST3_smx:INFO: Total # of broken channels: 0
10:33:28:ST3_smx:INFO: List of broken channels: []
10:33:29:ST3_smx:INFO: Configuring SMX FAST
10:33:31:ST3_smx:INFO: chip: 5-4 21.902970 C 1224.468235 mV
10:33:31:ST3_smx:INFO: Electrons
10:33:31:ST3_smx:INFO: # loops 0
10:33:32:ST3_smx:INFO: # loops 1
10:33:34:ST3_smx:INFO: # loops 2
10:33:35:ST3_smx:INFO: # loops 3
10:33:37:ST3_smx:INFO: # loops 4
10:33:39:ST3_smx:INFO: Total # of broken channels: 0
10:33:39:ST3_smx:INFO: List of broken channels: []
10:33:39:ST3_smx:INFO: Total # of broken channels: 0
10:33:39:ST3_smx:INFO: List of broken channels: []
10:33:39:ST3_smx:INFO: Configuring SMX FAST
10:33:41:ST3_smx:INFO: chip: 12-5 25.062742 C 1206.851500 mV
10:33:41:ST3_smx:INFO: Electrons
10:33:41:ST3_smx:INFO: # loops 0
10:33:43:ST3_smx:INFO: # loops 1
10:33:44:ST3_smx:INFO: # loops 2
10:33:46:ST3_smx:INFO: # loops 3
10:33:47:ST3_smx:INFO: # loops 4
10:33:49:ST3_smx:INFO: Total # of broken channels: 0
10:33:49:ST3_smx:INFO: List of broken channels: []
10:33:49:ST3_smx:INFO: Total # of broken channels: 0
10:33:49:ST3_smx:INFO: List of broken channels: []
10:33:50:ST3_smx:INFO: Configuring SMX FAST
10:33:52:ST3_smx:INFO: chip: 7-6 31.389742 C 1200.969315 mV
10:33:52:ST3_smx:INFO: Electrons
10:33:52:ST3_smx:INFO: # loops 0
10:33:53:ST3_smx:INFO: # loops 1
10:33:55:ST3_smx:INFO: # loops 2
10:33:56:ST3_smx:INFO: # loops 3
10:33:58:ST3_smx:INFO: # loops 4
10:33:59:ST3_smx:INFO: Total # of broken channels: 0
10:33:59:ST3_smx:INFO: List of broken channels: []
10:33:59:ST3_smx:INFO: Total # of broken channels: 0
10:33:59:ST3_smx:INFO: List of broken channels: []
10:34:00:ST3_smx:INFO: Configuring SMX FAST
10:34:02:ST3_smx:INFO: chip: 14-7 21.902970 C 1236.187875 mV
10:34:02:ST3_smx:INFO: Electrons
10:34:02:ST3_smx:INFO: # loops 0
10:34:04:ST3_smx:INFO: # loops 1
10:34:05:ST3_smx:INFO: # loops 2
10:34:07:ST3_smx:INFO: # loops 3
10:34:08:ST3_smx:INFO: # loops 4
10:34:10:ST3_smx:INFO: Total # of broken channels: 0
10:34:10:ST3_smx:INFO: List of broken channels: []
10:34:10:ST3_smx:INFO: Total # of broken channels: 0
10:34:10:ST3_smx:INFO: List of broken channels: []
10:34:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:34:11:febtest:INFO: 1-0 | XA-000-08-002-001-007-236-15 | 40.9 | 1159.7
10:34:11:febtest:INFO: 8-1 | XA-000-08-002-001-007-248-08 | 28.2 | 1189.2
10:34:11:febtest:INFO: 3-2 | XA-000-08-002-001-008-003-10 | 18.7 | 1242.0
10:34:11:febtest:INFO: 10-3 | XA-000-08-002-001-007-230-15 | 25.1 | 1206.9
10:34:12:febtest:INFO: 5-4 | XA-000-08-002-001-008-030-13 | 21.9 | 1224.5
10:34:12:febtest:INFO: 12-5 | XA-000-08-002-001-007-232-15 | 28.2 | 1206.9
10:34:12:febtest:INFO: 7-6 | XA-000-08-002-001-007-241-08 | 31.4 | 1201.0
10:34:12:febtest:INFO: 14-7 | XA-000-08-002-001-007-237-15 | 21.9 | 1236.2
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2023_11_30-10_32_33
OPERATOR : Robert V.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME : L3DL500114 M3DL5T1001141A2 62 C
FEB_SN : 0
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.447', '1.8890', '1.846', '2.1210', '7.001', '1.5550', '7.001', '1.5550']
VI_after__Init : ['2.450', '2.0170', '1.850', '0.3185', '7.000', '1.5510', '7.000', '1.5510']
VI_at__the_End : ['2.450', '2.0170', '1.850', '0.3185', '7.000', '1.5510', '7.000', '1.5510']
10:34:29:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_2054/TestDate_2023_11_30-10_32_33/