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FEB_1039 14.11.23 13:59:07
TextEdit.txt
13:57:33:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
13:57:33:febtest:INFO: FEB8.2 selected
13:57:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
13:57:47:ST3_Shared:INFO: Listo of operators:Irakli K.;
13:57:49:ST3_Shared:INFO: Listo of operators:Olga B.; Irakli K.;
13:57:50:ST3_Shared:INFO: Listo of operators:Olga B.; Oleksandr S.; Irakli K.;
13:57:51:ST3_Shared:INFO: Listo of operators:Olga B.; Oleksandr S.; Robert V.; Irakli K.;
13:58:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:58:22:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
13:58:22:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:58:22:febtest:INFO: Tsting FEB with SN 1039
13:58:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:58:39:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
13:58:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:58:39:febtest:INFO: Tsting FEB with SN 1039
13:59:07:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:59:07:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
13:59:07:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:59:07:febtest:INFO: Tsting FEB with SN 1039
13:59:08:smx_tester:INFO: Scanning setup
13:59:08:elinks:INFO: Disabling clock on downlink 0
13:59:08:elinks:INFO: Disabling clock on downlink 1
13:59:08:elinks:INFO: Disabling clock on downlink 2
13:59:08:elinks:INFO: Disabling clock on downlink 3
13:59:08:elinks:INFO: Disabling clock on downlink 4
13:59:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:59:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:59:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:59:08:elinks:INFO: Disabling clock on downlink 0
13:59:08:elinks:INFO: Disabling clock on downlink 1
13:59:08:elinks:INFO: Disabling clock on downlink 2
13:59:08:elinks:INFO: Disabling clock on downlink 3
13:59:08:elinks:INFO: Disabling clock on downlink 4
13:59:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:59:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
13:59:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
13:59:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:59:09:elinks:INFO: Disabling clock on downlink 0
13:59:09:elinks:INFO: Disabling clock on downlink 1
13:59:09:elinks:INFO: Disabling clock on downlink 2
13:59:09:elinks:INFO: Disabling clock on downlink 3
13:59:09:elinks:INFO: Disabling clock on downlink 4
13:59:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:59:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:59:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:59:09:elinks:INFO: Disabling clock on downlink 0
13:59:09:elinks:INFO: Disabling clock on downlink 1
13:59:09:elinks:INFO: Disabling clock on downlink 2
13:59:09:elinks:INFO: Disabling clock on downlink 3
13:59:09:elinks:INFO: Disabling clock on downlink 4
13:59:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:59:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:59:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:59:09:elinks:INFO: Disabling clock on downlink 0
13:59:09:elinks:INFO: Disabling clock on downlink 1
13:59:09:elinks:INFO: Disabling clock on downlink 2
13:59:09:elinks:INFO: Disabling clock on downlink 3
13:59:09:elinks:INFO: Disabling clock on downlink 4
13:59:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:59:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:59:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:59:09:setup_element:INFO: Scanning clock phase
13:59:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:59:09:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:59:09:setup_element:INFO: Clock phase scan results for group 0, downlink 1
13:59:09:setup_element:INFO: Eye window for uplink 0 : __________________________________________________________________________XXXXXX
Clock Delay: 36
13:59:09:setup_element:INFO: Eye window for uplink 1 : __________________________________________________________________________XXXXXX
Clock Delay: 36
13:59:09:setup_element:INFO: Eye window for uplink 2 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
13:59:09:setup_element:INFO: Eye window for uplink 3 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
13:59:09:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:59:09:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:59:09:setup_element:INFO: Eye window for uplink 6 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
13:59:09:setup_element:INFO: Eye window for uplink 7 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
13:59:09:setup_element:INFO: Eye window for uplink 8 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
13:59:09:setup_element:INFO: Eye window for uplink 9 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
13:59:09:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:59:09:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:59:09:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:59:09:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
13:59:09:setup_element:INFO: Eye window for uplink 14: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
13:59:09:setup_element:INFO: Eye window for uplink 15: X_______________________________________________________________________XXXXXXXX
Clock Delay: 36
13:59:09:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
13:59:09:setup_element:INFO: Scanning data phases
13:59:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:59:10:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:59:15:setup_element:INFO: Data phase scan results for group 0, downlink 1
13:59:15:setup_element:INFO: Eye window for uplink 0 : _________XXXXXX_________________________
Data delay found: 31
13:59:15:setup_element:INFO: Eye window for uplink 1 : ______XXXXXX____________________________
Data delay found: 28
13:59:15:setup_element:INFO: Eye window for uplink 2 : _____XXXXX______________________________
Data delay found: 27
13:59:15:setup_element:INFO: Eye window for uplink 3 : __XXXXXX________________________________
Data delay found: 24
13:59:15:setup_element:INFO: Eye window for uplink 4 : __XXXXX_________________________________
Data delay found: 24
13:59:15:setup_element:INFO: Eye window for uplink 5 : XX__________________________________XXXX
Data delay found: 18
13:59:15:setup_element:INFO: Eye window for uplink 6 : XX__________________________________XXXX
Data delay found: 18
13:59:15:setup_element:INFO: Eye window for uplink 7 : _______________________________XXXXX____
Data delay found: 13
13:59:15:setup_element:INFO: Eye window for uplink 8 : ________________________XXXX____________
Data delay found: 5
13:59:15:setup_element:INFO: Eye window for uplink 9 : ____________________________XXXXX_______
Data delay found: 10
13:59:15:setup_element:INFO: Eye window for uplink 10: ________________________XXXXXX__________
Data delay found: 6
13:59:15:setup_element:INFO: Eye window for uplink 11: ____________________________XXXXX_______
Data delay found: 10
13:59:15:setup_element:INFO: Eye window for uplink 12: ___________________________XXXXX________
Data delay found: 9
13:59:15:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXX_____
Data delay found: 12
13:59:15:setup_element:INFO: Eye window for uplink 14: ___________________________XXXXX________
Data delay found: 9
13:59:15:setup_element:INFO: Eye window for uplink 15: ______________________________XXXXX_____
Data delay found: 12
13:59:15:setup_element:INFO: Setting the data phase to 31 for uplink 0
13:59:15:setup_element:INFO: Setting the data phase to 28 for uplink 1
13:59:15:setup_element:INFO: Setting the data phase to 27 for uplink 2
13:59:15:setup_element:INFO: Setting the data phase to 24 for uplink 3
13:59:15:setup_element:INFO: Setting the data phase to 24 for uplink 4
13:59:15:setup_element:INFO: Setting the data phase to 18 for uplink 5
13:59:15:setup_element:INFO: Setting the data phase to 18 for uplink 6
13:59:15:setup_element:INFO: Setting the data phase to 13 for uplink 7
13:59:15:setup_element:INFO: Setting the data phase to 5 for uplink 8
13:59:15:setup_element:INFO: Setting the data phase to 10 for uplink 9
13:59:15:setup_element:INFO: Setting the data phase to 6 for uplink 10
13:59:15:setup_element:INFO: Setting the data phase to 10 for uplink 11
13:59:15:setup_element:INFO: Setting the data phase to 9 for uplink 12
13:59:15:setup_element:INFO: Setting the data phase to 12 for uplink 13
13:59:15:setup_element:INFO: Setting the data phase to 9 for uplink 14
13:59:15:setup_element:INFO: Setting the data phase to 12 for uplink 15
13:59:15:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: __________________________________________________________________________XXXXXX
Uplink 1: __________________________________________________________________________XXXXXX
Uplink 2: _________________________________________________________________________XXXXXX_
Uplink 3: _________________________________________________________________________XXXXXX_
Uplink 4: ________________________________________________________________________XXXXXXX_
Uplink 5: ________________________________________________________________________XXXXXXX_
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: _______________________________________________________________________XXXXXXX__
Uplink 9: _______________________________________________________________________XXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: X_______________________________________________________________________XXXXXXXX
Uplink 15: X_______________________________________________________________________XXXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 1:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 2:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 4:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 5:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 6:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 8:
Optimal Phase: 5
Window Length: 36
Eye Window: ________________________XXXX____________
Uplink 9:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 10:
Optimal Phase: 6
Window Length: 34
Eye Window: ________________________XXXXXX__________
Uplink 11:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 15:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
]
13:59:15:setup_element:INFO: Beginning SMX ASICs map scan
13:59:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:59:15:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:59:15:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:59:15:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:59:15:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:59:15:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
13:59:15:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
13:59:15:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
13:59:15:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
13:59:16:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
13:59:16:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
13:59:16:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
13:59:16:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
13:59:16:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
13:59:16:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
13:59:16:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
13:59:16:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
13:59:16:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
13:59:16:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
13:59:17:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
13:59:17:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
13:59:18:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: __________________________________________________________________________XXXXXX
Uplink 1: __________________________________________________________________________XXXXXX
Uplink 2: _________________________________________________________________________XXXXXX_
Uplink 3: _________________________________________________________________________XXXXXX_
Uplink 4: ________________________________________________________________________XXXXXXX_
Uplink 5: ________________________________________________________________________XXXXXXX_
Uplink 6: _________________________________________________________________________XXXXXXX
Uplink 7: _________________________________________________________________________XXXXXXX
Uplink 8: _______________________________________________________________________XXXXXXX__
Uplink 9: _______________________________________________________________________XXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: X_______________________________________________________________________XXXXXXXX
Uplink 15: X_______________________________________________________________________XXXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 1:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 2:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 3:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 4:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 5:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 6:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 7:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 8:
Optimal Phase: 5
Window Length: 36
Eye Window: ________________________XXXX____________
Uplink 9:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 10:
Optimal Phase: 6
Window Length: 34
Eye Window: ________________________XXXXXX__________
Uplink 11:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 15:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
13:59:18:setup_element:INFO: Performing Elink synchronization
13:59:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:59:18:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:59:18:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:59:18:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:59:18:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
13:59:18:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:59:18:ST3_emu:INFO: Number of chips: 8
13:59:18:ST3_emu:INFO: Chip address: 0x0
13:59:18:ST3_emu:INFO: Chip address: 0x1
13:59:18:ST3_emu:INFO: Chip address: 0x2
13:59:18:ST3_emu:INFO: Chip address: 0x3
13:59:18:ST3_emu:INFO: Chip address: 0x4
13:59:18:ST3_emu:INFO: Chip address: 0x5
13:59:18:ST3_emu:INFO: Chip address: 0x6
13:59:18:ST3_emu:INFO: Chip address: 0x7
13:59:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:59:19:febtest:INFO: 0-0 | XA-000-08-002-000-003-020-07 | 37.7 | 1206.9
13:59:20:febtest:INFO: 0-1 | XA-000-08-002-000-003-030-07 | 37.7 | 1201.0
13:59:20:febtest:INFO: 0-2 | XA-000-08-002-000-003-023-07 | 50.4 | 1159.7
13:59:20:febtest:INFO: 0-3 | XA-000-08-002-000-003-031-07 | 44.1 | 1183.3
13:59:20:febtest:INFO: 0-4 | XA-000-08-002-000-003-026-07 | 31.4 | 1236.2
13:59:20:febtest:INFO: 0-5 | XA-000-08-002-000-003-029-07 | 34.6 | 1212.7
13:59:21:febtest:INFO: 0-6 | XA-000-08-002-000-003-025-07 | 34.6 | 1218.6
13:59:21:febtest:INFO: 0-7 | XA-000-08-002-000-003-055-09 | 34.6 | 1230.3
13:59:21:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:59:25:ST3_smx:INFO: chip: 0-0 40.898880 C 1183.292940 mV
13:59:25:ST3_smx:INFO: # loops 0
13:59:26:ST3_smx:INFO: # loops 1
13:59:28:ST3_smx:INFO: # loops 2
13:59:30:ST3_smx:INFO: # loops 3
13:59:31:ST3_smx:INFO: # loops 4
13:59:33:ST3_smx:INFO: Total # of broken channels: 0
13:59:33:ST3_smx:INFO: List of broken channels: []
13:59:33:ST3_smx:INFO: Total # of broken channels: 0
13:59:33:ST3_smx:INFO: List of broken channels: []
13:59:34:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:59:38:ST3_smx:INFO: chip: 0-1 34.556970 C 1200.969315 mV
13:59:38:ST3_smx:INFO: # loops 0
13:59:40:ST3_smx:INFO: # loops 1
13:59:41:ST3_smx:INFO: # loops 2
13:59:43:ST3_smx:INFO: # loops 3
13:59:45:ST3_smx:INFO: # loops 4
13:59:46:ST3_smx:INFO: Total # of broken channels: 0
13:59:46:ST3_smx:INFO: List of broken channels: []
13:59:46:ST3_smx:INFO: Total # of broken channels: 0
13:59:46:ST3_smx:INFO: List of broken channels: []
13:59:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:59:51:ST3_smx:INFO: chip: 0-2 50.430383 C 1153.732915 mV
13:59:51:ST3_smx:INFO: # loops 0
13:59:52:ST3_smx:INFO: # loops 1
13:59:54:ST3_smx:INFO: # loops 2
13:59:56:ST3_smx:INFO: # loops 3
13:59:57:ST3_smx:INFO: # loops 4
13:59:59:ST3_smx:INFO: Total # of broken channels: 0
13:59:59:ST3_smx:INFO: List of broken channels: []
13:59:59:ST3_smx:INFO: Total # of broken channels: 0
13:59:59:ST3_smx:INFO: List of broken channels: []
14:00:00:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:00:03:ST3_smx:INFO: chip: 0-3 37.726682 C 1189.190035 mV
14:00:03:ST3_smx:INFO: # loops 0
14:00:05:ST3_smx:INFO: # loops 1
14:00:07:ST3_smx:INFO: # loops 2
14:00:08:ST3_smx:INFO: # loops 3
14:00:10:ST3_smx:INFO: # loops 4
14:00:12:ST3_smx:INFO: Total # of broken channels: 0
14:00:12:ST3_smx:INFO: List of broken channels: []
14:00:12:ST3_smx:INFO: Total # of broken channels: 0
14:00:12:ST3_smx:INFO: List of broken channels: []
14:00:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:00:16:ST3_smx:INFO: chip: 0-4 44.073563 C 1171.483840 mV
14:00:16:ST3_smx:INFO: # loops 0
14:00:18:ST3_smx:INFO: # loops 1
14:00:19:ST3_smx:INFO: # loops 2
14:00:21:ST3_smx:INFO: # loops 3
14:00:23:ST3_smx:INFO: # loops 4
14:00:24:ST3_smx:INFO: Total # of broken channels: 0
14:00:24:ST3_smx:INFO: List of broken channels: []
14:00:24:ST3_smx:INFO: Total # of broken channels: 0
14:00:24:ST3_smx:INFO: List of broken channels: []
14:00:25:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:00:29:ST3_smx:INFO: chip: 0-5 40.898880 C 1165.571835 mV
14:00:29:ST3_smx:INFO: # loops 0
14:00:30:ST3_smx:INFO: # loops 1
14:00:32:ST3_smx:INFO: # loops 2
14:00:34:ST3_smx:INFO: # loops 3
14:00:35:ST3_smx:INFO: # loops 4
14:00:37:ST3_smx:INFO: Total # of broken channels: 0
14:00:37:ST3_smx:INFO: List of broken channels: []
14:00:37:ST3_smx:INFO: Total # of broken channels: 0
14:00:37:ST3_smx:INFO: List of broken channels: []
14:00:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:00:41:ST3_smx:INFO: chip: 0-6 34.556970 C 1218.600960 mV
14:00:41:ST3_smx:INFO: # loops 0
14:00:43:ST3_smx:INFO: # loops 1
14:00:44:ST3_smx:INFO: # loops 2
14:00:46:ST3_smx:INFO: # loops 3
14:00:48:ST3_smx:INFO: # loops 4
14:00:49:ST3_smx:INFO: Total # of broken channels: 0
14:00:49:ST3_smx:INFO: List of broken channels: []
14:00:49:ST3_smx:INFO: Total # of broken channels: 0
14:00:49:ST3_smx:INFO: List of broken channels: []
14:00:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:00:54:ST3_smx:INFO: chip: 0-7 34.556970 C 1212.728715 mV
14:00:54:ST3_smx:INFO: # loops 0
14:00:55:ST3_smx:INFO: # loops 1
14:00:57:ST3_smx:INFO: # loops 2
14:00:59:ST3_smx:INFO: # loops 3
14:01:00:ST3_smx:INFO: # loops 4
14:01:02:ST3_smx:INFO: Total # of broken channels: 0
14:01:02:ST3_smx:INFO: List of broken channels: []
14:01:02:ST3_smx:INFO: Total # of broken channels: 5
14:01:02:ST3_smx:INFO: List of broken channels: [0, 1, 3, 5, 9]
14:01:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:01:03:febtest:INFO: 0-0 | XA-000-08-002-000-003-020-07 | 40.9 | 1171.5
14:01:03:febtest:INFO: 0-1 | XA-000-08-002-000-003-030-07 | 34.6 | 1195.1
14:01:03:febtest:INFO: 0-2 | XA-000-08-002-000-003-023-07 | 53.6 | 1147.8
14:01:03:febtest:INFO: 0-3 | XA-000-08-002-000-003-031-07 | 40.9 | 1177.4
14:01:04:febtest:INFO: 0-4 | XA-000-08-002-000-003-026-07 | 47.3 | 1171.5
14:01:04:febtest:INFO: 0-5 | XA-000-08-002-000-003-029-07 | 44.1 | 1159.7
14:01:04:febtest:INFO: 0-6 | XA-000-08-002-000-003-025-07 | 34.6 | 1218.6
14:01:04:febtest:INFO: 0-7 | XA-000-08-002-000-003-055-09 | 34.6 | 1212.7
14:01:14:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1039/TestDate_2023_11_14-13_59_07/
Comment.txt
sensor 05112