FEB_1046    01.02.24 15:25:02

TextEdit.txt
            15:25:02:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:25:02:ST3_Shared:INFO:	-----------------------FEB-Microcable-----------------------
15:25:02:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:25:03:febtest:INFO:	Testing FEB with SN 1046
15:25:04:smx_tester:INFO:	Scanning setup
15:25:04:elinks:INFO:	Disabling clock on downlink 0
15:25:04:elinks:INFO:	Disabling clock on downlink 1
15:25:04:elinks:INFO:	Disabling clock on downlink 2
15:25:04:elinks:INFO:	Disabling clock on downlink 3
15:25:04:elinks:INFO:	Disabling clock on downlink 4
15:25:04:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:25:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
15:25:04:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:25:04:elinks:INFO:	Disabling clock on downlink 0
15:25:04:elinks:INFO:	Disabling clock on downlink 1
15:25:04:elinks:INFO:	Disabling clock on downlink 2
15:25:04:elinks:INFO:	Disabling clock on downlink 3
15:25:04:elinks:INFO:	Disabling clock on downlink 4
15:25:04:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:25:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
15:25:05:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
15:25:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:25:05:elinks:INFO:	Disabling clock on downlink 0
15:25:05:elinks:INFO:	Disabling clock on downlink 1
15:25:05:elinks:INFO:	Disabling clock on downlink 2
15:25:05:elinks:INFO:	Disabling clock on downlink 3
15:25:05:elinks:INFO:	Disabling clock on downlink 4
15:25:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:25:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:25:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:25:05:elinks:INFO:	Disabling clock on downlink 0
15:25:05:elinks:INFO:	Disabling clock on downlink 1
15:25:05:elinks:INFO:	Disabling clock on downlink 2
15:25:05:elinks:INFO:	Disabling clock on downlink 3
15:25:05:elinks:INFO:	Disabling clock on downlink 4
15:25:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:25:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
15:25:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:25:05:elinks:INFO:	Disabling clock on downlink 0
15:25:05:elinks:INFO:	Disabling clock on downlink 1
15:25:05:elinks:INFO:	Disabling clock on downlink 2
15:25:05:elinks:INFO:	Disabling clock on downlink 3
15:25:05:elinks:INFO:	Disabling clock on downlink 4
15:25:05:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:25:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
15:25:05:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:25:05:setup_element:INFO:	Scanning clock phase
15:25:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:25:05:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:25:05:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
15:25:05:setup_element:INFO:	Eye window for uplink 0 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:25:05:setup_element:INFO:	Eye window for uplink 1 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
15:25:05:setup_element:INFO:	Eye window for uplink 4 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:25:05:setup_element:INFO:	Eye window for uplink 5 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
15:25:05:setup_element:INFO:	Eye window for uplink 6 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
15:25:05:setup_element:INFO:	Eye window for uplink 7 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
15:25:05:setup_element:INFO:	Eye window for uplink 8 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:25:05:setup_element:INFO:	Eye window for uplink 9 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:25:05:setup_element:INFO:	Eye window for uplink 10: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:25:05:setup_element:INFO:	Eye window for uplink 11: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
15:25:05:setup_element:INFO:	Eye window for uplink 12: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:25:05:setup_element:INFO:	Eye window for uplink 13: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:25:05:setup_element:INFO:	Eye window for uplink 14: _______________________________________________________________________XXXXXX___
Clock Delay: 33
15:25:05:setup_element:INFO:	Eye window for uplink 15: _______________________________________________________________________XXXXXX___
Clock Delay: 33
15:25:06:setup_element:INFO:	Setting the clock phase to 32 for group 0, downlink 1
15:25:06:setup_element:INFO:	Scanning data phases
15:25:06:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:25:06:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:25:11:setup_element:INFO:	Data phase scan results for group 0, downlink 1
15:25:11:setup_element:INFO:	Eye window for uplink 0 : ____________XXXXX_______________________
Data delay found: 34
15:25:11:setup_element:INFO:	Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
15:25:11:setup_element:INFO:	Eye window for uplink 4 : ______XXXXX_____________________________
Data delay found: 28
15:25:11:setup_element:INFO:	Eye window for uplink 5 : __XXXX__________________________________
Data delay found: 23
15:25:11:setup_element:INFO:	Eye window for uplink 6 : XXXX___________________________________X
Data delay found: 21
15:25:11:setup_element:INFO:	Eye window for uplink 7 : X__________________________________XXXXX
Data delay found: 17
15:25:11:setup_element:INFO:	Eye window for uplink 8 : _________________________XXXXX__________
Data delay found: 7
15:25:11:setup_element:INFO:	Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
15:25:11:setup_element:INFO:	Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
15:25:11:setup_element:INFO:	Eye window for uplink 11: ______________________________XXXXX_____
Data delay found: 12
15:25:11:setup_element:INFO:	Eye window for uplink 12: ___________________________XXXXXX_______
Data delay found: 9
15:25:11:setup_element:INFO:	Eye window for uplink 13: _______________________________XXXX_____
Data delay found: 12
15:25:11:setup_element:INFO:	Eye window for uplink 14: ______________________________XXXX______
Data delay found: 11
15:25:11:setup_element:INFO:	Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
15:25:11:setup_element:INFO:	Setting the data phase to 34 for uplink 0
15:25:11:setup_element:INFO:	Setting the data phase to 30 for uplink 1
15:25:11:setup_element:INFO:	Setting the data phase to 28 for uplink 4
15:25:11:setup_element:INFO:	Setting the data phase to 23 for uplink 5
15:25:11:setup_element:INFO:	Setting the data phase to 21 for uplink 6
15:25:11:setup_element:INFO:	Setting the data phase to 17 for uplink 7
15:25:11:setup_element:INFO:	Setting the data phase to 7 for uplink 8
15:25:11:setup_element:INFO:	Setting the data phase to 12 for uplink 9
15:25:11:setup_element:INFO:	Setting the data phase to 8 for uplink 10
15:25:11:setup_element:INFO:	Setting the data phase to 12 for uplink 11
15:25:11:setup_element:INFO:	Setting the data phase to 9 for uplink 12
15:25:11:setup_element:INFO:	Setting the data phase to 12 for uplink 13
15:25:11:setup_element:INFO:	Setting the data phase to 11 for uplink 14
15:25:11:setup_element:INFO:	Setting the data phase to 13 for uplink 15
15:25:11:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 70
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXXXXX__
      Uplink  1: _______________________________________________________________________XXXXXXX__
      Uplink  4: ______________________________________________________________________XXXXXXX___
      Uplink  5: ______________________________________________________________________XXXXXXX___
      Uplink  6: _______________________________________________________________________XXXXXX___
      Uplink  7: _______________________________________________________________________XXXXXX___
      Uplink  8: ____________________________________________________________________XXXXXXXXX___
      Uplink  9: ____________________________________________________________________XXXXXXXXX___
      Uplink 10: ____________________________________________________________________XXXXXXXXX___
      Uplink 11: ____________________________________________________________________XXXXXXXXX___
      Uplink 12: _____________________________________________________________________XXXXXXXX___
      Uplink 13: _____________________________________________________________________XXXXXXXX___
      Uplink 14: _______________________________________________________________________XXXXXX___
      Uplink 15: _______________________________________________________________________XXXXXX___
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 1:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 4:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 5:
      Optimal Phase: 23
      Window Length: 36
      Eye Window: __XXXX__________________________________
    Uplink 6:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 7:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 8:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 9:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 10:
      Optimal Phase: 8
      Window Length: 34
      Eye Window: __________________________XXXXXX________
    Uplink 11:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 12:
      Optimal Phase: 9
      Window Length: 34
      Eye Window: ___________________________XXXXXX_______
    Uplink 13:
      Optimal Phase: 12
      Window Length: 36
      Eye Window: _______________________________XXXX_____
    Uplink 14:
      Optimal Phase: 11
      Window Length: 36
      Eye Window: ______________________________XXXX______
    Uplink 15:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
]
15:25:11:setup_element:INFO:	Beginning SMX ASICs map scan
15:25:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:25:11:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:25:11:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
15:25:11:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
15:25:11:uplink:INFO:	Setting uplinks mask [0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:25:11:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
15:25:11:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
15:25:11:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
15:25:11:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
15:25:12:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
15:25:12:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
15:25:12:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
15:25:12:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
15:25:12:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
15:25:12:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
15:25:12:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
15:25:12:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
15:25:12:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
15:25:13:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
15:25:14:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 70
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXXXXX__
      Uplink  1: _______________________________________________________________________XXXXXXX__
      Uplink  4: ______________________________________________________________________XXXXXXX___
      Uplink  5: ______________________________________________________________________XXXXXXX___
      Uplink  6: _______________________________________________________________________XXXXXX___
      Uplink  7: _______________________________________________________________________XXXXXX___
      Uplink  8: ____________________________________________________________________XXXXXXXXX___
      Uplink  9: ____________________________________________________________________XXXXXXXXX___
      Uplink 10: ____________________________________________________________________XXXXXXXXX___
      Uplink 11: ____________________________________________________________________XXXXXXXXX___
      Uplink 12: _____________________________________________________________________XXXXXXXX___
      Uplink 13: _____________________________________________________________________XXXXXXXX___
      Uplink 14: _______________________________________________________________________XXXXXX___
      Uplink 15: _______________________________________________________________________XXXXXX___
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 1:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 4:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 5:
      Optimal Phase: 23
      Window Length: 36
      Eye Window: __XXXX__________________________________
    Uplink 6:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 7:
      Optimal Phase: 17
      Window Length: 34
      Eye Window: X__________________________________XXXXX
    Uplink 8:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 9:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 10:
      Optimal Phase: 8
      Window Length: 34
      Eye Window: __________________________XXXXXX________
    Uplink 11:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 12:
      Optimal Phase: 9
      Window Length: 34
      Eye Window: ___________________________XXXXXX_______
    Uplink 13:
      Optimal Phase: 12
      Window Length: 36
      Eye Window: _______________________________XXXX_____
    Uplink 14:
      Optimal Phase: 11
      Window Length: 36
      Eye Window: ______________________________XXXX______
    Uplink 15:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____

15:25:14:setup_element:INFO:	Performing Elink synchronization
15:25:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:25:14:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:25:14:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
15:25:14:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
15:25:14:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
15:25:14:uplink:INFO:	Enabling uplinks [0, 1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:25:14:ST3_emu:INFO:	Number of chips: 7
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  1  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   1  |   [0]   |  1  |  0  |     [8]      |   [(0, 8), (1, 9)] 
   3  |   [0]   |  1  |  0  |     [10]     |  [(0, 10), (1, 11)]
   4  |   [0]   |  1  |  0  |     [5]      |   [(0, 5), (1, 4)] 
   5  |   [0]   |  1  |  0  |     [12]     |  [(0, 12), (1, 13)]
   6  |   [0]   |  1  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   7  |   [0]   |  1  |  0  |     [14]     |  [(0, 14), (1, 15)]
15:25:15:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
15:25:15:febtest:INFO:	1-0 | XA-000-08-002-000-004-049-01 |  37.7 | 1183.3
15:25:16:febtest:INFO:	8-1 | XA-000-08-002-000-004-149-05 |  44.1 | 1165.6
15:25:16:febtest:INFO:	10-3 | XA-000-08-002-000-004-134-02 |  21.9 | 1247.9
15:25:16:febtest:INFO:	5-4 | XA-000-08-002-000-004-127-04 |  50.4 | 1177.4
15:25:16:febtest:INFO:	12-5 | XA-000-08-002-000-004-141-02 |  31.4 | 1206.9
15:25:17:febtest:INFO:	7-6 | XA-000-08-002-000-004-050-01 |  40.9 | 1189.2
15:25:17:febtest:INFO:	14-7 | XA-000-08-002-000-004-123-04 |  40.9 | 1189.2
15:25:17:ST3_smx:INFO:	Configuring SMX FAST
15:25:19:ST3_smx:INFO:	chip: 1-0 	 44.073563 C 	 1171.483840 mV
15:25:19:ST3_smx:INFO:		Electrons
15:25:19:ST3_smx:INFO:	# loops 0
15:25:21:ST3_smx:INFO:	# loops 1
15:25:22:ST3_smx:INFO:	# loops 2
15:25:24:ST3_smx:INFO:	# loops 3
15:25:26:ST3_smx:INFO:	# loops 4
15:25:28:ST3_smx:INFO:	Total # of broken channels: 0
15:25:28:ST3_smx:INFO:	List of broken channels: []
15:25:28:ST3_smx:INFO:	Total # of broken channels: 0
15:25:28:ST3_smx:INFO:	List of broken channels: []
15:25:28:ST3_smx:INFO:	Configuring SMX FAST
15:25:31:ST3_smx:INFO:	chip: 8-1 	 40.898880 C 	 1183.292940 mV
15:25:31:ST3_smx:INFO:		Electrons
15:25:31:ST3_smx:INFO:	# loops 0
15:25:32:ST3_smx:INFO:	# loops 1
15:25:34:ST3_smx:INFO:	# loops 2
15:25:36:ST3_smx:INFO:	# loops 3
15:25:37:ST3_smx:INFO:	# loops 4
15:25:39:ST3_smx:INFO:	Total # of broken channels: 0
15:25:39:ST3_smx:INFO:	List of broken channels: []
15:25:39:ST3_smx:INFO:	Total # of broken channels: 18
15:25:39:ST3_smx:INFO:	List of broken channels: [5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 43, 113]
15:25:40:ST3_smx:INFO:	Configuring SMX FAST
15:25:42:ST3_smx:INFO:	chip: 10-3 	 31.389742 C 	 1218.600960 mV
15:25:42:ST3_smx:INFO:		Electrons
15:25:42:ST3_smx:INFO:	# loops 0
15:25:44:ST3_smx:INFO:	# loops 1
15:25:46:ST3_smx:INFO:	# loops 2
15:25:47:ST3_smx:INFO:	# loops 3
15:25:49:ST3_smx:INFO:	# loops 4
15:25:51:ST3_smx:INFO:	Total # of broken channels: 0
15:25:51:ST3_smx:INFO:	List of broken channels: []
15:25:51:ST3_smx:INFO:	Total # of broken channels: 16
15:25:51:ST3_smx:INFO:	List of broken channels: [47, 49, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 79, 85]
15:25:52:ST3_smx:INFO:	Configuring SMX FAST
15:25:55:ST3_smx:INFO:	chip: 5-4 	 59.984250 C 	 1147.806000 mV
15:25:55:ST3_smx:INFO:		Electrons
15:25:55:ST3_smx:INFO:	# loops 0
15:25:57:ST3_smx:INFO:	# loops 1
15:25:59:ST3_smx:INFO:	# loops 2
15:26:01:ST3_smx:INFO:	# loops 3
15:26:03:ST3_smx:INFO:	# loops 4
15:26:05:ST3_smx:INFO:	Total # of broken channels: 0
15:26:05:ST3_smx:INFO:	List of broken channels: []
15:26:05:ST3_smx:INFO:	Total # of broken channels: 0
15:26:05:ST3_smx:INFO:	List of broken channels: []
15:26:05:ST3_smx:INFO:	Configuring SMX FAST
15:26:08:ST3_smx:INFO:	chip: 12-5 	 37.726682 C 	 1200.969315 mV
15:26:08:ST3_smx:INFO:		Electrons
15:26:08:ST3_smx:INFO:	# loops 0
15:26:09:ST3_smx:INFO:	# loops 1
15:26:11:ST3_smx:INFO:	# loops 2
15:26:13:ST3_smx:INFO:	# loops 3
15:26:15:ST3_smx:INFO:	# loops 4
15:26:16:ST3_smx:INFO:	Total # of broken channels: 1
15:26:16:ST3_smx:INFO:	List of broken channels: [102]
15:26:16:ST3_smx:INFO:	Total # of broken channels: 21
15:26:16:ST3_smx:INFO:	List of broken channels: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 33, 35, 37, 39, 87, 102]
15:26:17:ST3_smx:INFO:	Configuring SMX FAST
15:26:20:ST3_smx:INFO:	chip: 7-6 	 44.073563 C 	 1177.390875 mV
15:26:20:ST3_smx:INFO:		Electrons
15:26:20:ST3_smx:INFO:	# loops 0
15:26:21:ST3_smx:INFO:	# loops 1
15:26:23:ST3_smx:INFO:	# loops 2
15:26:25:ST3_smx:INFO:	# loops 3
15:26:27:ST3_smx:INFO:	# loops 4
15:26:29:ST3_smx:INFO:	Total # of broken channels: 0
15:26:29:ST3_smx:INFO:	List of broken channels: []
15:26:29:ST3_smx:INFO:	Total # of broken channels: 24
15:26:29:ST3_smx:INFO:	List of broken channels: [5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 29, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 125, 127]
15:26:29:ST3_smx:INFO:	Configuring SMX FAST
15:26:31:ST3_smx:INFO:	chip: 14-7 	 34.556970 C 	 1212.728715 mV
15:26:31:ST3_smx:INFO:		Electrons
15:26:31:ST3_smx:INFO:	# loops 0
15:26:33:ST3_smx:INFO:	# loops 1
15:26:35:ST3_smx:INFO:	# loops 2
15:26:37:ST3_smx:INFO:	# loops 3
15:26:38:ST3_smx:INFO:	# loops 4
15:26:40:ST3_smx:INFO:	Total # of broken channels: 0
15:26:40:ST3_smx:INFO:	List of broken channels: []
15:26:40:ST3_smx:INFO:	Total # of broken channels: 6
15:26:40:ST3_smx:INFO:	List of broken channels: [3, 5, 7, 9, 13, 17]
15:26:41:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
15:26:41:febtest:INFO:	1-0 | XA-000-08-002-000-004-049-01 |  44.1 | 1171.5
15:26:41:febtest:INFO:	8-1 | XA-000-08-002-000-004-149-05 |  40.9 | 1183.3
15:26:42:febtest:INFO:	10-3 | XA-000-08-002-000-004-134-02 |  31.4 | 1218.6
15:26:42:febtest:INFO:	5-4 | XA-000-08-002-000-004-127-04 |  60.0 | 1153.7
15:26:42:febtest:INFO:	12-5 | XA-000-08-002-000-004-141-02 |  37.7 | 1201.0
15:26:42:febtest:INFO:	7-6 | XA-000-08-002-000-004-050-01 |  44.1 | 1177.4
15:26:43:febtest:INFO:	14-7 | XA-000-08-002-000-004-123-04 |  34.6 | 1212.7
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2024_02_01-15_25_02
OPERATOR  : Robert V.; Irakli K.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 1046
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.451', '0.0002', '1.850', '0.0000', '2.450', '1.4880', '1.850', '2.0760']
VI_after__Init : ['0', '0', '0', '0', '0', '0']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
15:27:14:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_1046/TestDate_2024_02_01-15_25_02/