12:32:01:ST3_hmp4040:INFO:	
12:32:02:febtest:INFO:	FEB8.2 selected
12:33:49:ST3_Shared:INFO:	Listo of operators:Oleksandr S.; 
12:33:56:febtest:INFO:	FEB 8-2 A @ GSI
12:34:08:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
12:34:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:34:10:ST3_Shared:INFO:	-----------------------FEB-Microcable-----------------------
12:34:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:34:10:febtest:INFO:	Tsting FEB with SN 1047
12:34:11:smx_tester:INFO:	Scanning setup
12:34:11:elinks:INFO:	Disabling clock on downlink 0
12:34:11:elinks:INFO:	Disabling clock on downlink 1
12:34:11:elinks:INFO:	Disabling clock on downlink 2
12:34:11:elinks:INFO:	Disabling clock on downlink 3
12:34:11:elinks:INFO:	Disabling clock on downlink 4
12:34:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:34:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
12:34:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:34:11:elinks:INFO:	Disabling clock on downlink 0
12:34:11:elinks:INFO:	Disabling clock on downlink 1
12:34:11:elinks:INFO:	Disabling clock on downlink 2
12:34:11:elinks:INFO:	Disabling clock on downlink 3
12:34:11:elinks:INFO:	Disabling clock on downlink 4
12:34:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:34:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:34:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:34:12:elinks:INFO:	Disabling clock on downlink 0
12:34:12:elinks:INFO:	Disabling clock on downlink 1
12:34:12:elinks:INFO:	Disabling clock on downlink 2
12:34:12:elinks:INFO:	Disabling clock on downlink 3
12:34:12:elinks:INFO:	Disabling clock on downlink 4
12:34:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:34:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:34:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:34:12:elinks:INFO:	Disabling clock on downlink 0
12:34:12:elinks:INFO:	Disabling clock on downlink 1
12:34:12:elinks:INFO:	Disabling clock on downlink 2
12:34:12:elinks:INFO:	Disabling clock on downlink 3
12:34:12:elinks:INFO:	Disabling clock on downlink 4
12:34:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:34:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 24
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 25
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 26
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 27
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 28
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 29
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 30
12:34:12:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 31
12:34:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:34:12:elinks:INFO:	Disabling clock on downlink 0
12:34:12:elinks:INFO:	Disabling clock on downlink 1
12:34:12:elinks:INFO:	Disabling clock on downlink 2
12:34:12:elinks:INFO:	Disabling clock on downlink 3
12:34:12:elinks:INFO:	Disabling clock on downlink 4
12:34:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:34:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
12:34:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:34:12:setup_element:INFO:	Scanning clock phase
12:34:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:34:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
12:34:12:setup_element:INFO:	Clock phase scan results for group 0, downlink 3
12:34:12:setup_element:INFO:	Eye window for uplink 24: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
12:34:12:setup_element:INFO:	Eye window for uplink 25: __________________________________________________________________XXXXXXX_______
Clock Delay: 29
12:34:12:setup_element:INFO:	Eye window for uplink 26: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
12:34:12:setup_element:INFO:	Eye window for uplink 27: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
12:34:12:setup_element:INFO:	Eye window for uplink 28: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
12:34:12:setup_element:INFO:	Eye window for uplink 29: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
12:34:12:setup_element:INFO:	Eye window for uplink 30: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
12:34:12:setup_element:INFO:	Eye window for uplink 31: ___________________________________________________________________XXXXXXX______
Clock Delay: 30
12:34:12:setup_element:INFO:	Setting the clock phase to 29 for group 0, downlink 3
12:34:12:setup_element:INFO:	Scanning data phases
12:34:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:34:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
12:34:18:setup_element:INFO:	Data phase scan results for group 0, downlink 3
12:34:18:setup_element:INFO:	Eye window for uplink 24: XXXX___________________________________X
Data delay found: 21
12:34:18:setup_element:INFO:	Eye window for uplink 25: ___XXXX_________________________________
Data delay found: 24
12:34:18:setup_element:INFO:	Eye window for uplink 26: XXXX__________________________________XX
Data delay found: 20
12:34:18:setup_element:INFO:	Eye window for uplink 27: __XXXXX_________________________________
Data delay found: 24
12:34:18:setup_element:INFO:	Eye window for uplink 28: XXXXX___________________________________
Data delay found: 22
12:34:18:setup_element:INFO:	Eye window for uplink 29: ___XXXX_________________________________
Data delay found: 24
12:34:18:setup_element:INFO:	Eye window for uplink 30: __XXXX__________________________________
Data delay found: 23
12:34:18:setup_element:INFO:	Eye window for uplink 31: XXXXX_________________________________XX
Data delay found: 21
12:34:18:setup_element:INFO:	Setting the data phase to 21 for uplink 24
12:34:18:setup_element:INFO:	Setting the data phase to 24 for uplink 25
12:34:18:setup_element:INFO:	Setting the data phase to 20 for uplink 26
12:34:18:setup_element:INFO:	Setting the data phase to 24 for uplink 27
12:34:18:setup_element:INFO:	Setting the data phase to 22 for uplink 28
12:34:18:setup_element:INFO:	Setting the data phase to 24 for uplink 29
12:34:18:setup_element:INFO:	Setting the data phase to 23 for uplink 30
12:34:18:setup_element:INFO:	Setting the data phase to 21 for uplink 31
12:34:18:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 3
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 29
    Window Length: 72
    Eye Windows:
      Uplink 24: __________________________________________________________________XXXXXXX_______
      Uplink 25: __________________________________________________________________XXXXXXX_______
      Uplink 26: __________________________________________________________________XXXXXXXX______
      Uplink 27: __________________________________________________________________XXXXXXXX______
      Uplink 28: __________________________________________________________________XXXXXXXX______
      Uplink 29: __________________________________________________________________XXXXXXXX______
      Uplink 30: ___________________________________________________________________XXXXXXX______
      Uplink 31: ___________________________________________________________________XXXXXXX______
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 25:
      Optimal Phase: 24
      Window Length: 36
      Eye Window: ___XXXX_________________________________
    Uplink 26:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 27:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 28:
      Optimal Phase: 22
      Window Length: 35
      Eye Window: XXXXX___________________________________
    Uplink 29:
      Optimal Phase: 24
      Window Length: 36
      Eye Window: ___XXXX_________________________________
    Uplink 30:
      Optimal Phase: 23
      Window Length: 36
      Eye Window: __XXXX__________________________________
    Uplink 31:
      Optimal Phase: 21
      Window Length: 33
      Eye Window: XXXXX_________________________________XX
]
12:34:18:setup_element:INFO:	Beginning SMX ASICs map scan
12:34:18:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:34:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
12:34:18:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [3]
12:34:18:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [3]
12:34:18:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
12:34:18:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 24
12:34:18:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 25
12:34:18:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 26
12:34:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 27
12:34:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 28
12:34:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 29
12:34:19:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 30
12:34:19:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 31
12:34:21:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 3
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
  Clock Phase Characteristic:
    Optimal Phase: 29
    Window Length: 72
    Eye Windows:
      Uplink 24: __________________________________________________________________XXXXXXX_______
      Uplink 25: __________________________________________________________________XXXXXXX_______
      Uplink 26: __________________________________________________________________XXXXXXXX______
      Uplink 27: __________________________________________________________________XXXXXXXX______
      Uplink 28: __________________________________________________________________XXXXXXXX______
      Uplink 29: __________________________________________________________________XXXXXXXX______
      Uplink 30: ___________________________________________________________________XXXXXXX______
      Uplink 31: ___________________________________________________________________XXXXXXX______
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 25:
      Optimal Phase: 24
      Window Length: 36
      Eye Window: ___XXXX_________________________________
    Uplink 26:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 27:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 28:
      Optimal Phase: 22
      Window Length: 35
      Eye Window: XXXXX___________________________________
    Uplink 29:
      Optimal Phase: 24
      Window Length: 36
      Eye Window: ___XXXX_________________________________
    Uplink 30:
      Optimal Phase: 23
      Window Length: 36
      Eye Window: __XXXX__________________________________
    Uplink 31:
      Optimal Phase: 21
      Window Length: 33
      Eye Window: XXXXX_________________________________XX

12:34:21:setup_element:INFO:	Performing Elink synchronization
12:34:21:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:34:21:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
12:34:21:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [3]
12:34:21:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [3]
12:34:21:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 3
12:34:21:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
12:34:21:ST3_emu:INFO:	Number of chips: 4
12:34:21:ST3_emu:INFO:	Chip address:  	0x1
12:34:21:ST3_emu:INFO:	Chip address:  	0x3
12:34:21:ST3_emu:INFO:	Chip address:  	0x5
12:34:21:ST3_emu:INFO:	Chip address:  	0x7
12:34:22:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
12:34:22:febtest:INFO:	0-1 | XA-000-08-002-000-005-111-14 |  18.7 | 1212.7
12:34:22:febtest:INFO:	0-3 | XA-000-08-002-000-005-109-14 |  28.2 | 1177.4
12:34:22:febtest:INFO:	0-5 | XA-000-08-002-000-005-070-00 |   9.3 | 1253.7
12:34:23:febtest:INFO:	0-7 | XA-000-08-002-000-005-059-12 |  31.4 | 1183.3
12:34:23:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
12:34:26:ST3_smx:INFO:	chip: 0-1 	 21.902970 C 	 1189.190035 mV
12:34:26:ST3_smx:INFO:	# loops 0
12:34:28:ST3_smx:INFO:	# loops 1
12:34:29:ST3_smx:INFO:	# loops 2
12:34:31:ST3_smx:INFO:	# loops 3
12:34:32:ST3_smx:INFO:	# loops 4
12:34:34:ST3_smx:INFO:	Total # of broken channels: 0
12:34:34:ST3_smx:INFO:	List of broken channels: []
12:34:34:ST3_smx:INFO:	Total # of broken channels: 0
12:34:34:ST3_smx:INFO:	List of broken channels: []
12:34:35:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
12:34:38:ST3_smx:INFO:	chip: 0-3 	 25.062742 C 	 1177.390875 mV
12:34:38:ST3_smx:INFO:	# loops 0
12:34:40:ST3_smx:INFO:	# loops 1
12:34:41:ST3_smx:INFO:	# loops 2
12:34:43:ST3_smx:INFO:	# loops 3
12:34:45:ST3_smx:INFO:	# loops 4
12:34:46:ST3_smx:INFO:	Total # of broken channels: 0
12:34:46:ST3_smx:INFO:	List of broken channels: []
12:34:46:ST3_smx:INFO:	Total # of broken channels: 0
12:34:46:ST3_smx:INFO:	List of broken channels: []
12:34:47:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
12:34:50:ST3_smx:INFO:	chip: 0-5 	 15.590880 C 	 1218.600960 mV
12:34:50:ST3_smx:INFO:	# loops 0
12:34:52:ST3_smx:INFO:	# loops 1
12:34:53:ST3_smx:INFO:	# loops 2
12:34:55:ST3_smx:INFO:	# loops 3
12:34:56:ST3_smx:INFO:	# loops 4
12:34:58:ST3_smx:INFO:	Total # of broken channels: 0
12:34:58:ST3_smx:INFO:	List of broken channels: []
12:34:58:ST3_smx:INFO:	Total # of broken channels: 0
12:34:58:ST3_smx:INFO:	List of broken channels: []
12:34:58:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
12:35:02:ST3_smx:INFO:	chip: 0-7 	 28.225000 C 	 1183.292940 mV
12:35:02:ST3_smx:INFO:	# loops 0
12:35:03:ST3_smx:INFO:	# loops 1
12:35:05:ST3_smx:INFO:	# loops 2
12:35:06:ST3_smx:INFO:	# loops 3
12:35:08:ST3_smx:INFO:	# loops 4
12:35:09:ST3_smx:INFO:	Total # of broken channels: 0
12:35:09:ST3_smx:INFO:	List of broken channels: []
12:35:09:ST3_smx:INFO:	Total # of broken channels: 0
12:35:09:ST3_smx:INFO:	List of broken channels: []
12:35:10:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
12:35:10:febtest:INFO:	0-1 | XA-000-08-002-000-005-111-14 |  21.9 | 1183.3
12:35:11:febtest:INFO:	0-3 | XA-000-08-002-000-005-109-14 |  25.1 | 1171.5
12:35:11:febtest:INFO:	0-5 | XA-000-08-002-000-005-070-00 |  18.7 | 1212.7
12:35:11:febtest:INFO:	0-7 | XA-000-08-002-000-005-059-12 |  28.2 | 1183.3
12:35:13:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_1047/TestDate_2023_11_13-12_34_10/