13:11:46:ST3_hmp4040:INFO:	HAMEG,HMP2030,017836163,HW50010002/SW2.30
13:11:46:febtest:INFO:	FEB8.2 selected
13:13:26:febtest:INFO:	FEB 8-2 A @ GSI
13:13:43:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
13:14:12:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:14:12:ST3_Shared:INFO:	-----------------------FEB-Microcable-----------------------
13:14:12:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:14:12:febtest:INFO:	Tsting FEB with SN 1066
13:14:14:smx_tester:INFO:	Scanning setup
13:14:14:elinks:INFO:	Disabling clock on downlink 0
13:14:14:elinks:INFO:	Disabling clock on downlink 1
13:14:14:elinks:INFO:	Disabling clock on downlink 2
13:14:14:elinks:INFO:	Disabling clock on downlink 3
13:14:14:elinks:INFO:	Disabling clock on downlink 4
13:14:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:14:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:14:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:14:14:elinks:INFO:	Disabling clock on downlink 0
13:14:14:elinks:INFO:	Disabling clock on downlink 1
13:14:14:elinks:INFO:	Disabling clock on downlink 2
13:14:14:elinks:INFO:	Disabling clock on downlink 3
13:14:14:elinks:INFO:	Disabling clock on downlink 4
13:14:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:14:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:14:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:14:14:elinks:INFO:	Disabling clock on downlink 0
13:14:14:elinks:INFO:	Disabling clock on downlink 1
13:14:14:elinks:INFO:	Disabling clock on downlink 2
13:14:14:elinks:INFO:	Disabling clock on downlink 3
13:14:14:elinks:INFO:	Disabling clock on downlink 4
13:14:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:14:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:14:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:14:14:elinks:INFO:	Disabling clock on downlink 0
13:14:14:elinks:INFO:	Disabling clock on downlink 1
13:14:14:elinks:INFO:	Disabling clock on downlink 2
13:14:14:elinks:INFO:	Disabling clock on downlink 3
13:14:14:elinks:INFO:	Disabling clock on downlink 4
13:14:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:14:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 24
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 25
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 26
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 27
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 28
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 29
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 30
13:14:14:setup_element:INFO:	SOS detected for group 0, downlink 3, uplink 31
13:14:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:14:14:elinks:INFO:	Disabling clock on downlink 0
13:14:14:elinks:INFO:	Disabling clock on downlink 1
13:14:14:elinks:INFO:	Disabling clock on downlink 2
13:14:14:elinks:INFO:	Disabling clock on downlink 3
13:14:14:elinks:INFO:	Disabling clock on downlink 4
13:14:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:14:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:14:15:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:14:15:setup_element:INFO:	Scanning clock phase
13:14:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:14:15:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:14:15:setup_element:INFO:	Clock phase scan results for group 0, downlink 3
13:14:15:setup_element:INFO:	Eye window for uplink 24: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
13:14:15:setup_element:INFO:	Eye window for uplink 25: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
13:14:15:setup_element:INFO:	Eye window for uplink 26: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
13:14:15:setup_element:INFO:	Eye window for uplink 27: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
13:14:15:setup_element:INFO:	Eye window for uplink 28: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:14:15:setup_element:INFO:	Eye window for uplink 29: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:14:15:setup_element:INFO:	Eye window for uplink 30: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:14:15:setup_element:INFO:	Eye window for uplink 31: __________________________________________________________________XXXXXXXX______
Clock Delay: 29
13:14:15:setup_element:INFO:	Setting the clock phase to 29 for group 0, downlink 3
13:14:15:setup_element:INFO:	Scanning data phases
13:14:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:14:15:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:14:20:setup_element:INFO:	Data phase scan results for group 0, downlink 3
13:14:20:setup_element:INFO:	Eye window for uplink 24: XX__________________________________XXXX
Data delay found: 18
13:14:20:setup_element:INFO:	Eye window for uplink 25: XXXX____________________________________
Data delay found: 21
13:14:20:setup_element:INFO:	Eye window for uplink 26: XXX__________________________________XXX
Data delay found: 19
13:14:20:setup_element:INFO:	Eye window for uplink 27: __XXXXX_________________________________
Data delay found: 24
13:14:20:setup_element:INFO:	Eye window for uplink 28: XXXXX___________________________________
Data delay found: 22
13:14:20:setup_element:INFO:	Eye window for uplink 29: __XXXXX_________________________________
Data delay found: 24
13:14:20:setup_element:INFO:	Eye window for uplink 30: XXXXX__________________________________X
Data delay found: 21
13:14:20:setup_element:INFO:	Eye window for uplink 31: XXX__________________________________XXX
Data delay found: 19
13:14:20:setup_element:INFO:	Setting the data phase to 18 for uplink 24
13:14:20:setup_element:INFO:	Setting the data phase to 21 for uplink 25
13:14:20:setup_element:INFO:	Setting the data phase to 19 for uplink 26
13:14:20:setup_element:INFO:	Setting the data phase to 24 for uplink 27
13:14:20:setup_element:INFO:	Setting the data phase to 22 for uplink 28
13:14:20:setup_element:INFO:	Setting the data phase to 24 for uplink 29
13:14:20:setup_element:INFO:	Setting the data phase to 21 for uplink 30
13:14:20:setup_element:INFO:	Setting the data phase to 19 for uplink 31
13:14:20:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 3
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 29
    Window Length: 71
    Eye Windows:
      Uplink 24: _________________________________________________________________XXXXXXXX_______
      Uplink 25: _________________________________________________________________XXXXXXXX_______
      Uplink 26: _________________________________________________________________XXXXXXXXX______
      Uplink 27: _________________________________________________________________XXXXXXXXX______
      Uplink 28: __________________________________________________________________XXXXXXXX______
      Uplink 29: __________________________________________________________________XXXXXXXX______
      Uplink 30: __________________________________________________________________XXXXXXXX______
      Uplink 31: __________________________________________________________________XXXXXXXX______
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 25:
      Optimal Phase: 21
      Window Length: 36
      Eye Window: XXXX____________________________________
    Uplink 26:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 27:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 28:
      Optimal Phase: 22
      Window Length: 35
      Eye Window: XXXXX___________________________________
    Uplink 29:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 30:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 31:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
]
13:14:20:setup_element:INFO:	Beginning SMX ASICs map scan
13:14:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:14:20:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:14:20:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [3]
13:14:20:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [3]
13:14:20:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
13:14:21:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 24
13:14:21:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 25
13:14:21:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 26
13:14:21:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 27
13:14:21:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 28
13:14:21:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 29
13:14:22:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 30
13:14:22:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 31
13:14:23:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 3
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
  Clock Phase Characteristic:
    Optimal Phase: 29
    Window Length: 71
    Eye Windows:
      Uplink 24: _________________________________________________________________XXXXXXXX_______
      Uplink 25: _________________________________________________________________XXXXXXXX_______
      Uplink 26: _________________________________________________________________XXXXXXXXX______
      Uplink 27: _________________________________________________________________XXXXXXXXX______
      Uplink 28: __________________________________________________________________XXXXXXXX______
      Uplink 29: __________________________________________________________________XXXXXXXX______
      Uplink 30: __________________________________________________________________XXXXXXXX______
      Uplink 31: __________________________________________________________________XXXXXXXX______
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 25:
      Optimal Phase: 21
      Window Length: 36
      Eye Window: XXXX____________________________________
    Uplink 26:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX
    Uplink 27:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 28:
      Optimal Phase: 22
      Window Length: 35
      Eye Window: XXXXX___________________________________
    Uplink 29:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 30:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: XXXXX__________________________________X
    Uplink 31:
      Optimal Phase: 19
      Window Length: 34
      Eye Window: XXX__________________________________XXX

13:14:23:setup_element:INFO:	Performing Elink synchronization
13:14:23:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:14:23:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [3]
13:14:23:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [3]
13:14:23:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [3]
13:14:23:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 3
13:14:23:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
13:14:23:ST3_emu:INFO:	Number of chips: 4
13:14:23:ST3_emu:INFO:	Chip address:  	0x1
13:14:23:ST3_emu:INFO:	Chip address:  	0x3
13:14:23:ST3_emu:INFO:	Chip address:  	0x5
13:14:23:ST3_emu:INFO:	Chip address:  	0x7
13:14:24:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:14:24:febtest:INFO:	0-1 | XA-000-08-002-000-001-064-06 |  25.1 | 1206.9
13:14:25:febtest:INFO:	0-3 | XA-000-08-002-000-001-049-10 |  47.3 | 1141.9
13:14:25:febtest:INFO:	0-5 | XA-000-08-002-000-001-054-10 |  21.9 | 1224.5
13:14:25:febtest:INFO:	0-7 | XA-000-08-002-000-001-048-10 |  28.2 | 1195.1
13:14:25:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:14:29:ST3_smx:INFO:	chip: 0-1 	 21.902970 C 	 1200.969315 mV
13:14:29:ST3_smx:INFO:	# loops 0
13:14:31:ST3_smx:INFO:	# loops 1
13:14:33:ST3_smx:INFO:	# loops 2
13:14:34:ST3_smx:INFO:	# loops 3
13:14:36:ST3_smx:INFO:	# loops 4
13:14:38:ST3_smx:INFO:	Total # of broken channels: 0
13:14:38:ST3_smx:INFO:	List of broken channels: []
13:14:38:ST3_smx:INFO:	Total # of broken channels: 0
13:14:38:ST3_smx:INFO:	List of broken channels: []
13:14:38:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:14:42:ST3_smx:INFO:	chip: 0-3 	 44.073563 C 	 1129.995435 mV
13:14:42:ST3_smx:INFO:	# loops 0
13:14:44:ST3_smx:INFO:	# loops 1
13:14:45:ST3_smx:INFO:	# loops 2
13:14:47:ST3_smx:INFO:	# loops 3
13:14:49:ST3_smx:INFO:	# loops 4
13:14:50:ST3_smx:INFO:	Total # of broken channels: 0
13:14:50:ST3_smx:INFO:	List of broken channels: []
13:14:50:ST3_smx:INFO:	Total # of broken channels: 0
13:14:50:ST3_smx:INFO:	List of broken channels: []
13:14:51:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:14:55:ST3_smx:INFO:	chip: 0-5 	 31.389742 C 	 1165.571835 mV
13:14:55:ST3_smx:INFO:	# loops 0
13:14:56:ST3_smx:INFO:	# loops 1
13:14:58:ST3_smx:INFO:	# loops 2
13:15:00:ST3_smx:INFO:	# loops 3
13:15:01:ST3_smx:INFO:	# loops 4
13:15:03:ST3_smx:INFO:	Total # of broken channels: 0
13:15:03:ST3_smx:INFO:	List of broken channels: []
13:15:03:ST3_smx:INFO:	Total # of broken channels: 0
13:15:03:ST3_smx:INFO:	List of broken channels: []
13:15:04:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:15:07:ST3_smx:INFO:	chip: 0-7 	 31.389742 C 	 1177.390875 mV
13:15:07:ST3_smx:INFO:	# loops 0
13:15:09:ST3_smx:INFO:	# loops 1
13:15:11:ST3_smx:INFO:	# loops 2
13:15:12:ST3_smx:INFO:	# loops 3
13:15:14:ST3_smx:INFO:	# loops 4
13:15:15:ST3_smx:INFO:	Total # of broken channels: 0
13:15:15:ST3_smx:INFO:	List of broken channels: []
13:15:15:ST3_smx:INFO:	Total # of broken channels: 0
13:15:15:ST3_smx:INFO:	List of broken channels: []
13:15:16:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:15:16:febtest:INFO:	0-1 | XA-000-08-002-000-001-064-06 |  21.9 | 1189.2
13:15:16:febtest:INFO:	0-3 | XA-000-08-002-000-001-049-10 |  44.1 | 1124.0
13:15:17:febtest:INFO:	0-5 | XA-000-08-002-000-001-054-10 |  34.6 | 1165.6
13:15:17:febtest:INFO:	0-7 | XA-000-08-002-000-001-048-10 |  31.4 | 1177.4
13:15:27:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_1066/TestDate_2023_10_19-13_14_12/