FEB_1067 14.11.23 13:42:54
Info
13:42:20:ST3_Shared:INFO: Listo of operators:Robert V.;
13:42:21:ST3_Shared:INFO: Listo of operators:Alois Alzheimer
13:42:22:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
13:42:31:febtest:INFO: FEB 8-2 A @ GSI
13:42:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:42:35:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
13:42:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:42:35:febtest:INFO: Tsting FEB with SN 1067
13:42:36:smx_tester:INFO: Scanning setup
13:42:36:elinks:INFO: Disabling clock on downlink 0
13:42:36:elinks:INFO: Disabling clock on downlink 1
13:42:36:elinks:INFO: Disabling clock on downlink 2
13:42:36:elinks:INFO: Disabling clock on downlink 3
13:42:36:elinks:INFO: Disabling clock on downlink 4
13:42:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:42:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:36:elinks:INFO: Disabling clock on downlink 0
13:42:36:elinks:INFO: Disabling clock on downlink 1
13:42:36:elinks:INFO: Disabling clock on downlink 2
13:42:36:elinks:INFO: Disabling clock on downlink 3
13:42:36:elinks:INFO: Disabling clock on downlink 4
13:42:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:42:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:36:elinks:INFO: Disabling clock on downlink 0
13:42:36:elinks:INFO: Disabling clock on downlink 1
13:42:36:elinks:INFO: Disabling clock on downlink 2
13:42:36:elinks:INFO: Disabling clock on downlink 3
13:42:36:elinks:INFO: Disabling clock on downlink 4
13:42:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:42:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:36:elinks:INFO: Disabling clock on downlink 0
13:42:36:elinks:INFO: Disabling clock on downlink 1
13:42:36:elinks:INFO: Disabling clock on downlink 2
13:42:36:elinks:INFO: Disabling clock on downlink 3
13:42:37:elinks:INFO: Disabling clock on downlink 4
13:42:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:42:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:37:elinks:INFO: Disabling clock on downlink 0
13:42:37:elinks:INFO: Disabling clock on downlink 1
13:42:37:elinks:INFO: Disabling clock on downlink 2
13:42:37:elinks:INFO: Disabling clock on downlink 3
13:42:37:elinks:INFO: Disabling clock on downlink 4
13:42:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:42:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:37:ST3_emu:ERROR: # of setup_elements is ZERO!
13:42:54:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:42:54:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
13:42:54:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:42:55:febtest:INFO: Tsting FEB with SN 1067
13:42:56:smx_tester:INFO: Scanning setup
13:42:56:elinks:INFO: Disabling clock on downlink 0
13:42:56:elinks:INFO: Disabling clock on downlink 1
13:42:56:elinks:INFO: Disabling clock on downlink 2
13:42:56:elinks:INFO: Disabling clock on downlink 3
13:42:56:elinks:INFO: Disabling clock on downlink 4
13:42:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:42:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:56:elinks:INFO: Disabling clock on downlink 0
13:42:56:elinks:INFO: Disabling clock on downlink 1
13:42:56:elinks:INFO: Disabling clock on downlink 2
13:42:56:elinks:INFO: Disabling clock on downlink 3
13:42:56:elinks:INFO: Disabling clock on downlink 4
13:42:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
13:42:56:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
13:42:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:56:elinks:INFO: Disabling clock on downlink 0
13:42:56:elinks:INFO: Disabling clock on downlink 1
13:42:56:elinks:INFO: Disabling clock on downlink 2
13:42:56:elinks:INFO: Disabling clock on downlink 3
13:42:56:elinks:INFO: Disabling clock on downlink 4
13:42:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:42:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:56:elinks:INFO: Disabling clock on downlink 0
13:42:56:elinks:INFO: Disabling clock on downlink 1
13:42:56:elinks:INFO: Disabling clock on downlink 2
13:42:56:elinks:INFO: Disabling clock on downlink 3
13:42:56:elinks:INFO: Disabling clock on downlink 4
13:42:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:42:56:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:56:elinks:INFO: Disabling clock on downlink 0
13:42:56:elinks:INFO: Disabling clock on downlink 1
13:42:56:elinks:INFO: Disabling clock on downlink 2
13:42:56:elinks:INFO: Disabling clock on downlink 3
13:42:56:elinks:INFO: Disabling clock on downlink 4
13:42:56:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:42:56:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:42:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:42:57:setup_element:INFO: Scanning clock phase
13:42:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:42:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:42:57:setup_element:INFO: Clock phase scan results for group 0, downlink 1
13:42:57:setup_element:INFO: Eye window for uplink 0 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 1 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 4 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:42:57:setup_element:INFO: Eye window for uplink 5 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:42:57:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
13:42:57:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
13:42:57:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 12: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 13: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 14: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:42:57:setup_element:INFO: Eye window for uplink 15: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:42:57:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
13:42:57:setup_element:INFO: Scanning data phases
13:42:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:42:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:43:02:setup_element:INFO: Data phase scan results for group 0, downlink 1
13:43:02:setup_element:INFO: Eye window for uplink 0 : __________XXXXXX________________________
Data delay found: 32
13:43:02:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________
Data delay found: 29
13:43:02:setup_element:INFO: Eye window for uplink 2 : _______XXXXX____________________________
Data delay found: 29
13:43:02:setup_element:INFO: Eye window for uplink 3 : _____XXXXX______________________________
Data delay found: 27
13:43:02:setup_element:INFO: Eye window for uplink 4 : ___XXXXX________________________________
Data delay found: 25
13:43:02:setup_element:INFO: Eye window for uplink 5 : XXXX__________________________________XX
Data delay found: 20
13:43:02:setup_element:INFO: Eye window for uplink 6 : XX___________________________________XXX
Data delay found: 19
13:43:02:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXXX___
Data delay found: 14
13:43:02:setup_element:INFO: Eye window for uplink 8 : __________________________XXXX__________
Data delay found: 7
13:43:02:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
13:43:02:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
13:43:02:setup_element:INFO: Eye window for uplink 11: ______________________________XXXXX_____
Data delay found: 12
13:43:02:setup_element:INFO: Eye window for uplink 12: ___________________________XXXXX________
Data delay found: 9
13:43:02:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
13:43:02:setup_element:INFO: Eye window for uplink 14: ____________________________XXXX________
Data delay found: 9
13:43:02:setup_element:INFO: Eye window for uplink 15: ______________________________XXXXX_____
Data delay found: 12
13:43:02:setup_element:INFO: Setting the data phase to 32 for uplink 0
13:43:02:setup_element:INFO: Setting the data phase to 29 for uplink 1
13:43:02:setup_element:INFO: Setting the data phase to 29 for uplink 2
13:43:02:setup_element:INFO: Setting the data phase to 27 for uplink 3
13:43:02:setup_element:INFO: Setting the data phase to 25 for uplink 4
13:43:02:setup_element:INFO: Setting the data phase to 20 for uplink 5
13:43:02:setup_element:INFO: Setting the data phase to 19 for uplink 6
13:43:02:setup_element:INFO: Setting the data phase to 14 for uplink 7
13:43:02:setup_element:INFO: Setting the data phase to 7 for uplink 8
13:43:02:setup_element:INFO: Setting the data phase to 12 for uplink 9
13:43:02:setup_element:INFO: Setting the data phase to 8 for uplink 10
13:43:02:setup_element:INFO: Setting the data phase to 12 for uplink 11
13:43:02:setup_element:INFO: Setting the data phase to 9 for uplink 12
13:43:02:setup_element:INFO: Setting the data phase to 13 for uplink 13
13:43:02:setup_element:INFO: Setting the data phase to 9 for uplink 14
13:43:02:setup_element:INFO: Setting the data phase to 12 for uplink 15
13:43:02:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXXX
Uplink 1: ________________________________________________________________________XXXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXXXX_
Uplink 9: ______________________________________________________________________XXXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 4:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 15:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
]
13:43:02:setup_element:INFO: Beginning SMX ASICs map scan
13:43:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:43:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:43:02:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:43:02:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:43:02:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:43:02:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
13:43:02:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
13:43:02:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
13:43:02:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
13:43:03:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
13:43:03:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
13:43:03:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
13:43:03:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
13:43:03:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
13:43:03:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
13:43:03:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
13:43:03:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
13:43:03:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
13:43:03:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
13:43:04:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
13:43:04:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
13:43:05:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 70
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXXX
Uplink 1: ________________________________________________________________________XXXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXXXX_
Uplink 9: ______________________________________________________________________XXXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 4:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 15:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
13:43:05:setup_element:INFO: Performing Elink synchronization
13:43:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:43:05:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:43:05:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:43:05:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:43:05:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
13:43:05:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:43:05:ST3_emu:INFO: Number of chips: 8
13:43:05:ST3_emu:INFO: Chip address: 0x0
13:43:05:ST3_emu:INFO: Chip address: 0x1
13:43:05:ST3_emu:INFO: Chip address: 0x2
13:43:05:ST3_emu:INFO: Chip address: 0x3
13:43:05:ST3_emu:INFO: Chip address: 0x4
13:43:05:ST3_emu:INFO: Chip address: 0x5
13:43:05:ST3_emu:INFO: Chip address: 0x6
13:43:05:ST3_emu:INFO: Chip address: 0x7
13:43:06:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:43:06:febtest:INFO: 0-0 | XA-000-08-002-000-000-104-05 | 37.7 | 1177.4
13:43:06:febtest:INFO: 0-1 | XA-000-08-002-000-005-101-14 | 37.7 | 1177.4
13:43:06:febtest:INFO: 0-2 | XA-000-08-002-000-005-105-14 | 28.2 | 1218.6
13:43:07:febtest:INFO: 0-3 | XA-000-08-002-000-005-103-14 | 18.7 | 1247.9
13:43:07:febtest:INFO: 0-4 | XA-000-08-002-000-005-097-14 | 25.1 | 1230.3
13:43:07:febtest:INFO: 0-5 | XA-000-08-002-000-005-102-14 | 47.3 | 1153.7
13:43:07:febtest:INFO: 0-6 | XA-000-08-002-000-000-103-05 | 44.1 | 1165.6
13:43:08:febtest:INFO: 0-7 | XA-000-08-002-001-007-023-09 | 25.1 | 1242.0
13:43:08:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:43:11:ST3_smx:INFO: chip: 0-0 50.430383 C 1124.048640 mV
13:43:11:ST3_smx:INFO: # loops 0
13:43:13:ST3_smx:INFO: # loops 1
13:43:15:ST3_smx:INFO: # loops 2
13:43:16:ST3_smx:INFO: # loops 3
13:43:18:ST3_smx:INFO: # loops 4
13:43:20:ST3_smx:INFO: Total # of broken channels: 0
13:43:20:ST3_smx:INFO: List of broken channels: []
13:43:20:ST3_smx:INFO: Total # of broken channels: 0
13:43:20:ST3_smx:INFO: List of broken channels: []
13:43:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:43:24:ST3_smx:INFO: chip: 0-1 37.726682 C 1171.483840 mV
13:43:24:ST3_smx:INFO: # loops 0
13:43:26:ST3_smx:INFO: # loops 1
13:43:27:ST3_smx:INFO: # loops 2
13:43:29:ST3_smx:INFO: # loops 3
13:43:31:ST3_smx:INFO: # loops 4
13:43:32:ST3_smx:INFO: Total # of broken channels: 0
13:43:32:ST3_smx:INFO: List of broken channels: []
13:43:32:ST3_smx:INFO: Total # of broken channels: 0
13:43:32:ST3_smx:INFO: List of broken channels: []
13:43:33:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:43:37:ST3_smx:INFO: chip: 0-2 34.556970 C 1189.190035 mV
13:43:37:ST3_smx:INFO: # loops 0
13:43:39:ST3_smx:INFO: # loops 1
13:43:40:ST3_smx:INFO: # loops 2
13:43:42:ST3_smx:INFO: # loops 3
13:43:44:ST3_smx:INFO: # loops 4
13:43:45:ST3_smx:INFO: Total # of broken channels: 0
13:43:45:ST3_smx:INFO: List of broken channels: []
13:43:45:ST3_smx:INFO: Total # of broken channels: 1
13:43:45:ST3_smx:INFO: List of broken channels: [28]
13:43:46:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:43:50:ST3_smx:INFO: chip: 0-3 28.225000 C 1206.851500 mV
13:43:50:ST3_smx:INFO: # loops 0
13:43:51:ST3_smx:INFO: # loops 1
13:43:53:ST3_smx:INFO: # loops 2
13:43:55:ST3_smx:INFO: # loops 3
13:43:56:ST3_smx:INFO: # loops 4
13:43:58:ST3_smx:INFO: Total # of broken channels: 0
13:43:58:ST3_smx:INFO: List of broken channels: []
13:43:58:ST3_smx:INFO: Total # of broken channels: 0
13:43:58:ST3_smx:INFO: List of broken channels: []
13:43:59:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:44:02:ST3_smx:INFO: chip: 0-4 34.556970 C 1206.851500 mV
13:44:02:ST3_smx:INFO: # loops 0
13:44:04:ST3_smx:INFO: # loops 1
13:44:06:ST3_smx:INFO: # loops 2
13:44:07:ST3_smx:INFO: # loops 3
13:44:09:ST3_smx:INFO: # loops 4
13:44:11:ST3_smx:INFO: Total # of broken channels: 0
13:44:11:ST3_smx:INFO: List of broken channels: []
13:44:11:ST3_smx:INFO: Total # of broken channels: 0
13:44:11:ST3_smx:INFO: List of broken channels: []
13:44:11:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:44:15:ST3_smx:INFO: chip: 0-5 53.612520 C 1129.995435 mV
13:44:15:ST3_smx:INFO: # loops 0
13:44:17:ST3_smx:INFO: # loops 1
13:44:18:ST3_smx:INFO: # loops 2
13:44:20:ST3_smx:INFO: # loops 3
13:44:22:ST3_smx:INFO: # loops 4
13:44:23:ST3_smx:INFO: Total # of broken channels: 0
13:44:23:ST3_smx:INFO: List of broken channels: []
13:44:23:ST3_smx:INFO: Total # of broken channels: 8
13:44:23:ST3_smx:INFO: List of broken channels: [102, 104, 108, 114, 116, 118, 120, 122]
13:44:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:44:27:ST3_smx:INFO: chip: 0-6 53.612520 C 1129.995435 mV
13:44:27:ST3_smx:INFO: # loops 0
13:44:29:ST3_smx:INFO: # loops 1
13:44:31:ST3_smx:INFO: # loops 2
13:44:32:ST3_smx:INFO: # loops 3
13:44:34:ST3_smx:INFO: # loops 4
13:44:36:ST3_smx:INFO: Total # of broken channels: 0
13:44:36:ST3_smx:INFO: List of broken channels: []
13:44:36:ST3_smx:INFO: Total # of broken channels: 0
13:44:36:ST3_smx:INFO: List of broken channels: []
13:44:37:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
13:44:40:ST3_smx:INFO: chip: 0-7 28.225000 C 1230.330540 mV
13:44:40:ST3_smx:INFO: # loops 0
13:44:42:ST3_smx:INFO: # loops 1
13:44:44:ST3_smx:INFO: # loops 2
13:44:45:ST3_smx:INFO: # loops 3
13:44:47:ST3_smx:INFO: # loops 4
13:44:48:ST3_smx:INFO: Total # of broken channels: 0
13:44:48:ST3_smx:INFO: List of broken channels: []
13:44:48:ST3_smx:INFO: Total # of broken channels: 0
13:44:48:ST3_smx:INFO: List of broken channels: []
13:44:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
13:44:49:febtest:INFO: 0-0 | XA-000-08-002-000-000-104-05 | 53.6 | 1118.1
13:44:50:febtest:INFO: 0-1 | XA-000-08-002-000-005-101-14 | 40.9 | 1165.6
13:44:50:febtest:INFO: 0-2 | XA-000-08-002-000-005-105-14 | 37.7 | 1183.3
13:44:50:febtest:INFO: 0-3 | XA-000-08-002-000-005-103-14 | 31.4 | 1201.0
13:44:50:febtest:INFO: 0-4 | XA-000-08-002-000-005-097-14 | 34.6 | 1201.0
13:44:50:febtest:INFO: 0-5 | XA-000-08-002-000-005-102-14 | 56.8 | 1124.0
13:44:51:febtest:INFO: 0-6 | XA-000-08-002-000-000-103-05 | 56.8 | 1130.0
13:44:51:febtest:INFO: 0-7 | XA-000-08-002-001-007-023-09 | 31.4 | 1230.3
13:44:55:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1067/TestDate_2023_11_14-13_42_54/