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FEB_1076 01.02.24 15:57:41
Info
15:56:55:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,123796,HW50020003/SW2.71
15:57:02:febtest:INFO: FEB 8-2 selected
15:57:02:smx_tester:INFO: Setting Elink clock mode to 160 MHz
15:57:24:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:57:24:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
15:57:24:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:57:24:febtest:INFO: Testing FEB with SN 1076
15:57:41:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:57:41:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
15:57:41:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:57:42:febtest:INFO: Testing FEB with SN 1076
15:57:44:smx_tester:INFO: Scanning setup
15:57:44:elinks:INFO: Disabling clock on downlink 0
15:57:44:elinks:INFO: Disabling clock on downlink 1
15:57:44:elinks:INFO: Disabling clock on downlink 2
15:57:44:elinks:INFO: Disabling clock on downlink 3
15:57:44:elinks:INFO: Disabling clock on downlink 4
15:57:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
15:57:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:44:elinks:INFO: Disabling clock on downlink 0
15:57:44:elinks:INFO: Disabling clock on downlink 1
15:57:44:elinks:INFO: Disabling clock on downlink 2
15:57:44:elinks:INFO: Disabling clock on downlink 3
15:57:44:elinks:INFO: Disabling clock on downlink 4
15:57:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
15:57:44:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
15:57:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:44:elinks:INFO: Disabling clock on downlink 0
15:57:44:elinks:INFO: Disabling clock on downlink 1
15:57:44:elinks:INFO: Disabling clock on downlink 2
15:57:44:elinks:INFO: Disabling clock on downlink 3
15:57:44:elinks:INFO: Disabling clock on downlink 4
15:57:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
15:57:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:44:elinks:INFO: Disabling clock on downlink 0
15:57:44:elinks:INFO: Disabling clock on downlink 1
15:57:44:elinks:INFO: Disabling clock on downlink 2
15:57:44:elinks:INFO: Disabling clock on downlink 3
15:57:44:elinks:INFO: Disabling clock on downlink 4
15:57:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
15:57:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:44:elinks:INFO: Disabling clock on downlink 0
15:57:44:elinks:INFO: Disabling clock on downlink 1
15:57:44:elinks:INFO: Disabling clock on downlink 2
15:57:44:elinks:INFO: Disabling clock on downlink 3
15:57:44:elinks:INFO: Disabling clock on downlink 4
15:57:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
15:57:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
15:57:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
15:57:44:setup_element:INFO: Scanning clock phase
15:57:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:57:45:setup_element:INFO: Clock phase scan results for group 0, downlink 1
15:57:45:setup_element:INFO: Eye window for uplink 0 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:57:45:setup_element:INFO: Eye window for uplink 1 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
15:57:45:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:57:45:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:57:45:setup_element:INFO: Eye window for uplink 4 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:45:setup_element:INFO: Eye window for uplink 5 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:45:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:57:45:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:57:45:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:57:45:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:57:45:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:57:45:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
15:57:45:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:45:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:45:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:45:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
15:57:45:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
15:57:45:setup_element:INFO: Scanning data phases
15:57:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:57:50:setup_element:INFO: Data phase scan results for group 0, downlink 1
15:57:50:setup_element:INFO: Eye window for uplink 0 : ____________XXXXXX______________________
Data delay found: 34
15:57:50:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
15:57:50:setup_element:INFO: Eye window for uplink 2 : _________XXXXX__________________________
Data delay found: 31
15:57:50:setup_element:INFO: Eye window for uplink 3 : ______XXXXX_____________________________
Data delay found: 28
15:57:50:setup_element:INFO: Eye window for uplink 4 : ______XXXXX_____________________________
Data delay found: 28
15:57:50:setup_element:INFO: Eye window for uplink 5 : __XXXXX_________________________________
Data delay found: 24
15:57:50:setup_element:INFO: Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
15:57:50:setup_element:INFO: Eye window for uplink 7 : X_________________________________XXXXX_
Data delay found: 17
15:57:50:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________
Data delay found: 6
15:57:50:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
15:57:50:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
15:57:50:setup_element:INFO: Eye window for uplink 11: ______________________________XXXXX_____
Data delay found: 12
15:57:50:setup_element:INFO: Eye window for uplink 12: ____________________________XXXXX_______
Data delay found: 10
15:57:50:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
15:57:50:setup_element:INFO: Eye window for uplink 14: ____________________________XXXXXX______
Data delay found: 10
15:57:50:setup_element:INFO: Eye window for uplink 15: ______________________________XXXXXX____
Data delay found: 12
15:57:50:setup_element:INFO: Setting the data phase to 34 for uplink 0
15:57:50:setup_element:INFO: Setting the data phase to 30 for uplink 1
15:57:50:setup_element:INFO: Setting the data phase to 31 for uplink 2
15:57:50:setup_element:INFO: Setting the data phase to 28 for uplink 3
15:57:50:setup_element:INFO: Setting the data phase to 28 for uplink 4
15:57:50:setup_element:INFO: Setting the data phase to 24 for uplink 5
15:57:50:setup_element:INFO: Setting the data phase to 20 for uplink 6
15:57:50:setup_element:INFO: Setting the data phase to 17 for uplink 7
15:57:50:setup_element:INFO: Setting the data phase to 6 for uplink 8
15:57:50:setup_element:INFO: Setting the data phase to 12 for uplink 9
15:57:50:setup_element:INFO: Setting the data phase to 8 for uplink 10
15:57:50:setup_element:INFO: Setting the data phase to 12 for uplink 11
15:57:50:setup_element:INFO: Setting the data phase to 10 for uplink 12
15:57:50:setup_element:INFO: Setting the data phase to 13 for uplink 13
15:57:50:setup_element:INFO: Setting the data phase to 10 for uplink 14
15:57:50:setup_element:INFO: Setting the data phase to 12 for uplink 15
15:57:50:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXXX_
Uplink 1: _______________________________________________________________________XXXXXXXX_
Uplink 2: ________________________________________________________________________XXXXXX__
Uplink 3: ________________________________________________________________________XXXXXX__
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXX__
Uplink 7: ________________________________________________________________________XXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: ______________________________________________________________________XXXXXXXX__
Uplink 15: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 15:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
]
15:57:50:setup_element:INFO: Beginning SMX ASICs map scan
15:57:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:50:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:57:50:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:57:50:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:57:50:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:57:50:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
15:57:50:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
15:57:50:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
15:57:50:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
15:57:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
15:57:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
15:57:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
15:57:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
15:57:50:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
15:57:50:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
15:57:51:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
15:57:51:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
15:57:51:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
15:57:51:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
15:57:51:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
15:57:51:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
15:57:52:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXXX_
Uplink 1: _______________________________________________________________________XXXXXXXX_
Uplink 2: ________________________________________________________________________XXXXXX__
Uplink 3: ________________________________________________________________________XXXXXX__
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXX__
Uplink 7: ________________________________________________________________________XXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: ______________________________________________________________________XXXXXXXX__
Uplink 15: ______________________________________________________________________XXXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 15:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
15:57:52:setup_element:INFO: Performing Elink synchronization
15:57:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
15:57:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
15:57:52:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
15:57:52:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
15:57:52:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
15:57:52:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
15:57:52:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
15:57:54:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:57:54:febtest:INFO: 1-0 | XA-000-08-002-000-004-201-07 | 25.1 | 1224.5
15:57:54:febtest:INFO: 8-1 | XA-000-08-002-000-004-130-02 | 37.7 | 1189.2
15:57:55:febtest:INFO: 3-2 | XA-000-08-002-000-004-136-02 | 34.6 | 1195.1
15:57:55:febtest:INFO: 10-3 | XA-000-08-002-000-004-151-05 | 28.2 | 1212.7
15:57:55:febtest:INFO: 5-4 | XA-000-08-002-000-004-137-02 | 28.2 | 1218.6
15:57:55:febtest:INFO: 12-5 | XA-000-08-002-000-004-146-05 | 40.9 | 1183.3
15:57:55:febtest:INFO: 7-6 | XA-000-08-002-000-004-138-02 | 25.1 | 1218.6
15:57:55:febtest:INFO: 14-7 | XA-000-08-002-000-004-154-05 | 37.7 | 1195.1
15:57:56:ST3_smx:INFO: Configuring SMX FAST
15:57:58:ST3_smx:INFO: chip: 1-0 28.225000 C 1218.600960 mV
15:57:58:ST3_smx:INFO: Electrons
15:57:58:ST3_smx:INFO: # loops 0
15:57:59:ST3_smx:INFO: # loops 1
15:58:01:ST3_smx:INFO: # loops 2
15:58:02:ST3_smx:INFO: # loops 3
15:58:04:ST3_smx:INFO: # loops 4
15:58:06:ST3_smx:INFO: Total # of broken channels: 0
15:58:06:ST3_smx:INFO: List of broken channels: []
15:58:06:ST3_smx:INFO: Total # of broken channels: 31
15:58:06:ST3_smx:INFO: List of broken channels: [19, 23, 51, 59, 61, 67, 69, 71, 75, 79, 81, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 113, 115, 117, 119, 121, 123, 125]
15:58:07:ST3_smx:INFO: Configuring SMX FAST
15:58:09:ST3_smx:INFO: chip: 8-1 44.073563 C 1171.483840 mV
15:58:09:ST3_smx:INFO: Electrons
15:58:09:ST3_smx:INFO: # loops 0
15:58:10:ST3_smx:INFO: # loops 1
15:58:12:ST3_smx:INFO: # loops 2
15:58:13:ST3_smx:INFO: # loops 3
15:58:15:ST3_smx:INFO: # loops 4
15:58:17:ST3_smx:INFO: Total # of broken channels: 0
15:58:17:ST3_smx:INFO: List of broken channels: []
15:58:17:ST3_smx:INFO: Total # of broken channels: 0
15:58:17:ST3_smx:INFO: List of broken channels: []
15:58:18:ST3_smx:INFO: Configuring SMX FAST
15:58:19:ST3_smx:INFO: chip: 3-2 34.556970 C 1206.851500 mV
15:58:19:ST3_smx:INFO: Electrons
15:58:19:ST3_smx:INFO: # loops 0
15:58:21:ST3_smx:INFO: # loops 1
15:58:23:ST3_smx:INFO: # loops 2
15:58:24:ST3_smx:INFO: # loops 3
15:58:26:ST3_smx:INFO: # loops 4
15:58:27:ST3_smx:INFO: Total # of broken channels: 0
15:58:27:ST3_smx:INFO: List of broken channels: []
15:58:27:ST3_smx:INFO: Total # of broken channels: 0
15:58:27:ST3_smx:INFO: List of broken channels: []
15:58:28:ST3_smx:INFO: Configuring SMX FAST
15:58:30:ST3_smx:INFO: chip: 10-3 28.225000 C 1218.600960 mV
15:58:30:ST3_smx:INFO: Electrons
15:58:30:ST3_smx:INFO: # loops 0
15:58:32:ST3_smx:INFO: # loops 1
15:58:34:ST3_smx:INFO: # loops 2
15:58:35:ST3_smx:INFO: # loops 3
15:58:37:ST3_smx:INFO: # loops 4
15:58:38:ST3_smx:INFO: Total # of broken channels: 0
15:58:38:ST3_smx:INFO: List of broken channels: []
15:58:38:ST3_smx:INFO: Total # of broken channels: 0
15:58:38:ST3_smx:INFO: List of broken channels: []
15:58:39:ST3_smx:INFO: Configuring SMX FAST
15:58:41:ST3_smx:INFO: chip: 5-4 40.898880 C 1189.190035 mV
15:58:41:ST3_smx:INFO: Electrons
15:58:41:ST3_smx:INFO: # loops 0
15:58:43:ST3_smx:INFO: # loops 1
15:58:44:ST3_smx:INFO: # loops 2
15:58:46:ST3_smx:INFO: # loops 3
15:58:48:ST3_smx:INFO: # loops 4
15:58:49:ST3_smx:INFO: Total # of broken channels: 0
15:58:49:ST3_smx:INFO: List of broken channels: []
15:58:49:ST3_smx:INFO: Total # of broken channels: 0
15:58:49:ST3_smx:INFO: List of broken channels: []
15:58:50:ST3_smx:INFO: Configuring SMX FAST
15:58:52:ST3_smx:INFO: chip: 12-5 37.726682 C 1200.969315 mV
15:58:52:ST3_smx:INFO: Electrons
15:58:52:ST3_smx:INFO: # loops 0
15:58:54:ST3_smx:INFO: # loops 1
15:58:55:ST3_smx:INFO: # loops 2
15:58:57:ST3_smx:INFO: # loops 3
15:58:58:ST3_smx:INFO: # loops 4
15:59:00:ST3_smx:INFO: Total # of broken channels: 0
15:59:00:ST3_smx:INFO: List of broken channels: []
15:59:00:ST3_smx:INFO: Total # of broken channels: 0
15:59:00:ST3_smx:INFO: List of broken channels: []
15:59:01:ST3_smx:INFO: Configuring SMX FAST
15:59:03:ST3_smx:INFO: chip: 7-6 37.726682 C 1195.082160 mV
15:59:03:ST3_smx:INFO: Electrons
15:59:03:ST3_smx:INFO: # loops 0
15:59:05:ST3_smx:INFO: # loops 1
15:59:06:ST3_smx:INFO: # loops 2
15:59:08:ST3_smx:INFO: # loops 3
15:59:09:ST3_smx:INFO: # loops 4
15:59:11:ST3_smx:INFO: Total # of broken channels: 0
15:59:11:ST3_smx:INFO: List of broken channels: []
15:59:11:ST3_smx:INFO: Total # of broken channels: 0
15:59:11:ST3_smx:INFO: List of broken channels: []
15:59:12:ST3_smx:INFO: Configuring SMX FAST
15:59:14:ST3_smx:INFO: chip: 14-7 31.389742 C 1218.600960 mV
15:59:14:ST3_smx:INFO: Electrons
15:59:14:ST3_smx:INFO: # loops 0
15:59:15:ST3_smx:INFO: # loops 1
15:59:17:ST3_smx:INFO: # loops 2
15:59:19:ST3_smx:INFO: # loops 3
15:59:20:ST3_smx:INFO: # loops 4
15:59:22:ST3_smx:INFO: Total # of broken channels: 0
15:59:22:ST3_smx:INFO: List of broken channels: []
15:59:22:ST3_smx:INFO: Total # of broken channels: 0
15:59:22:ST3_smx:INFO: List of broken channels: []
15:59:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
15:59:23:febtest:INFO: 1-0 | XA-000-08-002-000-004-201-07 | 31.4 | 1224.5
15:59:23:febtest:INFO: 8-1 | XA-000-08-002-000-004-130-02 | 44.1 | 1171.5
15:59:23:febtest:INFO: 3-2 | XA-000-08-002-000-004-136-02 | 34.6 | 1206.9
15:59:24:febtest:INFO: 10-3 | XA-000-08-002-000-004-151-05 | 31.4 | 1218.6
15:59:24:febtest:INFO: 5-4 | XA-000-08-002-000-004-137-02 | 40.9 | 1189.2
15:59:24:febtest:INFO: 12-5 | XA-000-08-002-000-004-146-05 | 37.7 | 1201.0
15:59:24:febtest:INFO: 7-6 | XA-000-08-002-000-004-138-02 | 37.7 | 1195.1
15:59:25:febtest:INFO: 14-7 | XA-000-08-002-000-004-154-05 | 31.4 | 1218.6
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2024_02_01-15_57_41
OPERATOR : Alois Alzheimer
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1076
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.451', '1.8880', '1.850', '2.4610', '2.450', '0.0002', '1.850', '0.0001']
VI_after__Init : ['0', '0', '0', '0', '0', '0']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
15:59:27:ST3_Shared:INFO: Listo of operators:Robert V.;
15:59:28:ST3_Shared:INFO: Listo of operators:Robert V.; Irakli K.;
15:59:31:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1076/TestDate_2024_02_01-15_57_41/