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FEB_1077 12.01.24 08:57:49
Info
08:57:06:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
08:57:07:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
08:57:21:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:57:21:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
08:57:21:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:57:35:ST3_ModuleSelector:INFO: L6DL200120 M6DL2B3001203B2 124 B
08:57:35:ST3_ModuleSelector:INFO: 20154
08:57:35:febtest:INFO: Testing FEB with SN 1077
Traceback (most recent call last):
File "febtest.py", line 321, in DoFEB_SensorTest
if self.DoScanFEB8(reporter.out_dict):
File "febtest.py", line 178, in DoScanFEB8
if self.EMU.Scan_FEB8(reporter):
AttributeError: 'int' object has no attribute 'Scan_FEB8'
08:57:46:febtest:INFO: FEB 8-2 selected
08:57:46:smx_tester:INFO: Setting Elink clock mode to 160 MHz
08:57:49:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:57:49:ST3_Shared:INFO: -------------------------FEB-Sensor-------------------------
08:57:49:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:57:50:ST3_ModuleSelector:INFO: L6DL200120 M6DL2B3001203B2 124 B
08:57:50:ST3_ModuleSelector:INFO: 20154
08:57:50:febtest:INFO: Testing FEB with SN 1077
08:57:51:smx_tester:INFO: Scanning setup
08:57:51:elinks:INFO: Disabling clock on downlink 0
08:57:51:elinks:INFO: Disabling clock on downlink 1
08:57:51:elinks:INFO: Disabling clock on downlink 2
08:57:51:elinks:INFO: Disabling clock on downlink 3
08:57:51:elinks:INFO: Disabling clock on downlink 4
08:57:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:57:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:57:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:57:51:elinks:INFO: Disabling clock on downlink 0
08:57:51:elinks:INFO: Disabling clock on downlink 1
08:57:51:elinks:INFO: Disabling clock on downlink 2
08:57:51:elinks:INFO: Disabling clock on downlink 3
08:57:51:elinks:INFO: Disabling clock on downlink 4
08:57:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:57:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:57:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:57:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:57:51:elinks:INFO: Disabling clock on downlink 0
08:57:51:elinks:INFO: Disabling clock on downlink 1
08:57:51:elinks:INFO: Disabling clock on downlink 2
08:57:51:elinks:INFO: Disabling clock on downlink 3
08:57:51:elinks:INFO: Disabling clock on downlink 4
08:57:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:57:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:57:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:57:52:elinks:INFO: Disabling clock on downlink 0
08:57:52:elinks:INFO: Disabling clock on downlink 1
08:57:52:elinks:INFO: Disabling clock on downlink 2
08:57:52:elinks:INFO: Disabling clock on downlink 3
08:57:52:elinks:INFO: Disabling clock on downlink 4
08:57:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:57:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:57:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:57:52:elinks:INFO: Disabling clock on downlink 0
08:57:52:elinks:INFO: Disabling clock on downlink 1
08:57:52:elinks:INFO: Disabling clock on downlink 2
08:57:52:elinks:INFO: Disabling clock on downlink 3
08:57:52:elinks:INFO: Disabling clock on downlink 4
08:57:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:57:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:57:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:57:52:setup_element:INFO: Scanning clock phase
08:57:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:57:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:57:52:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:57:52:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
08:57:52:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
08:57:52:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:57:52:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:57:52:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:57:52:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:57:52:setup_element:INFO: Eye window for uplink 6 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
08:57:52:setup_element:INFO: Eye window for uplink 7 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
08:57:52:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:57:52:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:57:52:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:57:52:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:57:52:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:57:52:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:57:52:setup_element:INFO: Eye window for uplink 14: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:57:52:setup_element:INFO: Eye window for uplink 15: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:57:52:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
08:57:52:setup_element:INFO: Scanning data phases
08:57:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:57:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:57:57:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:57:57:setup_element:INFO: Eye window for uplink 0 : _____________XXXXX______________________
Data delay found: 35
08:57:57:setup_element:INFO: Eye window for uplink 1 : _________XXXXX__________________________
Data delay found: 31
08:57:57:setup_element:INFO: Eye window for uplink 2 : __________XXXXX_________________________
Data delay found: 32
08:57:57:setup_element:INFO: Eye window for uplink 3 : ______XXXXXX____________________________
Data delay found: 28
08:57:57:setup_element:INFO: Eye window for uplink 4 : _______XXXXXX___________________________
Data delay found: 29
08:57:57:setup_element:INFO: Eye window for uplink 5 : ___XXXXX________________________________
Data delay found: 25
08:57:57:setup_element:INFO: Eye window for uplink 6 : X___________________________________XXXX
Data delay found: 18
08:57:57:setup_element:INFO: Eye window for uplink 7 : ________________________________XXXXX___
Data delay found: 14
08:57:57:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________
Data delay found: 6
08:57:57:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXX______
Data delay found: 11
08:57:57:setup_element:INFO: Eye window for uplink 10: _________________________XXXXX__________
Data delay found: 7
08:57:57:setup_element:INFO: Eye window for uplink 11: _____________________________XXXXX______
Data delay found: 11
08:57:57:setup_element:INFO: Eye window for uplink 12: ____________________________XXXX________
Data delay found: 9
08:57:57:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXX_____
Data delay found: 12
08:57:57:setup_element:INFO: Eye window for uplink 14: ___________________________XXXXX________
Data delay found: 9
08:57:57:setup_element:INFO: Eye window for uplink 15: ____________________________XXXXX_______
Data delay found: 10
08:57:57:setup_element:INFO: Setting the data phase to 35 for uplink 0
08:57:57:setup_element:INFO: Setting the data phase to 31 for uplink 1
08:57:57:setup_element:INFO: Setting the data phase to 32 for uplink 2
08:57:57:setup_element:INFO: Setting the data phase to 28 for uplink 3
08:57:57:setup_element:INFO: Setting the data phase to 29 for uplink 4
08:57:57:setup_element:INFO: Setting the data phase to 25 for uplink 5
08:57:57:setup_element:INFO: Setting the data phase to 18 for uplink 6
08:57:57:setup_element:INFO: Setting the data phase to 14 for uplink 7
08:57:57:setup_element:INFO: Setting the data phase to 6 for uplink 8
08:57:57:setup_element:INFO: Setting the data phase to 11 for uplink 9
08:57:57:setup_element:INFO: Setting the data phase to 7 for uplink 10
08:57:57:setup_element:INFO: Setting the data phase to 11 for uplink 11
08:57:57:setup_element:INFO: Setting the data phase to 9 for uplink 12
08:57:57:setup_element:INFO: Setting the data phase to 12 for uplink 13
08:57:57:setup_element:INFO: Setting the data phase to 9 for uplink 14
08:57:57:setup_element:INFO: Setting the data phase to 10 for uplink 15
08:57:57:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: ________________________________________________________________________XXXXXXXX
Uplink 5: ________________________________________________________________________XXXXXXXX
Uplink 6: ______________________________________________________________________XXXXXXX___
Uplink 7: ______________________________________________________________________XXXXXXX___
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _____________________________________________________________________XXXXXXX____
Uplink 15: _____________________________________________________________________XXXXXXX____
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 1:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 2:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 3:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 5:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 6:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 10:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 11:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 12:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 15:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
]
08:57:57:setup_element:INFO: Beginning SMX ASICs map scan
08:57:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:57:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:57:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:57:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:57:58:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:57:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:57:58:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:57:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:57:58:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:57:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:57:58:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:57:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:57:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:57:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:57:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:57:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:57:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:57:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:57:59:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:57:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:57:59:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:58:00:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: ________________________________________________________________________XXXXXXXX
Uplink 5: ________________________________________________________________________XXXXXXXX
Uplink 6: ______________________________________________________________________XXXXXXX___
Uplink 7: ______________________________________________________________________XXXXXXX___
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _____________________________________________________________________XXXXXXX____
Uplink 15: _____________________________________________________________________XXXXXXX____
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 1:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 2:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 3:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 5:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 6:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 7:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 10:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 11:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 12:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 15:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
08:58:00:setup_element:INFO: Performing Elink synchronization
08:58:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:58:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:58:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:58:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:58:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:58:00:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:58:01:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
08:58:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
08:58:02:febtest:INFO: 1-0 | XA-000-08-002-001-007-191-13 | 15.6 | 1242.0
08:58:02:febtest:INFO: 8-1 | XA-000-08-002-001-007-223-06 | 21.9 | 1224.5
08:58:02:febtest:INFO: 3-2 | XA-000-08-002-001-007-184-13 | 18.7 | 1242.0
08:58:02:febtest:INFO: 10-3 | XA-000-08-002-001-007-229-15 | 21.9 | 1218.6
08:58:03:febtest:INFO: 5-4 | XA-000-08-002-001-007-194-01 | 25.1 | 1206.9
08:58:03:febtest:INFO: 12-5 | XA-000-08-002-001-007-219-06 | 21.9 | 1206.9
08:58:03:febtest:INFO: 7-6 | XA-000-08-002-001-007-203-01 | 25.1 | 1212.7
08:58:03:febtest:INFO: 14-7 | XA-000-08-002-001-007-221-06 | 31.4 | 1189.2
08:58:04:ST3_smx:INFO: Configuring SMX FAST
08:58:06:ST3_smx:INFO: chip: 1-0 28.225000 C 1200.969315 mV
08:58:06:ST3_smx:INFO: Electrons
08:58:06:ST3_smx:INFO: # loops 0
08:58:07:ST3_smx:INFO: # loops 1
08:58:09:ST3_smx:INFO: # loops 2
08:58:10:ST3_smx:INFO: # loops 3
08:58:12:ST3_smx:INFO: # loops 4
08:58:14:ST3_smx:INFO: Total # of broken channels: 0
08:58:14:ST3_smx:INFO: List of broken channels: []
08:58:14:ST3_smx:INFO: Total # of broken channels: 0
08:58:14:ST3_smx:INFO: List of broken channels: []
08:58:14:ST3_smx:INFO: Configuring SMX FAST
08:58:16:ST3_smx:INFO: chip: 8-1 28.225000 C 1195.082160 mV
08:58:16:ST3_smx:INFO: Electrons
08:58:16:ST3_smx:INFO: # loops 0
08:58:18:ST3_smx:INFO: # loops 1
08:58:20:ST3_smx:INFO: # loops 2
08:58:21:ST3_smx:INFO: # loops 3
08:58:23:ST3_smx:INFO: # loops 4
08:58:24:ST3_smx:INFO: Total # of broken channels: 0
08:58:24:ST3_smx:INFO: List of broken channels: []
08:58:24:ST3_smx:INFO: Total # of broken channels: 0
08:58:24:ST3_smx:INFO: List of broken channels: []
08:58:25:ST3_smx:INFO: Configuring SMX FAST
08:58:27:ST3_smx:INFO: chip: 3-2 25.062742 C 1212.728715 mV
08:58:27:ST3_smx:INFO: Electrons
08:58:27:ST3_smx:INFO: # loops 0
08:58:28:ST3_smx:INFO: # loops 1
08:58:30:ST3_smx:INFO: # loops 2
08:58:32:ST3_smx:INFO: # loops 3
08:58:33:ST3_smx:INFO: # loops 4
08:58:35:ST3_smx:INFO: Total # of broken channels: 0
08:58:35:ST3_smx:INFO: List of broken channels: []
08:58:35:ST3_smx:INFO: Total # of broken channels: 0
08:58:35:ST3_smx:INFO: List of broken channels: []
08:58:35:ST3_smx:INFO: Configuring SMX FAST
08:58:37:ST3_smx:INFO: chip: 10-3 18.745682 C 1224.468235 mV
08:58:37:ST3_smx:INFO: Electrons
08:58:37:ST3_smx:INFO: # loops 0
08:58:39:ST3_smx:INFO: # loops 1
08:58:40:ST3_smx:INFO: # loops 2
08:58:42:ST3_smx:INFO: # loops 3
08:58:44:ST3_smx:INFO: # loops 4
08:58:45:ST3_smx:INFO: Total # of broken channels: 0
08:58:45:ST3_smx:INFO: List of broken channels: []
08:58:45:ST3_smx:INFO: Total # of broken channels: 0
08:58:45:ST3_smx:INFO: List of broken channels: []
08:58:46:ST3_smx:INFO: Configuring SMX FAST
08:58:48:ST3_smx:INFO: chip: 5-4 31.389742 C 1195.082160 mV
08:58:48:ST3_smx:INFO: Electrons
08:58:48:ST3_smx:INFO: # loops 0
08:58:49:ST3_smx:INFO: # loops 1
08:58:51:ST3_smx:INFO: # loops 2
08:58:52:ST3_smx:INFO: # loops 3
08:58:54:ST3_smx:INFO: # loops 4
08:58:56:ST3_smx:INFO: Total # of broken channels: 0
08:58:56:ST3_smx:INFO: List of broken channels: []
08:58:56:ST3_smx:INFO: Total # of broken channels: 0
08:58:56:ST3_smx:INFO: List of broken channels: []
08:58:56:ST3_smx:INFO: Configuring SMX FAST
08:58:58:ST3_smx:INFO: chip: 12-5 25.062742 C 1206.851500 mV
08:58:58:ST3_smx:INFO: Electrons
08:58:58:ST3_smx:INFO: # loops 0
08:59:00:ST3_smx:INFO: # loops 1
08:59:01:ST3_smx:INFO: # loops 2
08:59:03:ST3_smx:INFO: # loops 3
08:59:04:ST3_smx:INFO: # loops 4
08:59:06:ST3_smx:INFO: Total # of broken channels: 0
08:59:06:ST3_smx:INFO: List of broken channels: []
08:59:06:ST3_smx:INFO: Total # of broken channels: 0
08:59:06:ST3_smx:INFO: List of broken channels: []
08:59:06:ST3_smx:INFO: Configuring SMX FAST
08:59:08:ST3_smx:INFO: chip: 7-6 25.062742 C 1218.600960 mV
08:59:08:ST3_smx:INFO: Electrons
08:59:08:ST3_smx:INFO: # loops 0
08:59:10:ST3_smx:INFO: # loops 1
08:59:12:ST3_smx:INFO: # loops 2
08:59:13:ST3_smx:INFO: # loops 3
08:59:15:ST3_smx:INFO: # loops 4
08:59:17:ST3_smx:INFO: Total # of broken channels: 0
08:59:17:ST3_smx:INFO: List of broken channels: []
08:59:17:ST3_smx:INFO: Total # of broken channels: 0
08:59:17:ST3_smx:INFO: List of broken channels: []
08:59:17:ST3_smx:INFO: Configuring SMX FAST
08:59:19:ST3_smx:INFO: chip: 14-7 31.389742 C 1189.190035 mV
08:59:19:ST3_smx:INFO: Electrons
08:59:19:ST3_smx:INFO: # loops 0
08:59:20:ST3_smx:INFO: # loops 1
08:59:22:ST3_smx:INFO: # loops 2
08:59:24:ST3_smx:INFO: # loops 3
08:59:25:ST3_smx:INFO: # loops 4
08:59:27:ST3_smx:INFO: Total # of broken channels: 0
08:59:27:ST3_smx:INFO: List of broken channels: []
08:59:27:ST3_smx:INFO: Total # of broken channels: 0
08:59:27:ST3_smx:INFO: List of broken channels: []
08:59:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
08:59:28:febtest:INFO: 1-0 | XA-000-08-002-001-007-191-13 | 28.2 | 1201.0
08:59:28:febtest:INFO: 8-1 | XA-000-08-002-001-007-223-06 | 28.2 | 1201.0
08:59:28:febtest:INFO: 3-2 | XA-000-08-002-001-007-184-13 | 25.1 | 1218.6
08:59:28:febtest:INFO: 10-3 | XA-000-08-002-001-007-229-15 | 21.9 | 1224.5
08:59:29:febtest:INFO: 5-4 | XA-000-08-002-001-007-194-01 | 31.4 | 1195.1
08:59:29:febtest:INFO: 12-5 | XA-000-08-002-001-007-219-06 | 25.1 | 1206.9
08:59:29:febtest:INFO: 7-6 | XA-000-08-002-001-007-203-01 | 21.9 | 1218.6
08:59:29:febtest:INFO: 14-7 | XA-000-08-002-001-007-221-06 | 31.4 | 1189.2
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 2024_01_12-08_57_49
OPERATOR : Oleksandr S.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME : L6DL200120 M6DL2B3001203B2 124 B
FEB_SN : 1077
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
SENSOR_ID: 20154
MODULE_NAME: L6DL200120 M6DL2B3001203B2 124 B
MODULE_TYPE:
MODULE_LADDER:
MODULE_MODULE:
MODULE_SIZE: 0
MODULE_GRADE:
---------------------------------------
VI_before_Init : ['2.450', '1.8680', '1.851', '0.5279', '7.000', '1.5270', '7.000', '1.5270']
VI_after__Init : ['2.450', '1.9870', '1.850', '0.6147', '7.000', '1.5320', '7.000', '1.5320']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
08:59:30:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1077/TestDate_2024_01_12-08_57_49/