14:25:42:febtest:INFO:	FEB 8-2 selected
14:25:42:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
14:25:55:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:25:55:ST3_Shared:INFO:	-----------------------FEB-Microcable-----------------------
14:25:55:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:25:56:febtest:INFO:	Testing FEB with SN 1093
14:25:57:smx_tester:INFO:	Scanning setup
14:25:57:elinks:INFO:	Disabling clock on downlink 0
14:25:57:elinks:INFO:	Disabling clock on downlink 1
14:25:57:elinks:INFO:	Disabling clock on downlink 2
14:25:57:elinks:INFO:	Disabling clock on downlink 3
14:25:57:elinks:INFO:	Disabling clock on downlink 4
14:25:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:25:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:25:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:25:57:elinks:INFO:	Disabling clock on downlink 0
14:25:57:elinks:INFO:	Disabling clock on downlink 1
14:25:57:elinks:INFO:	Disabling clock on downlink 2
14:25:57:elinks:INFO:	Disabling clock on downlink 3
14:25:57:elinks:INFO:	Disabling clock on downlink 4
14:25:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:25:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
14:25:57:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
14:25:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:25:57:elinks:INFO:	Disabling clock on downlink 0
14:25:57:elinks:INFO:	Disabling clock on downlink 1
14:25:57:elinks:INFO:	Disabling clock on downlink 2
14:25:57:elinks:INFO:	Disabling clock on downlink 3
14:25:57:elinks:INFO:	Disabling clock on downlink 4
14:25:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:25:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:25:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:25:57:elinks:INFO:	Disabling clock on downlink 0
14:25:57:elinks:INFO:	Disabling clock on downlink 1
14:25:57:elinks:INFO:	Disabling clock on downlink 2
14:25:57:elinks:INFO:	Disabling clock on downlink 3
14:25:57:elinks:INFO:	Disabling clock on downlink 4
14:25:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:25:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:25:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:25:57:elinks:INFO:	Disabling clock on downlink 0
14:25:57:elinks:INFO:	Disabling clock on downlink 1
14:25:57:elinks:INFO:	Disabling clock on downlink 2
14:25:57:elinks:INFO:	Disabling clock on downlink 3
14:25:57:elinks:INFO:	Disabling clock on downlink 4
14:25:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:25:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:25:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:25:58:setup_element:INFO:	Scanning clock phase
14:25:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:25:58:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:25:58:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
14:25:58:setup_element:INFO:	Eye window for uplink 0 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:25:58:setup_element:INFO:	Eye window for uplink 1 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:25:58:setup_element:INFO:	Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:25:58:setup_element:INFO:	Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:25:58:setup_element:INFO:	Eye window for uplink 4 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 5 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 6 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:25:58:setup_element:INFO:	Eye window for uplink 7 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:25:58:setup_element:INFO:	Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 10: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 11: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 12: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 13: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 14: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:25:58:setup_element:INFO:	Eye window for uplink 15: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:25:58:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 1
14:25:58:setup_element:INFO:	Scanning data phases
14:25:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:25:58:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:26:03:setup_element:INFO:	Data phase scan results for group 0, downlink 1
14:26:03:setup_element:INFO:	Eye window for uplink 0 : _____________XXXXX______________________
Data delay found: 35
14:26:03:setup_element:INFO:	Eye window for uplink 1 : _________XXXX___________________________
Data delay found: 30
14:26:03:setup_element:INFO:	Eye window for uplink 2 : _________XXXXX__________________________
Data delay found: 31
14:26:03:setup_element:INFO:	Eye window for uplink 3 : ______XXXXX_____________________________
Data delay found: 28
14:26:03:setup_element:INFO:	Eye window for uplink 4 : _____XXXX_______________________________
Data delay found: 26
14:26:03:setup_element:INFO:	Eye window for uplink 5 : _XXXXX_________________________________X
Data delay found: 22
14:26:03:setup_element:INFO:	Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
14:26:03:setup_element:INFO:	Eye window for uplink 7 : __________________________________XXXXX_
Data delay found: 16
14:26:03:setup_element:INFO:	Eye window for uplink 8 : ________________________XXXX____________
Data delay found: 5
14:26:03:setup_element:INFO:	Eye window for uplink 9 : _____________________________XXXXX______
Data delay found: 11
14:26:03:setup_element:INFO:	Eye window for uplink 10: _________________________XXXXXX_________
Data delay found: 7
14:26:03:setup_element:INFO:	Eye window for uplink 11: _____________________________XXXXXX_____
Data delay found: 11
14:26:03:setup_element:INFO:	Eye window for uplink 12: ___________________________XXXX_________
Data delay found: 8
14:26:03:setup_element:INFO:	Eye window for uplink 13: ______________________________XXXXX_____
Data delay found: 12
14:26:03:setup_element:INFO:	Eye window for uplink 14: _____________________________XXXXX______
Data delay found: 11
14:26:03:setup_element:INFO:	Eye window for uplink 15: ______________________________XXXXX_____
Data delay found: 12
14:26:03:setup_element:INFO:	Setting the data phase to 35 for uplink 0
14:26:03:setup_element:INFO:	Setting the data phase to 30 for uplink 1
14:26:03:setup_element:INFO:	Setting the data phase to 31 for uplink 2
14:26:03:setup_element:INFO:	Setting the data phase to 28 for uplink 3
14:26:03:setup_element:INFO:	Setting the data phase to 26 for uplink 4
14:26:03:setup_element:INFO:	Setting the data phase to 22 for uplink 5
14:26:03:setup_element:INFO:	Setting the data phase to 20 for uplink 6
14:26:03:setup_element:INFO:	Setting the data phase to 16 for uplink 7
14:26:03:setup_element:INFO:	Setting the data phase to 5 for uplink 8
14:26:03:setup_element:INFO:	Setting the data phase to 11 for uplink 9
14:26:03:setup_element:INFO:	Setting the data phase to 7 for uplink 10
14:26:03:setup_element:INFO:	Setting the data phase to 11 for uplink 11
14:26:03:setup_element:INFO:	Setting the data phase to 8 for uplink 12
14:26:03:setup_element:INFO:	Setting the data phase to 12 for uplink 13
14:26:03:setup_element:INFO:	Setting the data phase to 11 for uplink 14
14:26:03:setup_element:INFO:	Setting the data phase to 12 for uplink 15
14:26:03:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 69
    Eye Windows:
      Uplink  0: ________________________________________________________________________XXXXXXXX
      Uplink  1: ________________________________________________________________________XXXXXXXX
      Uplink  2: ________________________________________________________________________XXXXXXXX
      Uplink  3: ________________________________________________________________________XXXXXXXX
      Uplink  4: ______________________________________________________________________XXXXXXXX__
      Uplink  5: ______________________________________________________________________XXXXXXXX__
      Uplink  6: _______________________________________________________________________XXXXXXXX_
      Uplink  7: _______________________________________________________________________XXXXXXXX_
      Uplink  8: ______________________________________________________________________XXXXXXXX__
      Uplink  9: ______________________________________________________________________XXXXXXXX__
      Uplink 10: _____________________________________________________________________XXXXXXXXX__
      Uplink 11: _____________________________________________________________________XXXXXXXXX__
      Uplink 12: ______________________________________________________________________XXXXXXX___
      Uplink 13: ______________________________________________________________________XXXXXXX___
      Uplink 14: _______________________________________________________________________XXXXXX___
      Uplink 15: _______________________________________________________________________XXXXXX___
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 1:
      Optimal Phase: 30
      Window Length: 36
      Eye Window: _________XXXX___________________________
    Uplink 2:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 3:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 4:
      Optimal Phase: 26
      Window Length: 36
      Eye Window: _____XXXX_______________________________
    Uplink 5:
      Optimal Phase: 22
      Window Length: 33
      Eye Window: _XXXXX_________________________________X
    Uplink 6:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 7:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 8:
      Optimal Phase: 5
      Window Length: 36
      Eye Window: ________________________XXXX____________
    Uplink 9:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 10:
      Optimal Phase: 7
      Window Length: 34
      Eye Window: _________________________XXXXXX_________
    Uplink 11:
      Optimal Phase: 11
      Window Length: 34
      Eye Window: _____________________________XXXXXX_____
    Uplink 12:
      Optimal Phase: 8
      Window Length: 36
      Eye Window: ___________________________XXXX_________
    Uplink 13:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 14:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 15:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
]
14:26:03:setup_element:INFO:	Beginning SMX ASICs map scan
14:26:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:26:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:26:03:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:26:03:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:26:03:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:26:03:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:26:04:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:26:04:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:26:04:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:26:04:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:26:04:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:26:04:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:26:04:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:26:04:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:26:04:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:26:04:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:26:04:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:26:05:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:26:05:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:26:05:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:26:05:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:26:06:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 69
    Eye Windows:
      Uplink  0: ________________________________________________________________________XXXXXXXX
      Uplink  1: ________________________________________________________________________XXXXXXXX
      Uplink  2: ________________________________________________________________________XXXXXXXX
      Uplink  3: ________________________________________________________________________XXXXXXXX
      Uplink  4: ______________________________________________________________________XXXXXXXX__
      Uplink  5: ______________________________________________________________________XXXXXXXX__
      Uplink  6: _______________________________________________________________________XXXXXXXX_
      Uplink  7: _______________________________________________________________________XXXXXXXX_
      Uplink  8: ______________________________________________________________________XXXXXXXX__
      Uplink  9: ______________________________________________________________________XXXXXXXX__
      Uplink 10: _____________________________________________________________________XXXXXXXXX__
      Uplink 11: _____________________________________________________________________XXXXXXXXX__
      Uplink 12: ______________________________________________________________________XXXXXXX___
      Uplink 13: ______________________________________________________________________XXXXXXX___
      Uplink 14: _______________________________________________________________________XXXXXX___
      Uplink 15: _______________________________________________________________________XXXXXX___
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 1:
      Optimal Phase: 30
      Window Length: 36
      Eye Window: _________XXXX___________________________
    Uplink 2:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 3:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 4:
      Optimal Phase: 26
      Window Length: 36
      Eye Window: _____XXXX_______________________________
    Uplink 5:
      Optimal Phase: 22
      Window Length: 33
      Eye Window: _XXXXX_________________________________X
    Uplink 6:
      Optimal Phase: 20
      Window Length: 35
      Eye Window: XXX___________________________________XX
    Uplink 7:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 8:
      Optimal Phase: 5
      Window Length: 36
      Eye Window: ________________________XXXX____________
    Uplink 9:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 10:
      Optimal Phase: 7
      Window Length: 34
      Eye Window: _________________________XXXXXX_________
    Uplink 11:
      Optimal Phase: 11
      Window Length: 34
      Eye Window: _____________________________XXXXXX_____
    Uplink 12:
      Optimal Phase: 8
      Window Length: 36
      Eye Window: ___________________________XXXX_________
    Uplink 13:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____
    Uplink 14:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 15:
      Optimal Phase: 12
      Window Length: 35
      Eye Window: ______________________________XXXXX_____

14:26:06:setup_element:INFO:	Performing Elink synchronization
14:26:06:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:26:06:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:26:06:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:26:06:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:26:06:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
14:26:06:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:26:06:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  1  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   1  |   [0]   |  1  |  0  |     [8]      |   [(0, 8), (1, 9)] 
   2  |   [0]   |  1  |  0  |     [3]      |   [(0, 3), (1, 2)] 
   3  |   [0]   |  1  |  0  |     [10]     |  [(0, 10), (1, 11)]
   4  |   [0]   |  1  |  0  |     [5]      |   [(0, 5), (1, 4)] 
   5  |   [0]   |  1  |  0  |     [12]     |  [(0, 12), (1, 13)]
   6  |   [0]   |  1  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   7  |   [0]   |  1  |  0  |     [14]     |  [(0, 14), (1, 15)]
14:26:07:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
14:26:07:febtest:INFO:	1-0 | XA-000-08-002-001-007-022-09 |  40.9 | 1171.5
14:26:08:febtest:INFO:	8-1 | XA-000-08-002-001-007-005-14 |  25.1 | 1212.7
14:26:08:febtest:INFO:	3-2 | XA-000-08-002-001-007-011-14 |  56.8 | 1130.0
14:26:08:febtest:INFO:	10-3 | XA-000-08-002-001-007-015-14 |  50.4 | 1141.9
14:26:08:febtest:INFO:	5-4 | XA-000-08-002-001-007-007-14 |  31.4 | 1212.7
14:26:08:febtest:INFO:	12-5 | XA-000-08-002-001-007-002-14 |  34.6 | 1201.0
14:26:09:febtest:INFO:	7-6 | XA-000-08-002-001-007-008-14 |  40.9 | 1183.3
14:26:09:febtest:INFO:	14-7 | XA-000-08-002-001-007-010-14 |  28.2 | 1224.5
14:26:09:ST3_smx:INFO:	Configuring SMX FAST
14:26:11:ST3_smx:INFO:	chip: 1-0 	 40.898880 C 	 1165.571835 mV
14:26:11:ST3_smx:INFO:		Electrons
14:26:11:ST3_smx:INFO:	# loops 0
14:26:13:ST3_smx:INFO:	# loops 1
14:26:14:ST3_smx:INFO:	# loops 2
14:26:16:ST3_smx:INFO:	# loops 3
14:26:18:ST3_smx:INFO:	# loops 4
14:26:19:ST3_smx:INFO:	Total # of broken channels: 0
14:26:19:ST3_smx:INFO:	List of broken channels: []
14:26:19:ST3_smx:INFO:	Total # of broken channels: 0
14:26:19:ST3_smx:INFO:	List of broken channels: []
14:26:20:ST3_smx:INFO:	Configuring SMX FAST
14:26:22:ST3_smx:INFO:	chip: 8-1 	 31.389742 C 	 1206.851500 mV
14:26:22:ST3_smx:INFO:		Electrons
14:26:22:ST3_smx:INFO:	# loops 0
14:26:24:ST3_smx:INFO:	# loops 1
14:26:25:ST3_smx:INFO:	# loops 2
14:26:27:ST3_smx:INFO:	# loops 3
14:26:29:ST3_smx:INFO:	# loops 4
14:26:30:ST3_smx:INFO:	Total # of broken channels: 0
14:26:30:ST3_smx:INFO:	List of broken channels: []
14:26:30:ST3_smx:INFO:	Total # of broken channels: 0
14:26:30:ST3_smx:INFO:	List of broken channels: []
14:26:31:ST3_smx:INFO:	Configuring SMX FAST
14:26:33:ST3_smx:INFO:	chip: 3-2 	 53.612520 C 	 1135.937260 mV
14:26:33:ST3_smx:INFO:		Electrons
14:26:33:ST3_smx:INFO:	# loops 0
14:26:35:ST3_smx:INFO:	# loops 1
14:26:36:ST3_smx:INFO:	# loops 2
14:26:38:ST3_smx:INFO:	# loops 3
14:26:40:ST3_smx:INFO:	# loops 4
14:26:41:ST3_smx:INFO:	Total # of broken channels: 0
14:26:41:ST3_smx:INFO:	List of broken channels: []
14:26:41:ST3_smx:INFO:	Total # of broken channels: 0
14:26:41:ST3_smx:INFO:	List of broken channels: []
14:26:42:ST3_smx:INFO:	Configuring SMX FAST
14:26:44:ST3_smx:INFO:	chip: 10-3 	 47.250730 C 	 1159.654860 mV
14:26:44:ST3_smx:INFO:		Electrons
14:26:44:ST3_smx:INFO:	# loops 0
14:26:46:ST3_smx:INFO:	# loops 1
14:26:47:ST3_smx:INFO:	# loops 2
14:26:49:ST3_smx:INFO:	# loops 3
14:26:50:ST3_smx:INFO:	# loops 4
14:26:52:ST3_smx:INFO:	Total # of broken channels: 0
14:26:52:ST3_smx:INFO:	List of broken channels: []
14:26:52:ST3_smx:INFO:	Total # of broken channels: 0
14:26:52:ST3_smx:INFO:	List of broken channels: []
14:26:52:ST3_smx:INFO:	Configuring SMX FAST
14:26:54:ST3_smx:INFO:	chip: 5-4 	 37.726682 C 	 1195.082160 mV
14:26:54:ST3_smx:INFO:		Electrons
14:26:54:ST3_smx:INFO:	# loops 0
14:26:56:ST3_smx:INFO:	# loops 1
14:26:58:ST3_smx:INFO:	# loops 2
14:26:59:ST3_smx:INFO:	# loops 3
14:27:01:ST3_smx:INFO:	# loops 4
14:27:03:ST3_smx:INFO:	Total # of broken channels: 0
14:27:03:ST3_smx:INFO:	List of broken channels: []
14:27:03:ST3_smx:INFO:	Total # of broken channels: 0
14:27:03:ST3_smx:INFO:	List of broken channels: []
14:27:03:ST3_smx:INFO:	Configuring SMX FAST
14:27:05:ST3_smx:INFO:	chip: 12-5 	 37.726682 C 	 1189.190035 mV
14:27:05:ST3_smx:INFO:		Electrons
14:27:05:ST3_smx:INFO:	# loops 0
14:27:07:ST3_smx:INFO:	# loops 1
14:27:08:ST3_smx:INFO:	# loops 2
14:27:10:ST3_smx:INFO:	# loops 3
14:27:12:ST3_smx:INFO:	# loops 4
14:27:13:ST3_smx:INFO:	Total # of broken channels: 0
14:27:13:ST3_smx:INFO:	List of broken channels: []
14:27:13:ST3_smx:INFO:	Total # of broken channels: 0
14:27:13:ST3_smx:INFO:	List of broken channels: []
14:27:14:ST3_smx:INFO:	Configuring SMX FAST
14:27:16:ST3_smx:INFO:	chip: 7-6 	 44.073563 C 	 1183.292940 mV
14:27:16:ST3_smx:INFO:		Electrons
14:27:16:ST3_smx:INFO:	# loops 0
14:27:17:ST3_smx:INFO:	# loops 1
14:27:19:ST3_smx:INFO:	# loops 2
14:27:21:ST3_smx:INFO:	# loops 3
14:27:23:ST3_smx:INFO:	# loops 4
14:27:24:ST3_smx:INFO:	Total # of broken channels: 0
14:27:24:ST3_smx:INFO:	List of broken channels: []
14:27:24:ST3_smx:INFO:	Total # of broken channels: 0
14:27:24:ST3_smx:INFO:	List of broken channels: []
14:27:25:ST3_smx:INFO:	Configuring SMX FAST
14:27:27:ST3_smx:INFO:	chip: 14-7 	 34.556970 C 	 1195.082160 mV
14:27:27:ST3_smx:INFO:		Electrons
14:27:27:ST3_smx:INFO:	# loops 0
14:27:29:ST3_smx:INFO:	# loops 1
14:27:30:ST3_smx:INFO:	# loops 2
14:27:32:ST3_smx:INFO:	# loops 3
14:27:34:ST3_smx:INFO:	# loops 4
14:27:35:ST3_smx:INFO:	Total # of broken channels: 0
14:27:35:ST3_smx:INFO:	List of broken channels: []
14:27:35:ST3_smx:INFO:	Total # of broken channels: 0
14:27:35:ST3_smx:INFO:	List of broken channels: []
14:27:36:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
14:27:36:febtest:INFO:	1-0 | XA-000-08-002-001-007-022-09 |  40.9 | 1171.5
14:27:36:febtest:INFO:	8-1 | XA-000-08-002-001-007-005-14 |  31.4 | 1206.9
14:27:36:febtest:INFO:	3-2 | XA-000-08-002-001-007-011-14 |  53.6 | 1141.9
14:27:37:febtest:INFO:	10-3 | XA-000-08-002-001-007-015-14 |  50.4 | 1165.6
14:27:37:febtest:INFO:	5-4 | XA-000-08-002-001-007-007-14 |  37.7 | 1195.1
14:27:37:febtest:INFO:	12-5 | XA-000-08-002-001-007-002-14 |  37.7 | 1189.2
14:27:37:febtest:INFO:	7-6 | XA-000-08-002-001-007-008-14 |  44.1 | 1183.3
14:27:37:febtest:INFO:	14-7 | XA-000-08-002-001-007-010-14 |  34.6 | 1195.1
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 2024_01_22-14_25_55
OPERATOR  : Robert V.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 1093
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
---------------------------------------
VI_before_Init : ['2.448', '1.5300', '1.845', '2.5370', '7.000', '1.5740', '7.000', '1.5740']
VI_after__Init : ['0', '0', '0', '0', '0', '0']
VI_at__the_End : ['0', '0', '0', '0', '0', '0']
14:27:42:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_1093/TestDate_2024_01_22-14_25_55/