
FEB_1107 21.02.24 08:12:17
TextEdit.txt
07:57:43:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,123796,HW50020003/SW2.71 07:57:44:febtest:INFO: FEB type: 8.2 07:57:44:febtest:INFO: FEB SN: 1074 07:57:44:febtest:INFO: FEB A: 1 07:57:44:febtest:INFO: FEB B: 0 07:57:44:febtest:INFO: FEB 8-2 selected 07:57:44:smx_tester:INFO: Setting Elink clock mode to 160 MHz 07:57:44:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!! 07:57:47:febtest:INFO: FEB 8-2 selected 07:57:47:smx_tester:INFO: Setting Elink clock mode to 160 MHz 07:57:47:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!! 07:57:55:febtest:INFO: FEB 8-2 selected 07:57:55:smx_tester:INFO: Setting Elink clock mode to 160 MHz 07:58:13:febtest:INFO: FEB type: 8.2 07:58:13:febtest:INFO: FEB SN: 1106 07:58:13:febtest:INFO: FEB A: 1 07:58:13:febtest:INFO: FEB B: 0 07:58:14:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 07:58:14:ST3_Shared:INFO: -------------------------FEB-Sensor------------------------- 07:58:14:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 07:58:33:ST3_ModuleSelector:INFO: L6DL600127 M6DL6B0001270B2 124 C 07:58:33:ST3_ModuleSelector:INFO: 07:58:34:febtest:INFO: Testing FEB with SN 1106 07:58:36:smx_tester:INFO: Scanning setup 07:58:36:elinks:INFO: Disabling clock on downlink 0 07:58:36:elinks:INFO: Disabling clock on downlink 1 07:58:36:elinks:INFO: Disabling clock on downlink 2 07:58:36:elinks:INFO: Disabling clock on downlink 3 07:58:36:elinks:INFO: Disabling clock on downlink 4 07:58:36:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:58:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 07:58:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:58:36:elinks:INFO: Disabling clock on downlink 0 07:58:36:elinks:INFO: Disabling clock on downlink 1 07:58:36:elinks:INFO: Disabling clock on downlink 2 07:58:36:elinks:INFO: Disabling clock on downlink 3 07:58:36:elinks:INFO: Disabling clock on downlink 4 07:58:36:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:58:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14 07:58:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15 07:58:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:58:37:elinks:INFO: Disabling clock on downlink 0 07:58:37:elinks:INFO: Disabling clock on downlink 1 07:58:37:elinks:INFO: Disabling clock on downlink 2 07:58:37:elinks:INFO: Disabling clock on downlink 3 07:58:37:elinks:INFO: Disabling clock on downlink 4 07:58:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:58:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 07:58:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:58:37:elinks:INFO: Disabling clock on downlink 0 07:58:37:elinks:INFO: Disabling clock on downlink 1 07:58:37:elinks:INFO: Disabling clock on downlink 2 07:58:37:elinks:INFO: Disabling clock on downlink 3 07:58:37:elinks:INFO: Disabling clock on downlink 4 07:58:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:58:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 07:58:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:58:37:elinks:INFO: Disabling clock on downlink 0 07:58:37:elinks:INFO: Disabling clock on downlink 1 07:58:37:elinks:INFO: Disabling clock on downlink 2 07:58:37:elinks:INFO: Disabling clock on downlink 3 07:58:37:elinks:INFO: Disabling clock on downlink 4 07:58:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 07:58:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 07:58:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 07:58:37:setup_element:INFO: Scanning clock phase 07:58:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 07:58:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 07:58:38:setup_element:INFO: Clock phase scan results for group 0, downlink 1 07:58:38:setup_element:INFO: Eye window for uplink 0 : _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 1 : _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 4 : ______________________________________________________________________XXXXXXX___ Clock Delay: 33 07:58:38:setup_element:INFO: Eye window for uplink 5 : ______________________________________________________________________XXXXXXX___ Clock Delay: 33 07:58:38:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXX____ Clock Delay: 32 07:58:38:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXX____ Clock Delay: 32 07:58:38:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXX___ Clock Delay: 32 07:58:38:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXX___ Clock Delay: 32 07:58:38:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__ Clock Delay: 34 07:58:38:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1 07:58:38:setup_element:INFO: Scanning data phases 07:58:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 07:58:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 07:58:43:setup_element:INFO: Data phase scan results for group 0, downlink 1 07:58:43:setup_element:INFO: Eye window for uplink 0 : ___________XXXXXX_______________________ Data delay found: 33 07:58:43:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________ Data delay found: 29 07:58:43:setup_element:INFO: Eye window for uplink 2 : ________XXXXX___________________________ Data delay found: 30 07:58:43:setup_element:INFO: Eye window for uplink 3 : ______XXXXX_____________________________ Data delay found: 28 07:58:43:setup_element:INFO: Eye window for uplink 4 : _____XXXXX______________________________ Data delay found: 27 07:58:43:setup_element:INFO: Eye window for uplink 5 : __XXXX__________________________________ Data delay found: 23 07:58:43:setup_element:INFO: Eye window for uplink 6 : XXX___________________________________XX Data delay found: 20 07:58:43:setup_element:INFO: Eye window for uplink 7 : __________________________________XXXXX_ Data delay found: 16 07:58:43:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________ Data delay found: 6 07:58:43:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____ Data delay found: 12 07:58:43:setup_element:INFO: Eye window for uplink 10: _____XXXXXXXXXXXXXXXXXXXXXXXXXX_________ Data delay found: 37 07:58:43:setup_element:INFO: Eye window for uplink 11: _____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_____ Data delay found: 39 07:58:43:setup_element:INFO: Eye window for uplink 12: ______________________________XXXXX_____ Data delay found: 12 07:58:43:setup_element:INFO: Eye window for uplink 13: _________________________________XXXXX__ Data delay found: 15 07:58:43:setup_element:INFO: Eye window for uplink 14: ______________________________XXXXX_____ Data delay found: 12 07:58:43:setup_element:INFO: Eye window for uplink 15: ________________________________XXXXX___ Data delay found: 14 07:58:43:setup_element:INFO: Setting the data phase to 33 for uplink 0 07:58:43:setup_element:INFO: Setting the data phase to 29 for uplink 1 07:58:43:setup_element:INFO: Setting the data phase to 30 for uplink 2 07:58:43:setup_element:INFO: Setting the data phase to 28 for uplink 3 07:58:43:setup_element:INFO: Setting the data phase to 27 for uplink 4 07:58:43:setup_element:INFO: Setting the data phase to 23 for uplink 5 07:58:43:setup_element:INFO: Setting the data phase to 20 for uplink 6 07:58:43:setup_element:INFO: Setting the data phase to 16 for uplink 7 07:58:43:setup_element:INFO: Setting the data phase to 6 for uplink 8 07:58:43:setup_element:INFO: Setting the data phase to 12 for uplink 9 07:58:43:setup_element:INFO: Setting the data phase to 37 for uplink 10 07:58:43:setup_element:INFO: Setting the data phase to 39 for uplink 11 07:58:43:setup_element:INFO: Setting the data phase to 12 for uplink 12 07:58:43:setup_element:INFO: Setting the data phase to 15 for uplink 13 07:58:43:setup_element:INFO: Setting the data phase to 12 for uplink 14 07:58:43:setup_element:INFO: Setting the data phase to 14 for uplink 15 07:58:43:ST3_emu:ERROR: [ Setup Element: Group: 0 Downlink: 1 Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ASICs Map: None Clock Phase Characteristic: Optimal Phase: 33 Window Length: 71 Eye Windows: Uplink 0: _______________________________________________________________________XXXXXXX__ Uplink 1: _______________________________________________________________________XXXXXXX__ Uplink 2: _______________________________________________________________________XXXXXXX__ Uplink 3: _______________________________________________________________________XXXXXXX__ Uplink 4: ______________________________________________________________________XXXXXXX___ Uplink 5: ______________________________________________________________________XXXXXXX___ Uplink 6: _______________________________________________________________________XXXXXXX__ Uplink 7: _______________________________________________________________________XXXXXXX__ Uplink 8: _____________________________________________________________________XXXXXXX____ Uplink 9: _____________________________________________________________________XXXXXXX____ Uplink 10: _____________________________________________________________________XXXXXXXX___ Uplink 11: _____________________________________________________________________XXXXXXXX___ Uplink 12: _______________________________________________________________________XXXXXXX__ Uplink 13: _______________________________________________________________________XXXXXXX__ Uplink 14: _______________________________________________________________________XXXXXXX__ Uplink 15: _______________________________________________________________________XXXXXXX__ Data phase characteristics: Uplink 0: Optimal Phase: 33 Window Length: 34 Eye Window: ___________XXXXXX_______________________ Uplink 1: Optimal Phase: 29 Window Length: 35 Eye Window: _______XXXXX____________________________ Uplink 2: Optimal Phase: 30 Window Length: 35 Eye Window: ________XXXXX___________________________ Uplink 3: Optimal Phase: 28 Window Length: 35 Eye Window: ______XXXXX_____________________________ Uplink 4: Optimal Phase: 27 Window Length: 35 Eye Window: _____XXXXX______________________________ Uplink 5: Optimal Phase: 23 Window Length: 36 Eye Window: __XXXX__________________________________ Uplink 6: Optimal Phase: 20 Window Length: 35 Eye Window: XXX___________________________________XX Uplink 7: Optimal Phase: 16 Window Length: 35 Eye Window: __________________________________XXXXX_ Uplink 8: Optimal Phase: 6 Window Length: 36 Eye Window: _________________________XXXX___________ Uplink 9: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 10: Optimal Phase: 37 Window Length: 14 Eye Window: _____XXXXXXXXXXXXXXXXXXXXXXXXXX_________ Uplink 11: Optimal Phase: 39 Window Length: 10 Eye Window: _____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_____ Uplink 12: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 13: Optimal Phase: 15 Window Length: 35 Eye Window: _________________________________XXXXX__ Uplink 14: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 15: Optimal Phase: 14 Window Length: 35 Eye Window: ________________________________XXXXX___ ] 07:58:43:setup_element:INFO: Beginning SMX ASICs map scan 07:58:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 07:58:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 07:58:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1] 07:58:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1] 07:58:43:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] 07:58:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1 07:58:44:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0 07:58:44:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8 07:58:44:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9 07:58:44:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3 07:58:44:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2 07:58:44:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10 07:58:44:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11 07:58:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5 07:58:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4 07:58:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12 07:58:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13 07:58:45:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7 07:58:45:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6 07:58:45:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14 07:58:45:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15 07:58:46:ST3_emu:ERROR: Setup Element: Group: 0 Downlink: 1 Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ASICs Map: ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0) ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9) ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2) ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11) ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4) ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13) ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6) ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15) Clock Phase Characteristic: Optimal Phase: 33 Window Length: 71 Eye Windows: Uplink 0: _______________________________________________________________________XXXXXXX__ Uplink 1: _______________________________________________________________________XXXXXXX__ Uplink 2: _______________________________________________________________________XXXXXXX__ Uplink 3: _______________________________________________________________________XXXXXXX__ Uplink 4: ______________________________________________________________________XXXXXXX___ Uplink 5: ______________________________________________________________________XXXXXXX___ Uplink 6: _______________________________________________________________________XXXXXXX__ Uplink 7: _______________________________________________________________________XXXXXXX__ Uplink 8: _____________________________________________________________________XXXXXXX____ Uplink 9: _____________________________________________________________________XXXXXXX____ Uplink 10: _____________________________________________________________________XXXXXXXX___ Uplink 11: _____________________________________________________________________XXXXXXXX___ Uplink 12: _______________________________________________________________________XXXXXXX__ Uplink 13: _______________________________________________________________________XXXXXXX__ Uplink 14: _______________________________________________________________________XXXXXXX__ Uplink 15: _______________________________________________________________________XXXXXXX__ Data phase characteristics: Uplink 0: Optimal Phase: 33 Window Length: 34 Eye Window: ___________XXXXXX_______________________ Uplink 1: Optimal Phase: 29 Window Length: 35 Eye Window: _______XXXXX____________________________ Uplink 2: Optimal Phase: 30 Window Length: 35 Eye Window: ________XXXXX___________________________ Uplink 3: Optimal Phase: 28 Window Length: 35 Eye Window: ______XXXXX_____________________________ Uplink 4: Optimal Phase: 27 Window Length: 35 Eye Window: _____XXXXX______________________________ Uplink 5: Optimal Phase: 23 Window Length: 36 Eye Window: __XXXX__________________________________ Uplink 6: Optimal Phase: 20 Window Length: 35 Eye Window: XXX___________________________________XX Uplink 7: Optimal Phase: 16 Window Length: 35 Eye Window: __________________________________XXXXX_ Uplink 8: Optimal Phase: 6 Window Length: 36 Eye Window: _________________________XXXX___________ Uplink 9: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 10: Optimal Phase: 37 Window Length: 14 Eye Window: _____XXXXXXXXXXXXXXXXXXXXXXXXXX_________ Uplink 11: Optimal Phase: 39 Window Length: 10 Eye Window: _____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX_____ Uplink 12: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 13: Optimal Phase: 15 Window Length: 35 Eye Window: _________________________________XXXXX__ Uplink 14: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 15: Optimal Phase: 14 Window Length: 35 Eye Window: ________________________________XXXXX___ 07:58:46:setup_element:INFO: Performing Elink synchronization 07:58:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 07:58:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 07:58:46:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1] 07:58:46:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1] 07:58:46:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1 07:58:46:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] 07:58:46:ST3_emu:INFO: Number of chips: 8 addr | upli | dwnli | grp | uplinks | uplinks_map 0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)] 1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)] 2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)] 3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)] 4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)] 5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)] 6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)] 7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)] FEB type: A FEB_A: 1 FEB_B: 0 07:58:48:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV] 07:58:48:febtest:INFO: 1-0 | XA-000-08-002-000-000-105-05 | 25.1 | 1201.0 07:58:48:febtest:INFO: 8-1 | XA-000-08-002-000-002-095-15 | 40.9 | 1141.9 07:58:48:febtest:INFO: 3-2 | XA-000-08-002-000-005-094-07 | 40.9 | 1147.8 07:58:49:febtest:INFO: 10-3 | XA-000-08-002-000-005-091-07 | 31.4 | 1183.3 07:58:49:febtest:INFO: 5-4 | XA-000-08-002-000-005-090-07 | 25.1 | 1195.1 07:58:49:febtest:INFO: 12-5 | XA-000-08-002-000-005-088-07 | 18.7 | 1212.7 07:58:49:febtest:INFO: 7-6 | XA-000-08-002-000-002-092-15 | 37.7 | 1171.5 07:58:50:febtest:INFO: 14-7 | XA-000-08-002-000-005-096-14 | 28.2 | 1189.2 07:58:50:ST3_smx:INFO: Configuring SMX FAST 07:58:52:ST3_smx:INFO: chip: 1-0 25.062742 C 1206.851500 mV 07:58:52:ST3_smx:INFO: Electrons 07:58:52:ST3_smx:INFO: # loops 0 07:58:54:ST3_smx:INFO: # loops 1 07:58:55:ST3_smx:INFO: # loops 2 07:58:57:ST3_smx:INFO: # loops 3 07:58:59:ST3_smx:INFO: # loops 4 07:59:00:ST3_smx:INFO: Total # of broken channels: 0 07:59:00:ST3_smx:INFO: List of broken channels: [] 07:59:00:ST3_smx:INFO: Total # of broken channels: 0 07:59:00:ST3_smx:INFO: List of broken channels: [] 07:59:01:ST3_smx:INFO: Configuring SMX FAST 07:59:03:ST3_smx:INFO: chip: 8-1 50.430383 C 1106.178435 mV 07:59:03:ST3_smx:INFO: Electrons 07:59:03:ST3_smx:INFO: # loops 0 07:59:05:ST3_smx:INFO: # loops 1 07:59:06:ST3_smx:INFO: # loops 2 07:59:08:ST3_smx:INFO: # loops 3 07:59:09:ST3_smx:INFO: # loops 4 07:59:11:ST3_smx:INFO: Total # of broken channels: 0 07:59:11:ST3_smx:INFO: List of broken channels: [] 07:59:11:ST3_smx:INFO: Total # of broken channels: 0 07:59:11:ST3_smx:INFO: List of broken channels: [] 07:59:11:ST3_smx:INFO: Configuring SMX FAST 07:59:13:ST3_smx:INFO: chip: 3-2 34.556970 C 1177.390875 mV 07:59:13:ST3_smx:INFO: Electrons 07:59:13:ST3_smx:INFO: # loops 0 07:59:15:ST3_smx:INFO: # loops 1 07:59:17:ST3_smx:INFO: # loops 2 07:59:18:ST3_smx:INFO: # loops 3 07:59:20:ST3_smx:INFO: # loops 4 07:59:22:ST3_smx:INFO: Total # of broken channels: 0 07:59:22:ST3_smx:INFO: List of broken channels: [] 07:59:22:ST3_smx:INFO: Total # of broken channels: 0 07:59:22:ST3_smx:INFO: List of broken channels: [] 07:59:22:ST3_smx:INFO: Configuring SMX FAST 07:59:24:ST3_smx:INFO: chip: 10-3 28.225000 C 1189.190035 mV 07:59:24:ST3_smx:INFO: Electrons 07:59:24:ST3_smx:INFO: # loops 0 07:59:26:ST3_smx:INFO: # loops 1 07:59:27:ST3_smx:INFO: # loops 2 07:59:29:ST3_smx:INFO: # loops 3 07:59:30:ST3_smx:INFO: # loops 4 07:59:32:ST3_smx:INFO: Total # of broken channels: 0 07:59:32:ST3_smx:INFO: List of broken channels: [] 07:59:32:ST3_smx:INFO: Total # of broken channels: 0 07:59:32:ST3_smx:INFO: List of broken channels: [] 07:59:32:ST3_smx:INFO: Configuring SMX FAST 07:59:34:ST3_smx:INFO: chip: 5-4 28.225000 C 1206.851500 mV 07:59:34:ST3_smx:INFO: Electrons 07:59:34:ST3_smx:INFO: # loops 0 07:59:36:ST3_smx:INFO: # loops 1 07:59:38:ST3_smx:INFO: # loops 2 07:59:39:ST3_smx:INFO: # loops 3 07:59:41:ST3_smx:INFO: # loops 4 07:59:42:ST3_smx:INFO: Total # of broken channels: 0 07:59:42:ST3_smx:INFO: List of broken channels: [] 07:59:42:ST3_smx:INFO: Total # of broken channels: 0 07:59:42:ST3_smx:INFO: List of broken channels: [] 07:59:43:ST3_smx:INFO: Configuring SMX FAST 07:59:45:ST3_smx:INFO: chip: 12-5 21.902970 C 1212.728715 mV 07:59:45:ST3_smx:INFO: Electrons 07:59:45:ST3_smx:INFO: # loops 0 07:59:47:ST3_smx:INFO: # loops 1 07:59:48:ST3_smx:INFO: # loops 2 07:59:50:ST3_smx:INFO: # loops 3 07:59:51:ST3_smx:INFO: # loops 4 07:59:53:ST3_smx:INFO: Total # of broken channels: 1 07:59:53:ST3_smx:INFO: List of broken channels: [79] 07:59:53:ST3_smx:INFO: Total # of broken channels: 2 07:59:53:ST3_smx:INFO: List of broken channels: [71, 79] 07:59:53:ST3_smx:INFO: Configuring SMX FAST 07:59:55:ST3_smx:INFO: chip: 7-6 50.430383 C 1141.874115 mV 07:59:55:ST3_smx:INFO: Electrons 07:59:55:ST3_smx:INFO: # loops 0 07:59:57:ST3_smx:INFO: # loops 1 07:59:59:ST3_smx:INFO: # loops 2 08:00:00:ST3_smx:INFO: # loops 3 08:00:02:ST3_smx:INFO: # loops 4 08:00:03:ST3_smx:INFO: Total # of broken channels: 0 08:00:03:ST3_smx:INFO: List of broken channels: [] 08:00:03:ST3_smx:INFO: Total # of broken channels: 0 08:00:03:ST3_smx:INFO: List of broken channels: [] 08:00:04:ST3_smx:INFO: Configuring SMX FAST 08:00:06:ST3_smx:INFO: chip: 14-7 25.062742 C 1206.851500 mV 08:00:06:ST3_smx:INFO: Electrons 08:00:06:ST3_smx:INFO: # loops 0 08:00:07:ST3_smx:INFO: # loops 1 08:00:09:ST3_smx:INFO: # loops 2 08:00:10:ST3_smx:INFO: # loops 3 08:00:12:ST3_smx:INFO: # loops 4 08:00:14:ST3_smx:INFO: Total # of broken channels: 0 08:00:14:ST3_smx:INFO: List of broken channels: [] 08:00:14:ST3_smx:INFO: Total # of broken channels: 0 08:00:14:ST3_smx:INFO: List of broken channels: [] 08:00:15:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV] 08:00:15:febtest:INFO: 1-0 | XA-000-08-002-000-000-105-05 | 28.2 | 1212.7 08:00:15:febtest:INFO: 8-1 | XA-000-08-002-000-002-095-15 | 53.6 | 1106.2 08:00:15:febtest:INFO: 3-2 | XA-000-08-002-000-005-094-07 | 34.6 | 1177.4 08:00:15:febtest:INFO: 10-3 | XA-000-08-002-000-005-091-07 | 31.4 | 1189.2 08:00:16:febtest:INFO: 5-4 | XA-000-08-002-000-005-090-07 | 28.2 | 1206.9 08:00:16:febtest:INFO: 12-5 | XA-000-08-002-000-005-088-07 | 21.9 | 1212.7 08:00:16:febtest:INFO: 7-6 | XA-000-08-002-000-002-092-15 | 50.4 | 1141.9 08:00:16:febtest:INFO: 14-7 | XA-000-08-002-000-005-096-14 | 25.1 | 1206.9 ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Sensor TEST_DATE : 2024_02_19-07_58_14 OPERATOR : Alois Alzheimer SITE : GSI SETUP : GSI_TEST_SETUP_1 Set-ID : --------------------------------------- MODULE_NAME : L6DL600127 M6DL6B0001270B2 124 C FEB_SN : 1106 FEB_TYPE : 8.2 FEB_UPLINKS : 2 FEB_A : 1 FEB_B : 0 --------------------------------------- SENSOR_ID: MODULE_NAME: L6DL600127 M6DL6B0001270B2 124 C MODULE_TYPE: MODULE_LADDER: MODULE_MODULE: MODULE_SIZE: 0 MODULE_GRADE: --------------------------------------- VI_before_Init : ['2.450', '0.0003', '1.850', '0.0002', '2.450', '1.9240', '1.850', '0.5293'] VI_after__Init : ['2.450', '0.0003', '1.850', '0.0002', '2.450', '1.9870', '1.850', '0.3175'] VI_at__the_End : ['0', '0', '0', '0', '0', '0'] 08:00:30:ST3_Shared:INFO: Listo of operators:Olga B.; 08:00:32:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1106/TestDate_2024_02_19-07_58_14/ 08:11:51:febtest:INFO: FEB type: 8.2 08:11:51:febtest:INFO: FEB SN: 1101 08:11:51:febtest:INFO: FEB A: 1 08:11:51:febtest:INFO: FEB B: 0 08:12:14:febtest:INFO: FEB type: 8.2 08:12:14:febtest:INFO: FEB SN: 1107 08:12:14:febtest:INFO: FEB A: 1 08:12:14:febtest:INFO: FEB B: 0 08:12:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 08:12:17:ST3_Shared:INFO: -------------------------FEB-Sensor------------------------- 08:12:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo 08:12:34:ST3_ModuleSelector:INFO: L5DL500118 M5DL5B1001181B2 124 C 08:12:34:ST3_ModuleSelector:INFO: 08:12:34:febtest:INFO: Testing FEB with SN 1107 08:12:37:smx_tester:INFO: Scanning setup 08:12:37:elinks:INFO: Disabling clock on downlink 0 08:12:37:elinks:INFO: Disabling clock on downlink 1 08:12:37:elinks:INFO: Disabling clock on downlink 2 08:12:37:elinks:INFO: Disabling clock on downlink 3 08:12:37:elinks:INFO: Disabling clock on downlink 4 08:12:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 08:12:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0] 08:12:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 08:12:37:elinks:INFO: Disabling clock on downlink 0 08:12:37:elinks:INFO: Disabling clock on downlink 1 08:12:37:elinks:INFO: Disabling clock on downlink 2 08:12:37:elinks:INFO: Disabling clock on downlink 3 08:12:37:elinks:INFO: Disabling clock on downlink 4 08:12:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 08:12:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14 08:12:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15 08:12:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 08:12:37:elinks:INFO: Disabling clock on downlink 0 08:12:37:elinks:INFO: Disabling clock on downlink 1 08:12:37:elinks:INFO: Disabling clock on downlink 2 08:12:37:elinks:INFO: Disabling clock on downlink 3 08:12:37:elinks:INFO: Disabling clock on downlink 4 08:12:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 08:12:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2] 08:12:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 08:12:37:elinks:INFO: Disabling clock on downlink 0 08:12:37:elinks:INFO: Disabling clock on downlink 1 08:12:37:elinks:INFO: Disabling clock on downlink 2 08:12:37:elinks:INFO: Disabling clock on downlink 3 08:12:37:elinks:INFO: Disabling clock on downlink 4 08:12:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 08:12:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3] 08:12:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 08:12:37:elinks:INFO: Disabling clock on downlink 0 08:12:37:elinks:INFO: Disabling clock on downlink 1 08:12:37:elinks:INFO: Disabling clock on downlink 2 08:12:37:elinks:INFO: Disabling clock on downlink 3 08:12:37:elinks:INFO: Disabling clock on downlink 4 08:12:37:setup_element:INFO: Checking SOS, encoding_mode: SOS 08:12:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4] 08:12:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection 08:12:38:setup_element:INFO: Scanning clock phase 08:12:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 08:12:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 08:12:38:setup_element:INFO: Clock phase scan results for group 0, downlink 1 08:12:38:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXX_ Clock Delay: 35 08:12:38:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXX_ Clock Delay: 35 08:12:38:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXX_ Clock Delay: 35 08:12:38:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXX_ Clock Delay: 35 08:12:38:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_ Clock Delay: 34 08:12:38:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_ Clock Delay: 34 08:12:38:setup_element:INFO: Eye window for uplink 6 : ______________________________________________________________________XXXXXXX___ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 7 : ______________________________________________________________________XXXXXXX___ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXX___ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXX___ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXXX__ Clock Delay: 33 08:12:38:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXXX__ Clock Delay: 33 08:12:38:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1 08:12:38:setup_element:INFO: Scanning data phases 08:12:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 08:12:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 08:12:43:setup_element:INFO: Data phase scan results for group 0, downlink 1 08:12:43:setup_element:INFO: Eye window for uplink 0 : ____________XXXXX_______________________ Data delay found: 34 08:12:43:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________ Data delay found: 30 08:12:43:setup_element:INFO: Eye window for uplink 2 : ________XXXXX___________________________ Data delay found: 30 08:12:43:setup_element:INFO: Eye window for uplink 3 : _____XXXXX______________________________ Data delay found: 27 08:12:43:setup_element:INFO: Eye window for uplink 4 : _____XXXXXX_____________________________ Data delay found: 27 08:12:43:setup_element:INFO: Eye window for uplink 5 : __XXXX__________________________________ Data delay found: 23 08:12:43:setup_element:INFO: Eye window for uplink 6 : XX___________________________________XXX Data delay found: 19 08:12:43:setup_element:INFO: Eye window for uplink 7 : _________________________________XXXXX__ Data delay found: 15 08:12:43:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________ Data delay found: 6 08:12:43:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____ Data delay found: 12 08:12:43:setup_element:INFO: Eye window for uplink 10: _______________________XXXXXXXXXXXXXXXXX Data delay found: 11 08:12:43:setup_element:INFO: Eye window for uplink 11: _______________________XXXXXXXXXXXXXXXXX Data delay found: 11 08:12:43:setup_element:INFO: Eye window for uplink 12: ____________________________XXXX________ Data delay found: 9 08:12:43:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXX_____ Data delay found: 12 08:12:43:setup_element:INFO: Eye window for uplink 14: _____________________________XXXXX______ Data delay found: 11 08:12:43:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____ Data delay found: 13 08:12:43:setup_element:INFO: Setting the data phase to 34 for uplink 0 08:12:43:setup_element:INFO: Setting the data phase to 30 for uplink 1 08:12:43:setup_element:INFO: Setting the data phase to 30 for uplink 2 08:12:43:setup_element:INFO: Setting the data phase to 27 for uplink 3 08:12:43:setup_element:INFO: Setting the data phase to 27 for uplink 4 08:12:43:setup_element:INFO: Setting the data phase to 23 for uplink 5 08:12:43:setup_element:INFO: Setting the data phase to 19 for uplink 6 08:12:43:setup_element:INFO: Setting the data phase to 15 for uplink 7 08:12:43:setup_element:INFO: Setting the data phase to 6 for uplink 8 08:12:43:setup_element:INFO: Setting the data phase to 12 for uplink 9 08:12:43:setup_element:INFO: Setting the data phase to 11 for uplink 10 08:12:43:setup_element:INFO: Setting the data phase to 11 for uplink 11 08:12:43:setup_element:INFO: Setting the data phase to 9 for uplink 12 08:12:43:setup_element:INFO: Setting the data phase to 12 for uplink 13 08:12:43:setup_element:INFO: Setting the data phase to 11 for uplink 14 08:12:43:setup_element:INFO: Setting the data phase to 13 for uplink 15 08:12:43:ST3_emu:ERROR: [ Setup Element: Group: 0 Downlink: 1 Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ASICs Map: None Clock Phase Characteristic: Optimal Phase: 34 Window Length: 71 Eye Windows: Uplink 0: _________________________________________________________________________XXXXXX_ Uplink 1: _________________________________________________________________________XXXXXX_ Uplink 2: ________________________________________________________________________XXXXXXX_ Uplink 3: ________________________________________________________________________XXXXXXX_ Uplink 4: _______________________________________________________________________XXXXXXXX_ Uplink 5: _______________________________________________________________________XXXXXXXX_ Uplink 6: ______________________________________________________________________XXXXXXX___ Uplink 7: ______________________________________________________________________XXXXXXX___ Uplink 8: ______________________________________________________________________XXXXXXX___ Uplink 9: ______________________________________________________________________XXXXXXX___ Uplink 10: ______________________________________________________________________XXXXXXXX__ Uplink 11: ______________________________________________________________________XXXXXXXX__ Uplink 12: ______________________________________________________________________XXXXXXXX__ Uplink 13: ______________________________________________________________________XXXXXXXX__ Uplink 14: ______________________________________________________________________XXXXXXXX__ Uplink 15: ______________________________________________________________________XXXXXXXX__ Data phase characteristics: Uplink 0: Optimal Phase: 34 Window Length: 35 Eye Window: ____________XXXXX_______________________ Uplink 1: Optimal Phase: 30 Window Length: 35 Eye Window: ________XXXXX___________________________ Uplink 2: Optimal Phase: 30 Window Length: 35 Eye Window: ________XXXXX___________________________ Uplink 3: Optimal Phase: 27 Window Length: 35 Eye Window: _____XXXXX______________________________ Uplink 4: Optimal Phase: 27 Window Length: 34 Eye Window: _____XXXXXX_____________________________ Uplink 5: Optimal Phase: 23 Window Length: 36 Eye Window: __XXXX__________________________________ Uplink 6: Optimal Phase: 19 Window Length: 35 Eye Window: XX___________________________________XXX Uplink 7: Optimal Phase: 15 Window Length: 35 Eye Window: _________________________________XXXXX__ Uplink 8: Optimal Phase: 6 Window Length: 36 Eye Window: _________________________XXXX___________ Uplink 9: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 10: Optimal Phase: 11 Window Length: 23 Eye Window: _______________________XXXXXXXXXXXXXXXXX Uplink 11: Optimal Phase: 11 Window Length: 23 Eye Window: _______________________XXXXXXXXXXXXXXXXX Uplink 12: Optimal Phase: 9 Window Length: 36 Eye Window: ____________________________XXXX________ Uplink 13: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 14: Optimal Phase: 11 Window Length: 35 Eye Window: _____________________________XXXXX______ Uplink 15: Optimal Phase: 13 Window Length: 35 Eye Window: _______________________________XXXXX____ ] 08:12:43:setup_element:INFO: Beginning SMX ASICs map scan 08:12:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 08:12:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 08:12:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1] 08:12:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1] 08:12:43:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] 08:12:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1 08:12:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0 08:12:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8 08:12:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9 08:12:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3 08:12:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2 08:12:44:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10 08:12:44:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11 08:12:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5 08:12:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4 08:12:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12 08:12:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13 08:12:44:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7 08:12:44:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6 08:12:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14 08:12:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15 08:12:46:ST3_emu:ERROR: Setup Element: Group: 0 Downlink: 1 Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] ASICs Map: ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0) ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9) ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2) ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11) ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4) ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13) ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6) ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15) Clock Phase Characteristic: Optimal Phase: 34 Window Length: 71 Eye Windows: Uplink 0: _________________________________________________________________________XXXXXX_ Uplink 1: _________________________________________________________________________XXXXXX_ Uplink 2: ________________________________________________________________________XXXXXXX_ Uplink 3: ________________________________________________________________________XXXXXXX_ Uplink 4: _______________________________________________________________________XXXXXXXX_ Uplink 5: _______________________________________________________________________XXXXXXXX_ Uplink 6: ______________________________________________________________________XXXXXXX___ Uplink 7: ______________________________________________________________________XXXXXXX___ Uplink 8: ______________________________________________________________________XXXXXXX___ Uplink 9: ______________________________________________________________________XXXXXXX___ Uplink 10: ______________________________________________________________________XXXXXXXX__ Uplink 11: ______________________________________________________________________XXXXXXXX__ Uplink 12: ______________________________________________________________________XXXXXXXX__ Uplink 13: ______________________________________________________________________XXXXXXXX__ Uplink 14: ______________________________________________________________________XXXXXXXX__ Uplink 15: ______________________________________________________________________XXXXXXXX__ Data phase characteristics: Uplink 0: Optimal Phase: 34 Window Length: 35 Eye Window: ____________XXXXX_______________________ Uplink 1: Optimal Phase: 30 Window Length: 35 Eye Window: ________XXXXX___________________________ Uplink 2: Optimal Phase: 30 Window Length: 35 Eye Window: ________XXXXX___________________________ Uplink 3: Optimal Phase: 27 Window Length: 35 Eye Window: _____XXXXX______________________________ Uplink 4: Optimal Phase: 27 Window Length: 34 Eye Window: _____XXXXXX_____________________________ Uplink 5: Optimal Phase: 23 Window Length: 36 Eye Window: __XXXX__________________________________ Uplink 6: Optimal Phase: 19 Window Length: 35 Eye Window: XX___________________________________XXX Uplink 7: Optimal Phase: 15 Window Length: 35 Eye Window: _________________________________XXXXX__ Uplink 8: Optimal Phase: 6 Window Length: 36 Eye Window: _________________________XXXX___________ Uplink 9: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 10: Optimal Phase: 11 Window Length: 23 Eye Window: _______________________XXXXXXXXXXXXXXXXX Uplink 11: Optimal Phase: 11 Window Length: 23 Eye Window: _______________________XXXXXXXXXXXXXXXXX Uplink 12: Optimal Phase: 9 Window Length: 36 Eye Window: ____________________________XXXX________ Uplink 13: Optimal Phase: 12 Window Length: 35 Eye Window: ______________________________XXXXX_____ Uplink 14: Optimal Phase: 11 Window Length: 35 Eye Window: _____________________________XXXXX______ Uplink 15: Optimal Phase: 13 Window Length: 35 Eye Window: _______________________________XXXXX____ 08:12:46:setup_element:INFO: Performing Elink synchronization 08:12:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1] 08:12:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1] 08:12:46:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1] 08:12:46:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1] 08:12:46:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1 08:12:46:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] 08:12:46:ST3_emu:INFO: Number of chips: 8 addr | upli | dwnli | grp | uplinks | uplinks_map 0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)] 1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)] 2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)] 3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)] 4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)] 5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)] 6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)] 7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)] TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0_1 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0_1 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_0__upli_1 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_8 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_8 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_1__upli_8 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_2_3 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_2_3 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_2__upli_3 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3_10 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3_10 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_3__upli_10 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_4_5 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_4_5 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_4__upli_5 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5_12 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5_12 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_5__upli_12 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_6_7 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_6_7 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_6__upli_7 TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7_14 (Potential memory leak). TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7_14 (Potential memory leak). TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_7__upli_14 FEB type: A FEB_A: 1 FEB_B: 0 08:12:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV] 08:12:47:febtest:INFO: 1-0 | XA-000-08-002-000-007-236-07 | 15.6 | 1224.5 08:12:47:febtest:INFO: 8-1 | XA-000-08-002-001-006-120-15 | 53.6 | 1082.3 08:12:48:febtest:INFO: 3-2 | XA-000-08-002-000-008-007-02 | 21.9 | 1206.9 08:12:48:febtest:INFO: 10-3 | XA-000-08-002-001-006-118-15 | 18.7 | 1195.1 08:12:48:febtest:INFO: 5-4 | XA-000-08-002-000-008-022-05 | 9.3 | 1247.9 08:12:48:febtest:INFO: 12-5 | XA-000-08-002-001-006-115-15 | 21.9 | 1189.2 08:12:48:febtest:INFO: 7-6 | XA-000-08-002-001-008-107-01 | 15.6 | 1236.2 08:12:49:febtest:INFO: 14-7 | XA-000-08-002-001-006-135-09 | 21.9 | 1201.0 08:12:49:ST3_smx:INFO: Configuring SMX FAST 08:12:51:ST3_smx:INFO: chip: 1-0 18.745682 C 1212.728715 mV 08:12:51:ST3_smx:INFO: Electrons 08:12:51:ST3_smx:INFO: # loops 0 08:12:53:ST3_smx:INFO: # loops 1 08:12:55:ST3_smx:INFO: # loops 2 08:12:56:ST3_smx:INFO: # loops 3 08:12:58:ST3_smx:INFO: # loops 4 08:12:59:ST3_smx:INFO: Total # of broken channels: 0 08:12:59:ST3_smx:INFO: List of broken channels: [] 08:12:59:ST3_smx:INFO: Total # of broken channels: 0 08:12:59:ST3_smx:INFO: List of broken channels: [] 08:13:00:ST3_smx:INFO: Configuring SMX FAST 08:13:02:ST3_smx:INFO: chip: 8-1 50.430383 C 1100.211760 mV 08:13:02:ST3_smx:INFO: Electrons 08:13:02:ST3_smx:INFO: # loops 0 08:13:03:ST3_smx:INFO: # loops 1 08:13:05:ST3_smx:INFO: # loops 2 08:13:06:ST3_smx:INFO: # loops 3 08:13:08:ST3_smx:INFO: # loops 4 08:13:10:ST3_smx:INFO: Total # of broken channels: 0 08:13:10:ST3_smx:INFO: List of broken channels: [] 08:13:10:ST3_smx:INFO: Total # of broken channels: 0 08:13:10:ST3_smx:INFO: List of broken channels: [] 08:13:10:ST3_smx:INFO: Configuring SMX FAST 08:13:12:ST3_smx:INFO: chip: 3-2 31.389742 C 1177.390875 mV 08:13:12:ST3_smx:INFO: Electrons 08:13:12:ST3_smx:INFO: # loops 0 08:13:13:ST3_smx:INFO: # loops 1 08:13:15:ST3_smx:INFO: # loops 2 08:13:16:ST3_smx:INFO: # loops 3 08:13:18:ST3_smx:INFO: # loops 4 08:13:20:ST3_smx:INFO: Total # of broken channels: 3 08:13:20:ST3_smx:INFO: List of broken channels: [0, 79, 90] 08:13:20:ST3_smx:INFO: Total # of broken channels: 4 08:13:20:ST3_smx:INFO: List of broken channels: [0, 79, 90, 127] 08:13:20:ST3_smx:INFO: Configuring SMX FAST 08:13:22:ST3_smx:INFO: chip: 10-3 25.062742 C 1189.190035 mV 08:13:22:ST3_smx:INFO: Electrons 08:13:22:ST3_smx:INFO: # loops 0 08:13:23:ST3_smx:INFO: # loops 1 08:13:25:ST3_smx:INFO: # loops 2 08:13:26:ST3_smx:INFO: # loops 3 08:13:28:ST3_smx:INFO: # loops 4 08:13:30:ST3_smx:INFO: Total # of broken channels: 0 08:13:30:ST3_smx:INFO: List of broken channels: [] 08:13:30:ST3_smx:INFO: Total # of broken channels: 0 08:13:30:ST3_smx:INFO: List of broken channels: [] 08:13:30:ST3_smx:INFO: Configuring SMX FAST 08:13:32:ST3_smx:INFO: chip: 5-4 12.438562 C 1247.887635 mV 08:13:32:ST3_smx:INFO: Electrons 08:13:32:ST3_smx:INFO: # loops 0 08:13:33:ST3_smx:INFO: # loops 1 08:13:35:ST3_smx:INFO: # loops 2 08:13:37:ST3_smx:INFO: # loops 3 08:13:38:ST3_smx:INFO: # loops 4 08:13:40:ST3_smx:INFO: Total # of broken channels: 0 08:13:40:ST3_smx:INFO: List of broken channels: [] 08:13:40:ST3_smx:INFO: Total # of broken channels: 0 08:13:40:ST3_smx:INFO: List of broken channels: [] 08:13:40:ST3_smx:INFO: Configuring SMX FAST 08:13:42:ST3_smx:INFO: chip: 12-5 28.225000 C 1177.390875 mV 08:13:42:ST3_smx:INFO: Electrons 08:13:42:ST3_smx:INFO: # loops 0 08:13:43:ST3_smx:INFO: # loops 1 08:13:45:ST3_smx:INFO: # loops 2 08:13:47:ST3_smx:INFO: # loops 3 08:13:48:ST3_smx:INFO: # loops 4 08:13:50:ST3_smx:INFO: Total # of broken channels: 0 08:13:50:ST3_smx:INFO: List of broken channels: [] 08:13:50:ST3_smx:INFO: Total # of broken channels: 0 08:13:50:ST3_smx:INFO: List of broken channels: [] 08:13:50:ST3_smx:INFO: Configuring SMX FAST 08:13:52:ST3_smx:INFO: chip: 7-6 21.902970 C 1206.851500 mV 08:13:52:ST3_smx:INFO: Electrons 08:13:52:ST3_smx:INFO: # loops 0 08:13:53:ST3_smx:INFO: # loops 1 08:13:55:ST3_smx:INFO: # loops 2 08:13:57:ST3_smx:INFO: # loops 3 08:13:58:ST3_smx:INFO: # loops 4 08:14:00:ST3_smx:INFO: Total # of broken channels: 0 08:14:00:ST3_smx:INFO: List of broken channels: [] 08:14:00:ST3_smx:INFO: Total # of broken channels: 0 08:14:00:ST3_smx:INFO: List of broken channels: [] 08:14:00:ST3_smx:INFO: Configuring SMX FAST 08:14:02:ST3_smx:INFO: chip: 14-7 21.902970 C 1200.969315 mV 08:14:02:ST3_smx:INFO: Electrons 08:14:02:ST3_smx:INFO: # loops 0 08:14:03:ST3_smx:INFO: # loops 1 08:14:05:ST3_smx:INFO: # loops 2 08:14:07:ST3_smx:INFO: # loops 3 08:14:08:ST3_smx:INFO: # loops 4 08:14:10:ST3_smx:INFO: Total # of broken channels: 0 08:14:10:ST3_smx:INFO: List of broken channels: [] 08:14:10:ST3_smx:INFO: Total # of broken channels: 0 08:14:10:ST3_smx:INFO: List of broken channels: [] 08:14:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV] 08:14:11:febtest:INFO: 1-0 | XA-000-08-002-000-007-236-07 | 21.9 | 1212.7 08:14:11:febtest:INFO: 8-1 | XA-000-08-002-001-006-120-15 | 50.4 | 1106.2 08:14:11:febtest:INFO: 3-2 | XA-000-08-002-000-008-007-02 | 31.4 | 1177.4 08:14:12:febtest:INFO: 10-3 | XA-000-08-002-001-006-118-15 | 25.1 | 1189.2 08:14:12:febtest:INFO: 5-4 | XA-000-08-002-000-008-022-05 | 12.4 | 1253.7 08:14:12:febtest:INFO: 12-5 | XA-000-08-002-001-006-115-15 | 28.2 | 1177.4 08:14:12:febtest:INFO: 7-6 | XA-000-08-002-001-008-107-01 | 21.9 | 1212.7 08:14:13:febtest:INFO: 14-7 | XA-000-08-002-001-006-135-09 | 25.1 | 1206.9 ############################################################ # S U M M A R Y # ############################################################ TEST_NAME : FEB-Sensor TEST_DATE : 2024_02_21-08_12_17 OPERATOR : Olga B.; SITE : GSI SETUP : GSI_TEST_SETUP_1 Set-ID : --------------------------------------- MODULE_NAME : L5DL500118 M5DL5B1001181B2 124 C FEB_SN : 1107 FEB_TYPE : 8.2 FEB_UPLINKS : 2 FEB_A : 1 FEB_B : 0 --------------------------------------- SENSOR_ID: MODULE_NAME: L5DL500118 M5DL5B1001181B2 124 C MODULE_TYPE: MODULE_LADDER: MODULE_MODULE: MODULE_SIZE: 0 MODULE_GRADE: --------------------------------------- VI_before_Init : ['2.450', '0.0003', '1.850', '0.0000', '2.450', '1.8840', '1.850', '0.5065'] VI_after__Init : ['2.450', '0.0003', '1.850', '0.0000', '2.450', '1.9840', '1.850', '0.3191'] VI_at__the_End : ['0', '0', '0', '0', '0', '0'] 08:15:54:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_1107/TestDate_2024_02_21-08_12_17/