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FEB_1150 04.04.24 11:11:13
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11:11:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:11:13:ST3_Shared:INFO: FEB-ASIC
11:11:13:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:11:13:febtest:INFO: Testing FEB with SN 1150
11:11:16:smx_tester:INFO: Scanning setup
11:11:16:elinks:INFO: Disabling clock on downlink 0
11:11:16:elinks:INFO: Disabling clock on downlink 1
11:11:16:elinks:INFO: Disabling clock on downlink 2
11:11:16:elinks:INFO: Disabling clock on downlink 3
11:11:16:elinks:INFO: Disabling clock on downlink 4
11:11:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:11:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:11:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:11:16:elinks:INFO: Disabling clock on downlink 0
11:11:16:elinks:INFO: Disabling clock on downlink 1
11:11:16:elinks:INFO: Disabling clock on downlink 2
11:11:16:elinks:INFO: Disabling clock on downlink 3
11:11:16:elinks:INFO: Disabling clock on downlink 4
11:11:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:11:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
11:11:16:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
11:11:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:11:16:elinks:INFO: Disabling clock on downlink 0
11:11:16:elinks:INFO: Disabling clock on downlink 1
11:11:16:elinks:INFO: Disabling clock on downlink 2
11:11:16:elinks:INFO: Disabling clock on downlink 3
11:11:16:elinks:INFO: Disabling clock on downlink 4
11:11:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:11:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:11:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:11:16:elinks:INFO: Disabling clock on downlink 0
11:11:16:elinks:INFO: Disabling clock on downlink 1
11:11:16:elinks:INFO: Disabling clock on downlink 2
11:11:16:elinks:INFO: Disabling clock on downlink 3
11:11:16:elinks:INFO: Disabling clock on downlink 4
11:11:16:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:11:16:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:11:16:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:11:17:elinks:INFO: Disabling clock on downlink 0
11:11:17:elinks:INFO: Disabling clock on downlink 1
11:11:17:elinks:INFO: Disabling clock on downlink 2
11:11:17:elinks:INFO: Disabling clock on downlink 3
11:11:17:elinks:INFO: Disabling clock on downlink 4
11:11:17:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:11:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:11:17:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:11:17:setup_element:INFO: Scanning clock phase
11:11:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:11:17:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:11:17:setup_element:INFO: Clock phase scan results for group 0, downlink 1
11:11:17:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:11:17:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
11:11:17:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:11:17:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:11:17:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:11:17:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:11:17:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:11:17:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
11:11:17:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:11:17:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:11:17:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:11:17:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:11:17:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:11:17:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:11:17:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:11:17:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:11:17:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
11:11:17:setup_element:INFO: Scanning data phases
11:11:17:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:11:17:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:11:23:setup_element:INFO: Data phase scan results for group 0, downlink 1
11:11:23:setup_element:INFO: Eye window for uplink 0 : ______________XXXXX________XXXXXXXXXXXXX
Data delay found: 6
11:11:23:setup_element:INFO: Eye window for uplink 1 : _________XXXXXX____________XXXXXXXXXXXXX
Data delay found: 20
11:11:23:setup_element:INFO: Eye window for uplink 2 : _________XXXXX__________________________
Data delay found: 31
11:11:23:setup_element:INFO: Eye window for uplink 3 : _______XXXX_____________________________
Data delay found: 28
11:11:23:setup_element:INFO: Eye window for uplink 4 : _______XXXXX____________________________
Data delay found: 29
11:11:23:setup_element:INFO: Eye window for uplink 5 : ___XXXX_________________________________
Data delay found: 24
11:11:23:setup_element:INFO: Eye window for uplink 6 : XX___________________________________XXX
Data delay found: 19
11:11:23:setup_element:INFO: Eye window for uplink 7 : _________________________________XXXXX__
Data delay found: 15
11:11:23:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________
Data delay found: 6
11:11:23:setup_element:INFO: Eye window for uplink 9 : _____________________________XXXXXX_____
Data delay found: 11
11:11:23:setup_element:INFO: Eye window for uplink 10: ___________________________XXXXX________
Data delay found: 9
11:11:23:setup_element:INFO: Eye window for uplink 11: _______________________________XXXX_____
Data delay found: 12
11:11:23:setup_element:INFO: Eye window for uplink 12: _____________________________XXXXX______
Data delay found: 11
11:11:23:setup_element:INFO: Eye window for uplink 13: ________________________________XXXXX___
Data delay found: 14
11:11:23:setup_element:INFO: Eye window for uplink 14: _____________________________XXXXX______
Data delay found: 11
11:11:23:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
11:11:23:setup_element:INFO: Setting the data phase to 6 for uplink 0
11:11:23:setup_element:INFO: Setting the data phase to 20 for uplink 1
11:11:23:setup_element:INFO: Setting the data phase to 31 for uplink 2
11:11:23:setup_element:INFO: Setting the data phase to 28 for uplink 3
11:11:23:setup_element:INFO: Setting the data phase to 29 for uplink 4
11:11:23:setup_element:INFO: Setting the data phase to 24 for uplink 5
11:11:23:setup_element:INFO: Setting the data phase to 19 for uplink 6
11:11:23:setup_element:INFO: Setting the data phase to 15 for uplink 7
11:11:23:setup_element:INFO: Setting the data phase to 6 for uplink 8
11:11:23:setup_element:INFO: Setting the data phase to 11 for uplink 9
11:11:23:setup_element:INFO: Setting the data phase to 9 for uplink 10
11:11:23:setup_element:INFO: Setting the data phase to 12 for uplink 11
11:11:23:setup_element:INFO: Setting the data phase to 11 for uplink 12
11:11:23:setup_element:INFO: Setting the data phase to 14 for uplink 13
11:11:23:setup_element:INFO: Setting the data phase to 11 for uplink 14
11:11:23:setup_element:INFO: Setting the data phase to 13 for uplink 15
11:11:23:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: ________________________________________________________________________XXXXXXX_
Uplink 5: ________________________________________________________________________XXXXXXX_
Uplink 6: _______________________________________________________________________XXXXXX___
Uplink 7: _______________________________________________________________________XXXXXX___
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _____________________________________________________________________XXXXXXXXX__
Uplink 11: _____________________________________________________________________XXXXXXXXX__
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 6
Window Length: 14
Eye Window: ______________XXXXX________XXXXXXXXXXXXX
Uplink 1:
Optimal Phase: 20
Window Length: 12
Eye Window: _________XXXXXX____________XXXXXXXXXXXXX
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 10:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 12:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 13:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 14:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
]
11:11:23:setup_element:INFO: Beginning SMX ASICs map scan
11:11:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:11:23:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:11:23:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:11:23:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:11:23:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:11:23:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
11:11:23:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
11:11:23:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
11:11:23:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
11:11:23:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
11:11:23:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
11:11:23:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
11:11:23:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
11:11:24:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
11:11:24:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
11:11:24:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
11:11:24:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
11:11:24:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
11:11:24:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
11:11:24:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
11:11:24:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
11:11:25:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: ________________________________________________________________________XXXXXXX_
Uplink 5: ________________________________________________________________________XXXXXXX_
Uplink 6: _______________________________________________________________________XXXXXX___
Uplink 7: _______________________________________________________________________XXXXXX___
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _____________________________________________________________________XXXXXXXXX__
Uplink 11: _____________________________________________________________________XXXXXXXXX__
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 6
Window Length: 14
Eye Window: ______________XXXXX________XXXXXXXXXXXXX
Uplink 1:
Optimal Phase: 20
Window Length: 12
Eye Window: _________XXXXXX____________XXXXXXXXXXXXX
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 7:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 10:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 12:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 13:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 14:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
11:11:25:setup_element:INFO: Performing Elink synchronization
11:11:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:11:26:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:11:26:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:11:26:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:11:26:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
11:11:26:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:11:26:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
FEB type: A FEB_A: 1 FEB_B: 0
11:11:27:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:11:27:febtest:INFO: 01-00 | XA-000-08-002-002-006-024-05 | 21.9 | 1218.6
11:11:27:febtest:INFO: 08-01 | XA-000-08-002-001-008-254-12 | 25.1 | 1230.3
11:11:27:febtest:INFO: 03-02 | XA-000-08-002-002-006-150-15 | 28.2 | 1218.6
11:11:28:febtest:INFO: 10-03 | XA-000-08-002-002-006-016-05 | 34.6 | 1195.1
11:11:28:febtest:INFO: 05-04 | XA-000-08-002-002-006-019-05 | 31.4 | 1212.7
11:11:28:febtest:INFO: 12-05 | XA-000-08-002-001-008-178-09 | 34.6 | 1224.5
11:11:28:febtest:INFO: 07-06 | XA-000-08-002-001-008-255-12 | 34.6 | 1195.1
11:11:29:febtest:INFO: 14-07 | XA-000-08-002-001-008-194-05 | 37.7 | 1177.4
11:11:29:ST3_smx:INFO: Configuring SMX FAST
11:11:31:ST3_smx:INFO: chip: 1-0 28.225000 C 1206.851500 mV
11:11:31:ST3_smx:INFO: Electrons
11:11:31:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:33:ST3_smx:INFO: ----> Checking Analog response
11:11:33:ST3_smx:INFO: ----> Checking broken channels
11:11:33:ST3_smx:INFO: Total # broken ch: 0
11:11:33:ST3_smx:INFO: List FAST: []
11:11:33:ST3_smx:INFO: List SLOW: []
11:11:33:ST3_smx:INFO: Holes
11:11:33:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:35:ST3_smx:INFO: ----> Checking Analog response
11:11:35:ST3_smx:INFO: ----> Checking broken channels
11:11:35:ST3_smx:INFO: Total # broken ch: 0
11:11:35:ST3_smx:INFO: List FAST: []
11:11:35:ST3_smx:INFO: List SLOW: []
11:11:36:ST3_smx:INFO: Configuring SMX FAST
11:11:38:ST3_smx:INFO: chip: 8-1 31.389742 C 1206.851500 mV
11:11:38:ST3_smx:INFO: Electrons
11:11:38:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:39:ST3_smx:INFO: ----> Checking Analog response
11:11:39:ST3_smx:INFO: ----> Checking broken channels
11:11:40:ST3_smx:INFO: Total # broken ch: 0
11:11:40:ST3_smx:INFO: List FAST: []
11:11:40:ST3_smx:INFO: List SLOW: []
11:11:40:ST3_smx:INFO: Holes
11:11:40:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:42:ST3_smx:INFO: ----> Checking Analog response
11:11:42:ST3_smx:INFO: ----> Checking broken channels
11:11:42:ST3_smx:INFO: Total # broken ch: 0
11:11:42:ST3_smx:INFO: List FAST: []
11:11:42:ST3_smx:INFO: List SLOW: []
11:11:42:ST3_smx:INFO: Configuring SMX FAST
11:11:44:ST3_smx:INFO: chip: 3-2 31.389742 C 1206.851500 mV
11:11:44:ST3_smx:INFO: Electrons
11:11:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:46:ST3_smx:INFO: ----> Checking Analog response
11:11:46:ST3_smx:INFO: ----> Checking broken channels
11:11:47:ST3_smx:INFO: Total # broken ch: 0
11:11:47:ST3_smx:INFO: List FAST: []
11:11:47:ST3_smx:INFO: List SLOW: []
11:11:47:ST3_smx:INFO: Holes
11:11:47:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:49:ST3_smx:INFO: ----> Checking Analog response
11:11:49:ST3_smx:INFO: ----> Checking broken channels
11:11:49:ST3_smx:INFO: Total # broken ch: 0
11:11:49:ST3_smx:INFO: List FAST: []
11:11:49:ST3_smx:INFO: List SLOW: []
11:11:49:ST3_smx:INFO: Configuring SMX FAST
11:11:51:ST3_smx:INFO: chip: 10-3 34.556970 C 1206.851500 mV
11:11:51:ST3_smx:INFO: Electrons
11:11:51:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:53:ST3_smx:INFO: ----> Checking Analog response
11:11:53:ST3_smx:INFO: ----> Checking broken channels
11:11:53:ST3_smx:INFO: Total # broken ch: 0
11:11:53:ST3_smx:INFO: List FAST: []
11:11:53:ST3_smx:INFO: List SLOW: []
11:11:53:ST3_smx:INFO: Holes
11:11:53:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:11:55:ST3_smx:INFO: ----> Checking Analog response
11:11:55:ST3_smx:INFO: ----> Checking broken channels
11:11:56:ST3_smx:INFO: Total # broken ch: 0
11:11:56:ST3_smx:INFO: List FAST: []
11:11:56:ST3_smx:INFO: List SLOW: []
11:11:56:ST3_smx:INFO: Configuring SMX FAST
11:11:58:ST3_smx:INFO: chip: 5-4 31.389742 C 1218.600960 mV
11:11:58:ST3_smx:INFO: Electrons
11:11:58:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:00:ST3_smx:INFO: ----> Checking Analog response
11:12:00:ST3_smx:INFO: ----> Checking broken channels
11:12:00:ST3_smx:INFO: Total # broken ch: 0
11:12:00:ST3_smx:INFO: List FAST: []
11:12:00:ST3_smx:INFO: List SLOW: []
11:12:00:ST3_smx:INFO: Holes
11:12:00:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:02:ST3_smx:INFO: ----> Checking Analog response
11:12:02:ST3_smx:INFO: ----> Checking broken channels
11:12:03:ST3_smx:INFO: Total # broken ch: 0
11:12:03:ST3_smx:INFO: List FAST: []
11:12:03:ST3_smx:INFO: List SLOW: []
11:12:03:ST3_smx:INFO: Configuring SMX FAST
11:12:05:ST3_smx:INFO: chip: 12-5 31.389742 C 1247.887635 mV
11:12:05:ST3_smx:INFO: Electrons
11:12:05:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:07:ST3_smx:INFO: ----> Checking Analog response
11:12:07:ST3_smx:INFO: ----> Checking broken channels
11:12:07:ST3_smx:INFO: Total # broken ch: 0
11:12:07:ST3_smx:INFO: List FAST: []
11:12:07:ST3_smx:INFO: List SLOW: []
11:12:07:ST3_smx:INFO: Holes
11:12:07:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:09:ST3_smx:INFO: ----> Checking Analog response
11:12:09:ST3_smx:INFO: ----> Checking broken channels
11:12:09:ST3_smx:INFO: Total # broken ch: 0
11:12:09:ST3_smx:INFO: List FAST: []
11:12:09:ST3_smx:INFO: List SLOW: []
11:12:10:ST3_smx:INFO: Configuring SMX FAST
11:12:12:ST3_smx:INFO: chip: 7-6 47.250730 C 1159.654860 mV
11:12:12:ST3_smx:INFO: Electrons
11:12:12:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:14:ST3_smx:INFO: ----> Checking Analog response
11:12:14:ST3_smx:INFO: ----> Checking broken channels
11:12:14:ST3_smx:INFO: Total # broken ch: 0
11:12:14:ST3_smx:INFO: List FAST: []
11:12:14:ST3_smx:INFO: List SLOW: []
11:12:14:ST3_smx:INFO: Holes
11:12:14:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:16:ST3_smx:INFO: ----> Checking Analog response
11:12:16:ST3_smx:INFO: ----> Checking broken channels
11:12:16:ST3_smx:INFO: Total # broken ch: 0
11:12:16:ST3_smx:INFO: List FAST: []
11:12:16:ST3_smx:INFO: List SLOW: []
11:12:17:ST3_smx:INFO: Configuring SMX FAST
11:12:19:ST3_smx:INFO: chip: 14-7 44.073563 C 1159.654860 mV
11:12:19:ST3_smx:INFO: Electrons
11:12:19:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:21:ST3_smx:INFO: ----> Checking Analog response
11:12:21:ST3_smx:INFO: ----> Checking broken channels
11:12:21:ST3_smx:INFO: Total # broken ch: 0
11:12:21:ST3_smx:INFO: List FAST: []
11:12:21:ST3_smx:INFO: List SLOW: []
11:12:21:ST3_smx:INFO: Holes
11:12:21:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
11:12:23:ST3_smx:INFO: ----> Checking Analog response
11:12:23:ST3_smx:INFO: ----> Checking broken channels
11:12:23:ST3_smx:INFO: Total # broken ch: 0
11:12:23:ST3_smx:INFO: List FAST: []
11:12:23:ST3_smx:INFO: List SLOW: []
11:12:24:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:12:24:febtest:INFO: 01-00 | XA-000-08-002-002-006-024-05 | 28.2 | 1206.9
11:12:24:febtest:INFO: 08-01 | XA-000-08-002-001-008-254-12 | 34.6 | 1206.9
11:12:25:febtest:INFO: 03-02 | XA-000-08-002-002-006-150-15 | 34.6 | 1206.9
11:12:25:febtest:INFO: 10-03 | XA-000-08-002-002-006-016-05 | 34.6 | 1206.9
11:12:25:febtest:INFO: 05-04 | XA-000-08-002-002-006-019-05 | 31.4 | 1218.6
11:12:25:febtest:INFO: 12-05 | XA-000-08-002-001-008-178-09 | 31.4 | 1242.0
11:12:25:febtest:INFO: 07-06 | XA-000-08-002-001-008-255-12 | 50.4 | 1153.7
11:12:26:febtest:INFO: 14-07 | XA-000-08-002-001-008-194-05 | 47.3 | 1153.7
############################################################
# S U M M A R Y #
############################################################
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_04_04-11_11_13
OPERATOR : Oleksandr S.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 1150
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.450', '1.4380', '1.849', '2.6200', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0120', '1.850', '0.4840', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '2.0090', '1.850', '0.3197', '0.000', '0.0000', '0.000', '0.0000']
Comment.txt
Test FEB from EE with ASICs ADC not 0