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FEB_1166 04.06.24 08:02:38
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08:02:38:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:02:38:ST3_Shared:INFO: FEB-Sensor
08:02:38:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:02:57:ST3_ModuleSelector:INFO: L4DL000161 M4DL0T3001613A2 124 C
08:02:57:ST3_ModuleSelector:INFO: 23094
08:02:57:febtest:INFO: Testing FEB with SN 1166
08:02:58:smx_tester:INFO: Scanning setup
08:02:58:elinks:INFO: Disabling clock on downlink 0
08:02:58:elinks:INFO: Disabling clock on downlink 1
08:02:58:elinks:INFO: Disabling clock on downlink 2
08:02:58:elinks:INFO: Disabling clock on downlink 3
08:02:58:elinks:INFO: Disabling clock on downlink 4
08:02:58:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:02:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:02:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:02:59:elinks:INFO: Disabling clock on downlink 0
08:02:59:elinks:INFO: Disabling clock on downlink 1
08:02:59:elinks:INFO: Disabling clock on downlink 2
08:02:59:elinks:INFO: Disabling clock on downlink 3
08:02:59:elinks:INFO: Disabling clock on downlink 4
08:02:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:02:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:02:59:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:02:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:02:59:elinks:INFO: Disabling clock on downlink 0
08:02:59:elinks:INFO: Disabling clock on downlink 1
08:02:59:elinks:INFO: Disabling clock on downlink 2
08:02:59:elinks:INFO: Disabling clock on downlink 3
08:02:59:elinks:INFO: Disabling clock on downlink 4
08:02:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:02:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:02:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:02:59:elinks:INFO: Disabling clock on downlink 0
08:02:59:elinks:INFO: Disabling clock on downlink 1
08:02:59:elinks:INFO: Disabling clock on downlink 2
08:02:59:elinks:INFO: Disabling clock on downlink 3
08:02:59:elinks:INFO: Disabling clock on downlink 4
08:02:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:02:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:02:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:02:59:elinks:INFO: Disabling clock on downlink 0
08:02:59:elinks:INFO: Disabling clock on downlink 1
08:02:59:elinks:INFO: Disabling clock on downlink 2
08:02:59:elinks:INFO: Disabling clock on downlink 3
08:02:59:elinks:INFO: Disabling clock on downlink 4
08:02:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:02:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:02:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:02:59:setup_element:INFO: Scanning clock phase
08:02:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:02:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:03:00:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:03:00:setup_element:INFO: Eye window for uplink 0 : ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 1 : ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 8 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 9 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:03:00:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:03:00:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:03:00:setup_element:INFO: Eye window for uplink 12: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:03:00:setup_element:INFO: Eye window for uplink 13: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:03:00:setup_element:INFO: Eye window for uplink 14: _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:03:00:setup_element:INFO: Eye window for uplink 15: _________________________________________________________________________XXXXXX_
Clock Delay: 35
08:03:00:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
08:03:00:setup_element:INFO: Scanning data phases
08:03:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:03:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:03:05:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:03:05:setup_element:INFO: Eye window for uplink 0 : ___________XXXXX________________________
Data delay found: 33
08:03:05:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________
Data delay found: 29
08:03:05:setup_element:INFO: Eye window for uplink 2 : ___________XXXX_________________________
Data delay found: 32
08:03:05:setup_element:INFO: Eye window for uplink 3 : ________XXXXX___________________________
Data delay found: 30
08:03:05:setup_element:INFO: Eye window for uplink 4 : _________XXXXX__________________________
Data delay found: 31
08:03:05:setup_element:INFO: Eye window for uplink 5 : _____XXXXX______________________________
Data delay found: 27
08:03:05:setup_element:INFO: Eye window for uplink 6 : _XXXXX__________________________________
Data delay found: 23
08:03:05:setup_element:INFO: Eye window for uplink 7 : XXX_________________________________XXXX
Data delay found: 19
08:03:05:setup_element:INFO: Eye window for uplink 8 : ____________________________XXXX________
Data delay found: 9
08:03:05:setup_element:INFO: Eye window for uplink 9 : ________________________________XXXXXX__
Data delay found: 14
08:03:05:setup_element:INFO: Eye window for uplink 10: ____________________________XXXXX_______
Data delay found: 10
08:03:05:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXX____
Data delay found: 13
08:03:05:setup_element:INFO: Eye window for uplink 12: ___________________________XXXX_________
Data delay found: 8
08:03:05:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXX_____
Data delay found: 12
08:03:05:setup_element:INFO: Eye window for uplink 14: _______________________________XXXXX____
Data delay found: 13
08:03:05:setup_element:INFO: Eye window for uplink 15: _________________________________XXXXXX_
Data delay found: 15
08:03:05:setup_element:INFO: Setting the data phase to 33 for uplink 0
08:03:05:setup_element:INFO: Setting the data phase to 29 for uplink 1
08:03:05:setup_element:INFO: Setting the data phase to 32 for uplink 2
08:03:05:setup_element:INFO: Setting the data phase to 30 for uplink 3
08:03:05:setup_element:INFO: Setting the data phase to 31 for uplink 4
08:03:05:setup_element:INFO: Setting the data phase to 27 for uplink 5
08:03:05:setup_element:INFO: Setting the data phase to 23 for uplink 6
08:03:05:setup_element:INFO: Setting the data phase to 19 for uplink 7
08:03:05:setup_element:INFO: Setting the data phase to 9 for uplink 8
08:03:05:setup_element:INFO: Setting the data phase to 14 for uplink 9
08:03:05:setup_element:INFO: Setting the data phase to 10 for uplink 10
08:03:05:setup_element:INFO: Setting the data phase to 13 for uplink 11
08:03:05:setup_element:INFO: Setting the data phase to 8 for uplink 12
08:03:05:setup_element:INFO: Setting the data phase to 12 for uplink 13
08:03:05:setup_element:INFO: Setting the data phase to 13 for uplink 14
08:03:05:setup_element:INFO: Setting the data phase to 15 for uplink 15
08:03:05:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 0: ______________________________________________________________________XXXXXXXXX_
Uplink 1: ______________________________________________________________________XXXXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: _______________________________________________________________________XXXXXXXX_
Uplink 7: _______________________________________________________________________XXXXXXXX_
Uplink 8: _______________________________________________________________________XXXXXXX__
Uplink 9: _______________________________________________________________________XXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: _____________________________________________________________________XXXXXXXX___
Uplink 13: _____________________________________________________________________XXXXXXXX___
Uplink 14: _________________________________________________________________________XXXXXX_
Uplink 15: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 32
Window Length: 36
Eye Window: ___________XXXX_________________________
Uplink 3:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 4:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 5:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 6:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 7:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 8:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 9:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 10:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 15:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
]
08:03:05:setup_element:INFO: Beginning SMX ASICs map scan
08:03:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:03:05:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:03:05:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:03:05:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:03:05:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:03:05:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:03:05:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:03:06:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:03:06:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:03:06:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:03:06:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:03:06:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:03:06:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:03:06:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:03:06:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:03:06:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:03:06:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:03:07:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:03:07:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:03:07:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:03:07:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:03:08:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 0: ______________________________________________________________________XXXXXXXXX_
Uplink 1: ______________________________________________________________________XXXXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: _______________________________________________________________________XXXXXXXX_
Uplink 7: _______________________________________________________________________XXXXXXXX_
Uplink 8: _______________________________________________________________________XXXXXXX__
Uplink 9: _______________________________________________________________________XXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: _____________________________________________________________________XXXXXXXX___
Uplink 13: _____________________________________________________________________XXXXXXXX___
Uplink 14: _________________________________________________________________________XXXXXX_
Uplink 15: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 32
Window Length: 36
Eye Window: ___________XXXX_________________________
Uplink 3:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 4:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 5:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 6:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 7:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 8:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 9:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 10:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 11:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 12:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 15:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
08:03:08:setup_element:INFO: Performing Elink synchronization
08:03:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:03:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:03:08:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:03:08:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:03:08:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:03:08:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:03:08:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
08:03:09:febtest:INFO: Init all SMX (CSA): 30
08:03:22:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:03:23:febtest:INFO: 01-00 | XA-000-08-002-002-006-100-09 | 18.7 | 1195.1
08:03:23:febtest:INFO: 08-01 | XA-000-08-002-002-006-076-07 | 25.1 | 1165.6
08:03:23:febtest:INFO: 03-02 | XA-000-08-002-002-006-090-00 | 31.4 | 1153.7
08:03:23:febtest:INFO: 10-03 | XA-000-08-002-002-006-066-07 | 18.7 | 1189.2
08:03:24:febtest:INFO: 05-04 | XA-000-08-002-002-006-067-07 | 34.6 | 1153.7
08:03:24:febtest:INFO: 12-05 | XA-000-08-002-002-006-096-09 | 12.4 | 1212.7
08:03:24:febtest:INFO: 07-06 | XA-000-08-002-002-006-071-07 | 31.4 | 1153.7
08:03:24:febtest:INFO: 14-07 | XA-000-08-002-002-006-095-00 | 15.6 | 1206.9
08:03:25:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:03:27:ST3_smx:INFO: chip: 1-0 18.745682 C 1200.969315 mV
08:03:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:28:ST3_smx:INFO: Electrons
08:03:28:ST3_smx:INFO: # loops 0
08:03:29:ST3_smx:INFO: # loops 1
08:03:31:ST3_smx:INFO: # loops 2
08:03:32:ST3_smx:INFO: # loops 3
08:03:34:ST3_smx:INFO: # loops 4
08:03:35:ST3_smx:INFO: Total # of broken channels: 0
08:03:35:ST3_smx:INFO: List of broken channels: []
08:03:35:ST3_smx:INFO: Total # of broken channels: 0
08:03:35:ST3_smx:INFO: List of broken channels: []
08:03:37:ST3_smx:INFO: chip: 8-1 25.062742 C 1177.390875 mV
08:03:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:37:ST3_smx:INFO: Electrons
08:03:37:ST3_smx:INFO: # loops 0
08:03:38:ST3_smx:INFO: # loops 1
08:03:40:ST3_smx:INFO: # loops 2
08:03:41:ST3_smx:INFO: # loops 3
08:03:43:ST3_smx:INFO: # loops 4
08:03:45:ST3_smx:INFO: Total # of broken channels: 0
08:03:45:ST3_smx:INFO: List of broken channels: []
08:03:45:ST3_smx:INFO: Total # of broken channels: 0
08:03:45:ST3_smx:INFO: List of broken channels: []
08:03:46:ST3_smx:INFO: chip: 3-2 31.389742 C 1159.654860 mV
08:03:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:46:ST3_smx:INFO: Electrons
08:03:47:ST3_smx:INFO: # loops 0
08:03:48:ST3_smx:INFO: # loops 1
08:03:50:ST3_smx:INFO: # loops 2
08:03:51:ST3_smx:INFO: # loops 3
08:03:53:ST3_smx:INFO: # loops 4
08:03:54:ST3_smx:INFO: Total # of broken channels: 0
08:03:54:ST3_smx:INFO: List of broken channels: []
08:03:54:ST3_smx:INFO: Total # of broken channels: 0
08:03:54:ST3_smx:INFO: List of broken channels: []
08:03:56:ST3_smx:INFO: chip: 10-3 21.902970 C 1200.969315 mV
08:03:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:03:56:ST3_smx:INFO: Electrons
08:03:56:ST3_smx:INFO: # loops 0
08:03:57:ST3_smx:INFO: # loops 1
08:03:59:ST3_smx:INFO: # loops 2
08:04:00:ST3_smx:INFO: # loops 3
08:04:02:ST3_smx:INFO: # loops 4
08:04:03:ST3_smx:INFO: Total # of broken channels: 0
08:04:03:ST3_smx:INFO: List of broken channels: []
08:04:03:ST3_smx:INFO: Total # of broken channels: 0
08:04:03:ST3_smx:INFO: List of broken channels: []
08:04:05:ST3_smx:INFO: chip: 5-4 34.556970 C 1159.654860 mV
08:04:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:05:ST3_smx:INFO: Electrons
08:04:05:ST3_smx:INFO: # loops 0
08:04:07:ST3_smx:INFO: # loops 1
08:04:08:ST3_smx:INFO: # loops 2
08:04:10:ST3_smx:INFO: # loops 3
08:04:11:ST3_smx:INFO: # loops 4
08:04:13:ST3_smx:INFO: Total # of broken channels: 0
08:04:13:ST3_smx:INFO: List of broken channels: []
08:04:13:ST3_smx:INFO: Total # of broken channels: 0
08:04:13:ST3_smx:INFO: List of broken channels: []
08:04:14:ST3_smx:INFO: chip: 12-5 15.590880 C 1224.468235 mV
08:04:14:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:14:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:14:ST3_smx:INFO: Electrons
08:04:14:ST3_smx:INFO: # loops 0
08:04:16:ST3_smx:INFO: # loops 1
08:04:17:ST3_smx:INFO: # loops 2
08:04:19:ST3_smx:INFO: # loops 3
08:04:20:ST3_smx:INFO: # loops 4
08:04:22:ST3_smx:INFO: Total # of broken channels: 0
08:04:22:ST3_smx:INFO: List of broken channels: []
08:04:22:ST3_smx:INFO: Total # of broken channels: 0
08:04:22:ST3_smx:INFO: List of broken channels: []
08:04:24:ST3_smx:INFO: chip: 7-6 34.556970 C 1159.654860 mV
08:04:24:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:24:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:24:ST3_smx:INFO: Electrons
08:04:24:ST3_smx:INFO: # loops 0
08:04:25:ST3_smx:INFO: # loops 1
08:04:27:ST3_smx:INFO: # loops 2
08:04:28:ST3_smx:INFO: # loops 3
08:04:30:ST3_smx:INFO: # loops 4
08:04:31:ST3_smx:INFO: Total # of broken channels: 0
08:04:31:ST3_smx:INFO: List of broken channels: []
08:04:31:ST3_smx:INFO: Total # of broken channels: 0
08:04:31:ST3_smx:INFO: List of broken channels: []
08:04:33:ST3_smx:INFO: chip: 14-7 18.745682 C 1212.728715 mV
08:04:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:33:ST3_smx:INFO: Electrons
08:04:33:ST3_smx:INFO: # loops 0
08:04:35:ST3_smx:INFO: # loops 1
08:04:36:ST3_smx:INFO: # loops 2
08:04:38:ST3_smx:INFO: # loops 3
08:04:39:ST3_smx:INFO: # loops 4
08:04:41:ST3_smx:INFO: Total # of broken channels: 0
08:04:41:ST3_smx:INFO: List of broken channels: []
08:04:41:ST3_smx:INFO: Total # of broken channels: 0
08:04:41:ST3_smx:INFO: List of broken channels: []
08:04:41:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:04:41:febtest:INFO: 01-00 | XA-000-08-002-002-006-100-09 | 21.9 | 1224.5
08:04:42:febtest:INFO: 08-01 | XA-000-08-002-002-006-076-07 | 28.2 | 1195.1
08:04:42:febtest:INFO: 03-02 | XA-000-08-002-002-006-090-00 | 31.4 | 1183.3
08:04:42:febtest:INFO: 10-03 | XA-000-08-002-002-006-066-07 | 21.9 | 1218.6
08:04:42:febtest:INFO: 05-04 | XA-000-08-002-002-006-067-07 | 37.7 | 1183.3
08:04:43:febtest:INFO: 12-05 | XA-000-08-002-002-006-096-09 | 15.6 | 1247.9
08:04:43:febtest:INFO: 07-06 | XA-000-08-002-002-006-071-07 | 37.7 | 1177.4
08:04:43:febtest:INFO: 14-07 | XA-000-08-002-002-006-095-00 | 18.7 | 1236.2
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_04-08_02_38
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1166| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 23094
MODULE_NAME: L4DL000161 M4DL0T3001613A2 124 C
MODULE_TYPE:
MODULE_LADDER:
MODULE_MODULE:
MODULE_SIZE: 0
MODULE_GRADE:
------------------------------------------------------------
VI_before_Init : ['2.450', '1.4770', '1.850', '2.5140', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0280', '1.850', '2.4600', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9500', '1.850', '0.5212', '0.000', '0.0000', '0.000', '0.0000']