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FEB_1167 28.05.24 08:03:31
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08:03:31:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:03:31:ST3_Shared:INFO: FEB-Sensor
08:03:31:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:03:55:ST3_ModuleSelector:INFO: L7DL300122 M7DL3T2001222A2 124 B
08:03:55:ST3_ModuleSelector:INFO: 26214
08:03:55:febtest:INFO: Testing FEB with SN 1167
08:03:57:smx_tester:INFO: Scanning setup
08:03:57:elinks:INFO: Disabling clock on downlink 0
08:03:57:elinks:INFO: Disabling clock on downlink 1
08:03:57:elinks:INFO: Disabling clock on downlink 2
08:03:57:elinks:INFO: Disabling clock on downlink 3
08:03:57:elinks:INFO: Disabling clock on downlink 4
08:03:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:03:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:03:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:03:57:elinks:INFO: Disabling clock on downlink 0
08:03:57:elinks:INFO: Disabling clock on downlink 1
08:03:57:elinks:INFO: Disabling clock on downlink 2
08:03:57:elinks:INFO: Disabling clock on downlink 3
08:03:57:elinks:INFO: Disabling clock on downlink 4
08:03:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:03:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:03:57:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:03:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:03:57:elinks:INFO: Disabling clock on downlink 0
08:03:57:elinks:INFO: Disabling clock on downlink 1
08:03:57:elinks:INFO: Disabling clock on downlink 2
08:03:57:elinks:INFO: Disabling clock on downlink 3
08:03:57:elinks:INFO: Disabling clock on downlink 4
08:03:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:03:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:03:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:03:57:elinks:INFO: Disabling clock on downlink 0
08:03:57:elinks:INFO: Disabling clock on downlink 1
08:03:57:elinks:INFO: Disabling clock on downlink 2
08:03:57:elinks:INFO: Disabling clock on downlink 3
08:03:57:elinks:INFO: Disabling clock on downlink 4
08:03:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:03:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:03:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:03:57:elinks:INFO: Disabling clock on downlink 0
08:03:57:elinks:INFO: Disabling clock on downlink 1
08:03:57:elinks:INFO: Disabling clock on downlink 2
08:03:57:elinks:INFO: Disabling clock on downlink 3
08:03:57:elinks:INFO: Disabling clock on downlink 4
08:03:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:03:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:03:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:03:57:setup_element:INFO: Scanning clock phase
08:03:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:03:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:03:58:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:03:58:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
08:03:58:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
08:03:58:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
08:03:58:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXXXX_
Clock Delay: 33
08:03:58:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:03:58:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:03:58:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XX_______
Clock Delay: 31
08:03:58:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XX_______
Clock Delay: 31
08:03:58:setup_element:INFO: Eye window for uplink 14: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Eye window for uplink 15: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:03:58:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
08:03:58:setup_element:INFO: Scanning data phases
08:03:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:03:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:04:03:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:04:03:setup_element:INFO: Eye window for uplink 0 : ____________XXXXXX______________________
Data delay found: 34
08:04:03:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
08:04:03:setup_element:INFO: Eye window for uplink 2 : _________XXXX___________________________
Data delay found: 30
08:04:03:setup_element:INFO: Eye window for uplink 3 : _____XXXXXX_____________________________
Data delay found: 27
08:04:03:setup_element:INFO: Eye window for uplink 4 : _______XXXX_____________________________
Data delay found: 28
08:04:03:setup_element:INFO: Eye window for uplink 5 : ___XXXX_________________________________
Data delay found: 24
08:04:03:setup_element:INFO: Eye window for uplink 6 : XXXX___________________________________X
Data delay found: 21
08:04:03:setup_element:INFO: Eye window for uplink 7 : X__________________________________XXXX_
Data delay found: 17
08:04:03:setup_element:INFO: Eye window for uplink 8 : _________________________XXXXX__________
Data delay found: 7
08:04:03:setup_element:INFO: Eye window for uplink 9 : _______________________________XXXXX____
Data delay found: 13
08:04:03:setup_element:INFO: Eye window for uplink 10: _____________________________XXXXX______
Data delay found: 11
08:04:03:setup_element:INFO: Eye window for uplink 11: _________________________________XXXXX__
Data delay found: 15
08:04:03:setup_element:INFO: Eye window for uplink 12: _______________________________XXXX_____
Data delay found: 12
08:04:03:setup_element:INFO: Eye window for uplink 13: __________________________________XXXXX_
Data delay found: 16
08:04:03:setup_element:INFO: Eye window for uplink 14: ________________________________XXX_____
Data delay found: 13
08:04:03:setup_element:INFO: Eye window for uplink 15: _________________________________XXXXX__
Data delay found: 15
08:04:04:setup_element:INFO: Setting the data phase to 34 for uplink 0
08:04:04:setup_element:INFO: Setting the data phase to 30 for uplink 1
08:04:04:setup_element:INFO: Setting the data phase to 30 for uplink 2
08:04:04:setup_element:INFO: Setting the data phase to 27 for uplink 3
08:04:04:setup_element:INFO: Setting the data phase to 28 for uplink 4
08:04:04:setup_element:INFO: Setting the data phase to 24 for uplink 5
08:04:04:setup_element:INFO: Setting the data phase to 21 for uplink 6
08:04:04:setup_element:INFO: Setting the data phase to 17 for uplink 7
08:04:04:setup_element:INFO: Setting the data phase to 7 for uplink 8
08:04:04:setup_element:INFO: Setting the data phase to 13 for uplink 9
08:04:04:setup_element:INFO: Setting the data phase to 11 for uplink 10
08:04:04:setup_element:INFO: Setting the data phase to 15 for uplink 11
08:04:04:setup_element:INFO: Setting the data phase to 12 for uplink 12
08:04:04:setup_element:INFO: Setting the data phase to 16 for uplink 13
08:04:04:setup_element:INFO: Setting the data phase to 13 for uplink 14
08:04:04:setup_element:INFO: Setting the data phase to 15 for uplink 15
08:04:04:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: ________________________________________________________________________XXXXXXX_
Uplink 5: ________________________________________________________________________XXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: _____________________________________________________________________XXXXXXXXXX_
Uplink 9: _____________________________________________________________________XXXXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXX__
Uplink 11: _______________________________________________________________________XXXXXXX__
Uplink 12: _______________________________________________________________________XX_______
Uplink 13: _______________________________________________________________________XX_______
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 3:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 6:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 7:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 8:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 9:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 10:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 11:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 12:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 13:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 14:
Optimal Phase: 13
Window Length: 37
Eye Window: ________________________________XXX_____
Uplink 15:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
]
08:04:04:setup_element:INFO: Beginning SMX ASICs map scan
08:04:04:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:04:04:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:04:04:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:04:04:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:04:04:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:04:04:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:04:04:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:04:04:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:04:04:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:04:04:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:04:04:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:04:04:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:04:04:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:04:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:04:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:04:05:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:04:05:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:04:05:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:04:05:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:04:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:04:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:04:06:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: ________________________________________________________________________XXXXXXX_
Uplink 5: ________________________________________________________________________XXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: _____________________________________________________________________XXXXXXXXXX_
Uplink 9: _____________________________________________________________________XXXXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXX__
Uplink 11: _______________________________________________________________________XXXXXXX__
Uplink 12: _______________________________________________________________________XX_______
Uplink 13: _______________________________________________________________________XX_______
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 3:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 5:
Optimal Phase: 24
Window Length: 36
Eye Window: ___XXXX_________________________________
Uplink 6:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 7:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 8:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 9:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 10:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 11:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 12:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 13:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 14:
Optimal Phase: 13
Window Length: 37
Eye Window: ________________________________XXX_____
Uplink 15:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
08:04:06:setup_element:INFO: Performing Elink synchronization
08:04:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:04:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:04:06:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:04:06:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:04:06:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:04:06:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:04:06:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
08:04:07:febtest:INFO: Init all SMX (CSA): 30
08:04:21:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:04:21:febtest:INFO: 01-00 | XA-000-08-002-000-007-069-03 | 25.1 | 1177.4
08:04:22:febtest:INFO: 08-01 | XA-000-08-002-002-008-128-01 | 25.1 | 1159.7
08:04:22:febtest:INFO: 03-02 | XA-000-08-002-000-007-064-03 | 25.1 | 1183.3
08:04:22:febtest:INFO: 10-03 | XA-000-08-002-002-008-143-01 | 25.1 | 1177.4
08:04:22:febtest:INFO: 05-04 | XA-000-08-002-002-008-131-01 | 34.6 | 1153.7
08:04:23:febtest:INFO: 12-05 | XA-000-08-002-002-008-147-06 | 34.6 | 1147.8
08:04:23:febtest:INFO: 07-06 | XA-000-08-002-002-008-123-07 | 31.4 | 1165.6
08:04:23:febtest:INFO: 14-07 | XA-000-08-002-002-008-145-06 | 37.7 | 1141.9
08:04:24:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:04:26:ST3_smx:INFO: chip: 1-0 25.062742 C 1189.190035 mV
08:04:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:26:ST3_smx:INFO: Electrons
08:04:26:ST3_smx:INFO: # loops 0
08:04:28:ST3_smx:INFO: # loops 1
08:04:29:ST3_smx:INFO: # loops 2
08:04:31:ST3_smx:INFO: # loops 3
08:04:33:ST3_smx:INFO: # loops 4
08:04:34:ST3_smx:INFO: Total # of broken channels: 0
08:04:34:ST3_smx:INFO: List of broken channels: []
08:04:34:ST3_smx:INFO: Total # of broken channels: 0
08:04:34:ST3_smx:INFO: List of broken channels: []
08:04:36:ST3_smx:INFO: chip: 8-1 25.062742 C 1171.483840 mV
08:04:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:36:ST3_smx:INFO: Electrons
08:04:36:ST3_smx:INFO: # loops 0
08:04:38:ST3_smx:INFO: # loops 1
08:04:39:ST3_smx:INFO: # loops 2
08:04:41:ST3_smx:INFO: # loops 3
08:04:43:ST3_smx:INFO: # loops 4
08:04:44:ST3_smx:INFO: Total # of broken channels: 0
08:04:44:ST3_smx:INFO: List of broken channels: []
08:04:44:ST3_smx:INFO: Total # of broken channels: 0
08:04:44:ST3_smx:INFO: List of broken channels: []
08:04:46:ST3_smx:INFO: chip: 3-2 25.062742 C 1189.190035 mV
08:04:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:46:ST3_smx:INFO: Electrons
08:04:46:ST3_smx:INFO: # loops 0
08:04:48:ST3_smx:INFO: # loops 1
08:04:49:ST3_smx:INFO: # loops 2
08:04:51:ST3_smx:INFO: # loops 3
08:04:53:ST3_smx:INFO: # loops 4
08:04:54:ST3_smx:INFO: Total # of broken channels: 0
08:04:54:ST3_smx:INFO: List of broken channels: []
08:04:54:ST3_smx:INFO: Total # of broken channels: 0
08:04:54:ST3_smx:INFO: List of broken channels: []
08:04:56:ST3_smx:INFO: chip: 10-3 25.062742 C 1189.190035 mV
08:04:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:04:56:ST3_smx:INFO: Electrons
08:04:56:ST3_smx:INFO: # loops 0
08:04:58:ST3_smx:INFO: # loops 1
08:04:59:ST3_smx:INFO: # loops 2
08:05:01:ST3_smx:INFO: # loops 3
08:05:02:ST3_smx:INFO: # loops 4
08:05:04:ST3_smx:INFO: Total # of broken channels: 0
08:05:04:ST3_smx:INFO: List of broken channels: []
08:05:04:ST3_smx:INFO: Total # of broken channels: 0
08:05:04:ST3_smx:INFO: List of broken channels: []
08:05:06:ST3_smx:INFO: chip: 5-4 37.726682 C 1165.571835 mV
08:05:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:06:ST3_smx:INFO: Electrons
08:05:06:ST3_smx:INFO: # loops 0
08:05:07:ST3_smx:INFO: # loops 1
08:05:09:ST3_smx:INFO: # loops 2
08:05:10:ST3_smx:INFO: # loops 3
08:05:12:ST3_smx:INFO: # loops 4
08:05:14:ST3_smx:INFO: Total # of broken channels: 0
08:05:14:ST3_smx:INFO: List of broken channels: []
08:05:14:ST3_smx:INFO: Total # of broken channels: 0
08:05:14:ST3_smx:INFO: List of broken channels: []
08:05:15:ST3_smx:INFO: chip: 12-5 34.556970 C 1159.654860 mV
08:05:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:15:ST3_smx:INFO: Electrons
08:05:15:ST3_smx:INFO: # loops 0
08:05:17:ST3_smx:INFO: # loops 1
08:05:19:ST3_smx:INFO: # loops 2
08:05:20:ST3_smx:INFO: # loops 3
08:05:22:ST3_smx:INFO: # loops 4
08:05:23:ST3_smx:INFO: Total # of broken channels: 0
08:05:23:ST3_smx:INFO: List of broken channels: []
08:05:23:ST3_smx:INFO: Total # of broken channels: 0
08:05:23:ST3_smx:INFO: List of broken channels: []
08:05:25:ST3_smx:INFO: chip: 7-6 34.556970 C 1177.390875 mV
08:05:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:25:ST3_smx:INFO: Electrons
08:05:25:ST3_smx:INFO: # loops 0
08:05:27:ST3_smx:INFO: # loops 1
08:05:28:ST3_smx:INFO: # loops 2
08:05:30:ST3_smx:INFO: # loops 3
08:05:32:ST3_smx:INFO: # loops 4
08:05:33:ST3_smx:INFO: Total # of broken channels: 0
08:05:33:ST3_smx:INFO: List of broken channels: []
08:05:33:ST3_smx:INFO: Total # of broken channels: 0
08:05:33:ST3_smx:INFO: List of broken channels: []
08:05:35:ST3_smx:INFO: chip: 14-7 40.898880 C 1147.806000 mV
08:05:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:05:35:ST3_smx:INFO: Electrons
08:05:35:ST3_smx:INFO: # loops 0
08:05:37:ST3_smx:INFO: # loops 1
08:05:38:ST3_smx:INFO: # loops 2
08:05:40:ST3_smx:INFO: # loops 3
08:05:41:ST3_smx:INFO: # loops 4
08:05:43:ST3_smx:INFO: Total # of broken channels: 0
08:05:43:ST3_smx:INFO: List of broken channels: []
08:05:43:ST3_smx:INFO: Total # of broken channels: 0
08:05:43:ST3_smx:INFO: List of broken channels: []
08:05:43:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:05:44:febtest:INFO: 01-00 | XA-000-08-002-000-007-069-03 | 28.2 | 1212.7
08:05:44:febtest:INFO: 08-01 | XA-000-08-002-002-008-128-01 | 28.2 | 1189.2
08:05:44:febtest:INFO: 03-02 | XA-000-08-002-000-007-064-03 | 28.2 | 1206.9
08:05:44:febtest:INFO: 10-03 | XA-000-08-002-002-008-143-01 | 28.2 | 1206.9
08:05:44:febtest:INFO: 05-04 | XA-000-08-002-002-008-131-01 | 37.7 | 1183.3
08:05:45:febtest:INFO: 12-05 | XA-000-08-002-002-008-147-06 | 37.7 | 1183.3
08:05:45:febtest:INFO: 07-06 | XA-000-08-002-002-008-123-07 | 37.7 | 1195.1
08:05:45:febtest:INFO: 14-07 | XA-000-08-002-002-008-145-06 | 44.1 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_05_28-08_03_31
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1167| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 26214
MODULE_NAME: L7DL300122 M7DL3T2001222A2 124 B
MODULE_TYPE:
MODULE_LADDER:
MODULE_MODULE:
MODULE_SIZE: 0
MODULE_GRADE:
------------------------------------------------------------
VI_before_Init : ['2.450', '1.5590', '1.849', '2.5960', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.1150', '1.850', '2.3510', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9950', '1.850', '0.5289', '0.000', '0.0000', '0.000', '0.0000']