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FEB_1169 28.05.24 13:49:27
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13:49:27:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:49:27:ST3_Shared:INFO: FEB-Sensor
13:49:27:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:49:51:ST3_ModuleSelector:INFO: L4DL000161 M4DL0B1001611B2 62 A
13:49:51:ST3_ModuleSelector:INFO: 10043
13:49:51:febtest:INFO: Testing FEB with SN 1169
13:49:52:smx_tester:INFO: Scanning setup
13:49:52:elinks:INFO: Disabling clock on downlink 0
13:49:52:elinks:INFO: Disabling clock on downlink 1
13:49:52:elinks:INFO: Disabling clock on downlink 2
13:49:52:elinks:INFO: Disabling clock on downlink 3
13:49:52:elinks:INFO: Disabling clock on downlink 4
13:49:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:49:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:49:52:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:49:52:elinks:INFO: Disabling clock on downlink 0
13:49:52:elinks:INFO: Disabling clock on downlink 1
13:49:52:elinks:INFO: Disabling clock on downlink 2
13:49:52:elinks:INFO: Disabling clock on downlink 3
13:49:52:elinks:INFO: Disabling clock on downlink 4
13:49:52:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:49:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:49:52:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
13:49:53:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
13:49:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:49:53:elinks:INFO: Disabling clock on downlink 0
13:49:53:elinks:INFO: Disabling clock on downlink 1
13:49:53:elinks:INFO: Disabling clock on downlink 2
13:49:53:elinks:INFO: Disabling clock on downlink 3
13:49:53:elinks:INFO: Disabling clock on downlink 4
13:49:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:49:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:49:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:49:53:elinks:INFO: Disabling clock on downlink 0
13:49:53:elinks:INFO: Disabling clock on downlink 1
13:49:53:elinks:INFO: Disabling clock on downlink 2
13:49:53:elinks:INFO: Disabling clock on downlink 3
13:49:53:elinks:INFO: Disabling clock on downlink 4
13:49:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:49:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:49:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:49:53:elinks:INFO: Disabling clock on downlink 0
13:49:53:elinks:INFO: Disabling clock on downlink 1
13:49:53:elinks:INFO: Disabling clock on downlink 2
13:49:53:elinks:INFO: Disabling clock on downlink 3
13:49:53:elinks:INFO: Disabling clock on downlink 4
13:49:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:49:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:49:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:49:53:setup_element:INFO: Scanning clock phase
13:49:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:49:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:49:53:setup_element:INFO: Clock phase scan results for group 0, downlink 1
13:49:53:setup_element:INFO: Eye window for uplink 0 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:49:53:setup_element:INFO: Eye window for uplink 1 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:49:53:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:49:53:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
13:49:53:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 6 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 7 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 8 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:49:53:setup_element:INFO: Eye window for uplink 9 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:49:53:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:49:53:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:49:53:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:49:53:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:49:53:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
13:49:53:setup_element:INFO: Scanning data phases
13:49:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:49:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:49:59:setup_element:INFO: Data phase scan results for group 0, downlink 1
13:49:59:setup_element:INFO: Eye window for uplink 0 : ____________XXXXX_______________________
Data delay found: 34
13:49:59:setup_element:INFO: Eye window for uplink 1 : ________XXXXX___________________________
Data delay found: 30
13:49:59:setup_element:INFO: Eye window for uplink 2 : __________XXXXX_________________________
Data delay found: 32
13:49:59:setup_element:INFO: Eye window for uplink 3 : _______XXXXX____________________________
Data delay found: 29
13:49:59:setup_element:INFO: Eye window for uplink 4 : _____XXXX_______________________________
Data delay found: 26
13:49:59:setup_element:INFO: Eye window for uplink 5 : _XXXXX__________________________________
Data delay found: 23
13:49:59:setup_element:INFO: Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
13:49:59:setup_element:INFO: Eye window for uplink 7 : __________________________________XXXXX_
Data delay found: 16
13:49:59:setup_element:INFO: Eye window for uplink 8 : _______________________XXXXX____________
Data delay found: 5
13:49:59:setup_element:INFO: Eye window for uplink 9 : ____________________________XXXXXX______
Data delay found: 10
13:49:59:setup_element:INFO: Eye window for uplink 10: _________________________XXXXX__________
Data delay found: 7
13:49:59:setup_element:INFO: Eye window for uplink 11: _____________________________XXXXX______
Data delay found: 11
13:49:59:setup_element:INFO: Eye window for uplink 12: ____________________________XXXX________
Data delay found: 9
13:49:59:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXX_____
Data delay found: 12
13:49:59:setup_element:INFO: Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
13:49:59:setup_element:INFO: Eye window for uplink 15: _______________________________XXXX_____
Data delay found: 12
13:49:59:setup_element:INFO: Setting the data phase to 34 for uplink 0
13:49:59:setup_element:INFO: Setting the data phase to 30 for uplink 1
13:49:59:setup_element:INFO: Setting the data phase to 32 for uplink 2
13:49:59:setup_element:INFO: Setting the data phase to 29 for uplink 3
13:49:59:setup_element:INFO: Setting the data phase to 26 for uplink 4
13:49:59:setup_element:INFO: Setting the data phase to 23 for uplink 5
13:49:59:setup_element:INFO: Setting the data phase to 20 for uplink 6
13:49:59:setup_element:INFO: Setting the data phase to 16 for uplink 7
13:49:59:setup_element:INFO: Setting the data phase to 5 for uplink 8
13:49:59:setup_element:INFO: Setting the data phase to 10 for uplink 9
13:49:59:setup_element:INFO: Setting the data phase to 7 for uplink 10
13:49:59:setup_element:INFO: Setting the data phase to 11 for uplink 11
13:49:59:setup_element:INFO: Setting the data phase to 9 for uplink 12
13:49:59:setup_element:INFO: Setting the data phase to 12 for uplink 13
13:49:59:setup_element:INFO: Setting the data phase to 10 for uplink 14
13:49:59:setup_element:INFO: Setting the data phase to 12 for uplink 15
13:49:59:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXX_
Uplink 1: ________________________________________________________________________XXXXXXX_
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: _______________________________________________________________________XXXXXX___
Uplink 5: _______________________________________________________________________XXXXXX___
Uplink 6: ______________________________________________________________________XXXXXXXX__
Uplink 7: ______________________________________________________________________XXXXXXXX__
Uplink 8: ____________________________________________________________________XXXXXXXXX___
Uplink 9: ____________________________________________________________________XXXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXX___
Uplink 13: ______________________________________________________________________XXXXXXX___
Uplink 14: ______________________________________________________________________XXXXXXX___
Uplink 15: ______________________________________________________________________XXXXXXX___
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 3:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 4:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 8:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 9:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 10:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 11:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 12:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
]
13:49:59:setup_element:INFO: Beginning SMX ASICs map scan
13:49:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:49:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:49:59:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:49:59:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:49:59:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:49:59:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
13:49:59:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
13:49:59:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
13:49:59:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
13:50:00:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
13:50:00:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
13:50:00:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
13:50:00:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
13:50:00:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
13:50:00:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
13:50:00:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
13:50:00:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
13:50:00:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
13:50:00:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
13:50:00:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
13:50:00:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
13:50:02:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 69
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXX_
Uplink 1: ________________________________________________________________________XXXXXXX_
Uplink 2: ________________________________________________________________________XXXXXXX_
Uplink 3: ________________________________________________________________________XXXXXXX_
Uplink 4: _______________________________________________________________________XXXXXX___
Uplink 5: _______________________________________________________________________XXXXXX___
Uplink 6: ______________________________________________________________________XXXXXXXX__
Uplink 7: ______________________________________________________________________XXXXXXXX__
Uplink 8: ____________________________________________________________________XXXXXXXXX___
Uplink 9: ____________________________________________________________________XXXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXX___
Uplink 11: _____________________________________________________________________XXXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXX___
Uplink 13: ______________________________________________________________________XXXXXXX___
Uplink 14: ______________________________________________________________________XXXXXXX___
Uplink 15: ______________________________________________________________________XXXXXXX___
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 1:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 2:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 3:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 4:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 8:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 9:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 10:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 11:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 12:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
13:50:02:setup_element:INFO: Performing Elink synchronization
13:50:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:50:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:50:02:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:50:02:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:50:02:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
13:50:02:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:50:02:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0_1 (Potential memory leak).
13:50:03:febtest:INFO: Init all SMX (CSA): 30
13:50:17:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:50:18:febtest:INFO: 01-00 | XA-000-08-002-002-006-169-06 | 37.7 | 1141.9
13:50:18:febtest:INFO: 08-01 | XA-000-08-002-002-008-187-08 | 37.7 | 1147.8
13:50:18:febtest:INFO: 03-02 | XA-000-08-002-002-008-162-15 | 34.6 | 1159.7
13:50:18:febtest:INFO: 10-03 | XA-000-08-002-002-006-118-14 | 34.6 | 1153.7
13:50:18:febtest:INFO: 05-04 | XA-000-08-002-002-006-130-08 | 37.7 | 1165.6
13:50:19:febtest:INFO: 12-05 | XA-000-08-002-002-006-124-14 | 34.6 | 1159.7
13:50:19:febtest:INFO: 07-06 | XA-000-08-002-002-008-177-08 | 34.6 | 1171.5
13:50:19:febtest:INFO: 14-07 | XA-000-08-002-002-008-184-08 | 50.4 | 1112.1
13:50:20:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
13:50:22:ST3_smx:INFO: chip: 1-0 40.898880 C 1153.732915 mV
13:50:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:22:ST3_smx:INFO: Electrons
13:50:22:ST3_smx:INFO: # loops 0
13:50:24:ST3_smx:INFO: # loops 1
13:50:25:ST3_smx:INFO: # loops 2
13:50:27:ST3_smx:INFO: # loops 3
13:50:29:ST3_smx:INFO: # loops 4
13:50:30:ST3_smx:INFO: Total # of broken channels: 0
13:50:30:ST3_smx:INFO: List of broken channels: []
13:50:30:ST3_smx:INFO: Total # of broken channels: 1
13:50:30:ST3_smx:INFO: List of broken channels: [91]
13:50:32:ST3_smx:INFO: chip: 8-1 37.726682 C 1159.654860 mV
13:50:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:32:ST3_smx:INFO: Electrons
13:50:32:ST3_smx:INFO: # loops 0
13:50:34:ST3_smx:INFO: # loops 1
13:50:36:ST3_smx:INFO: # loops 2
13:50:37:ST3_smx:INFO: # loops 3
13:50:39:ST3_smx:INFO: # loops 4
13:50:41:ST3_smx:INFO: Total # of broken channels: 0
13:50:41:ST3_smx:INFO: List of broken channels: []
13:50:41:ST3_smx:INFO: Total # of broken channels: 0
13:50:41:ST3_smx:INFO: List of broken channels: []
13:50:42:ST3_smx:INFO: chip: 3-2 34.556970 C 1171.483840 mV
13:50:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:42:ST3_smx:INFO: Electrons
13:50:42:ST3_smx:INFO: # loops 0
13:50:44:ST3_smx:INFO: # loops 1
13:50:46:ST3_smx:INFO: # loops 2
13:50:47:ST3_smx:INFO: # loops 3
13:50:49:ST3_smx:INFO: # loops 4
13:50:51:ST3_smx:INFO: Total # of broken channels: 0
13:50:51:ST3_smx:INFO: List of broken channels: []
13:50:51:ST3_smx:INFO: Total # of broken channels: 1
13:50:51:ST3_smx:INFO: List of broken channels: [34]
13:50:52:ST3_smx:INFO: chip: 10-3 34.556970 C 1165.571835 mV
13:50:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:50:52:ST3_smx:INFO: Electrons
13:50:52:ST3_smx:INFO: # loops 0
13:50:54:ST3_smx:INFO: # loops 1
13:50:55:ST3_smx:INFO: # loops 2
13:50:57:ST3_smx:INFO: # loops 3
13:50:59:ST3_smx:INFO: # loops 4
13:51:00:ST3_smx:INFO: Total # of broken channels: 0
13:51:00:ST3_smx:INFO: List of broken channels: []
13:51:00:ST3_smx:INFO: Total # of broken channels: 0
13:51:00:ST3_smx:INFO: List of broken channels: []
13:51:02:ST3_smx:INFO: chip: 5-4 37.726682 C 1171.483840 mV
13:51:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:02:ST3_smx:INFO: Electrons
13:51:02:ST3_smx:INFO: # loops 0
13:51:04:ST3_smx:INFO: # loops 1
13:51:06:ST3_smx:INFO: # loops 2
13:51:07:ST3_smx:INFO: # loops 3
13:51:09:ST3_smx:INFO: # loops 4
13:51:10:ST3_smx:INFO: Total # of broken channels: 0
13:51:10:ST3_smx:INFO: List of broken channels: []
13:51:10:ST3_smx:INFO: Total # of broken channels: 0
13:51:10:ST3_smx:INFO: List of broken channels: []
13:51:12:ST3_smx:INFO: chip: 12-5 34.556970 C 1171.483840 mV
13:51:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:12:ST3_smx:INFO: Electrons
13:51:12:ST3_smx:INFO: # loops 0
13:51:14:ST3_smx:INFO: # loops 1
13:51:16:ST3_smx:INFO: # loops 2
13:51:17:ST3_smx:INFO: # loops 3
13:51:19:ST3_smx:INFO: # loops 4
13:51:21:ST3_smx:INFO: Total # of broken channels: 0
13:51:21:ST3_smx:INFO: List of broken channels: []
13:51:21:ST3_smx:INFO: Total # of broken channels: 0
13:51:21:ST3_smx:INFO: List of broken channels: []
13:51:22:ST3_smx:INFO: chip: 7-6 34.556970 C 1183.292940 mV
13:51:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:22:ST3_smx:INFO: Electrons
13:51:22:ST3_smx:INFO: # loops 0
13:51:24:ST3_smx:INFO: # loops 1
13:51:26:ST3_smx:INFO: # loops 2
13:51:27:ST3_smx:INFO: # loops 3
13:51:29:ST3_smx:INFO: # loops 4
13:51:30:ST3_smx:INFO: Total # of broken channels: 3
13:51:30:ST3_smx:INFO: List of broken channels: [23, 25, 27]
13:51:30:ST3_smx:INFO: Total # of broken channels: 44
13:51:30:ST3_smx:INFO: List of broken channels: [23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 77, 79, 81, 83, 85, 93, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127]
13:51:32:ST3_smx:INFO: chip: 14-7 50.430383 C 1118.096875 mV
13:51:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:51:32:ST3_smx:INFO: Electrons
13:51:32:ST3_smx:INFO: # loops 0
13:51:34:ST3_smx:INFO: # loops 1
13:51:35:ST3_smx:INFO: # loops 2
13:51:37:ST3_smx:INFO: # loops 3
13:51:39:ST3_smx:INFO: # loops 4
13:51:40:ST3_smx:INFO: Total # of broken channels: 0
13:51:40:ST3_smx:INFO: List of broken channels: []
13:51:40:ST3_smx:INFO: Total # of broken channels: 0
13:51:40:ST3_smx:INFO: List of broken channels: []
13:51:41:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:51:41:febtest:INFO: 01-00 | XA-000-08-002-002-006-169-06 | 40.9 | 1177.4
13:51:41:febtest:INFO: 08-01 | XA-000-08-002-002-008-187-08 | 37.7 | 1183.3
13:51:41:febtest:INFO: 03-02 | XA-000-08-002-002-008-162-15 | 37.7 | 1195.1
13:51:42:febtest:INFO: 10-03 | XA-000-08-002-002-006-118-14 | 37.7 | 1189.2
13:51:42:febtest:INFO: 05-04 | XA-000-08-002-002-006-130-08 | 37.7 | 1195.1
13:51:42:febtest:INFO: 12-05 | XA-000-08-002-002-006-124-14 | 34.6 | 1189.2
13:51:42:febtest:INFO: 07-06 | XA-000-08-002-002-008-177-08 | 37.7 | 1201.0
13:51:42:febtest:INFO: 14-07 | XA-000-08-002-002-008-184-08 | 53.6 | 1141.9
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_05_28-13_49_27
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1169| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 10043
MODULE_NAME: L4DL000161 M4DL0B1001611B2 62 A
MODULE_TYPE:
MODULE_LADDER: L4DL000161
MODULE_MODULE: M4DL0B1001611B2
MODULE_SIZE: 62
MODULE_GRADE: A
------------------------------------------------------------
VI_before_Init : ['2.450', '1.5560', '1.849', '2.2810', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0200', '1.850', '2.4590', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9870', '1.850', '0.5253', '0.000', '0.0000', '0.000', '0.0000']