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FEB_1170 04.06.24 08:33:29
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08:33:29:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:33:29:ST3_Shared:INFO: FEB-Sensor
08:33:29:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:33:49:ST3_ModuleSelector:INFO: L7DL300122 M7DL3T1001221A2 62 B
08:33:49:ST3_ModuleSelector:INFO: 25123
08:33:49:febtest:INFO: Testing FEB with SN 1170
08:33:50:smx_tester:INFO: Scanning setup
08:33:50:elinks:INFO: Disabling clock on downlink 0
08:33:50:elinks:INFO: Disabling clock on downlink 1
08:33:50:elinks:INFO: Disabling clock on downlink 2
08:33:50:elinks:INFO: Disabling clock on downlink 3
08:33:50:elinks:INFO: Disabling clock on downlink 4
08:33:50:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:33:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:33:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:33:51:elinks:INFO: Disabling clock on downlink 0
08:33:51:elinks:INFO: Disabling clock on downlink 1
08:33:51:elinks:INFO: Disabling clock on downlink 2
08:33:51:elinks:INFO: Disabling clock on downlink 3
08:33:51:elinks:INFO: Disabling clock on downlink 4
08:33:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:33:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:33:51:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:33:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:33:51:elinks:INFO: Disabling clock on downlink 0
08:33:51:elinks:INFO: Disabling clock on downlink 1
08:33:51:elinks:INFO: Disabling clock on downlink 2
08:33:51:elinks:INFO: Disabling clock on downlink 3
08:33:51:elinks:INFO: Disabling clock on downlink 4
08:33:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:33:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:33:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:33:51:elinks:INFO: Disabling clock on downlink 0
08:33:51:elinks:INFO: Disabling clock on downlink 1
08:33:51:elinks:INFO: Disabling clock on downlink 2
08:33:51:elinks:INFO: Disabling clock on downlink 3
08:33:51:elinks:INFO: Disabling clock on downlink 4
08:33:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:33:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:33:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:33:51:elinks:INFO: Disabling clock on downlink 0
08:33:51:elinks:INFO: Disabling clock on downlink 1
08:33:51:elinks:INFO: Disabling clock on downlink 2
08:33:51:elinks:INFO: Disabling clock on downlink 3
08:33:51:elinks:INFO: Disabling clock on downlink 4
08:33:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:33:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:33:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:33:51:setup_element:INFO: Scanning clock phase
08:33:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:33:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:52:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:33:52:setup_element:INFO: Eye window for uplink 0 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:33:52:setup_element:INFO: Eye window for uplink 1 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:33:52:setup_element:INFO: Eye window for uplink 2 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
08:33:52:setup_element:INFO: Eye window for uplink 3 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
08:33:52:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:33:52:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:33:52:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:33:52:setup_element:INFO: Eye window for uplink 14: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:33:52:setup_element:INFO: Eye window for uplink 15: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:33:52:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
08:33:52:setup_element:INFO: Scanning data phases
08:33:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:33:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:57:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:33:57:setup_element:INFO: Eye window for uplink 0 : ___________XXXXXX_______________________
Data delay found: 33
08:33:57:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________
Data delay found: 29
08:33:57:setup_element:INFO: Eye window for uplink 2 : _________XXXXX__________________________
Data delay found: 31
08:33:57:setup_element:INFO: Eye window for uplink 3 : ______XXXXX_____________________________
Data delay found: 28
08:33:57:setup_element:INFO: Eye window for uplink 4 : ___XXXXX________________________________
Data delay found: 25
08:33:57:setup_element:INFO: Eye window for uplink 5 : XXXX__________________________________XX
Data delay found: 20
08:33:57:setup_element:INFO: Eye window for uplink 6 : _XXXX___________________________________
Data delay found: 22
08:33:57:setup_element:INFO: Eye window for uplink 7 : XX__________________________________XXXX
Data delay found: 18
08:33:57:setup_element:INFO: Eye window for uplink 8 : ________________________XXXX____________
Data delay found: 5
08:33:57:setup_element:INFO: Eye window for uplink 9 : ____________________________XXXXXX______
Data delay found: 10
08:33:57:setup_element:INFO: Eye window for uplink 10: ____________________________XXXX________
Data delay found: 9
08:33:57:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXXX___
Data delay found: 13
08:33:57:setup_element:INFO: Eye window for uplink 12: ___________________________XXXXXX_______
Data delay found: 9
08:33:57:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
08:33:57:setup_element:INFO: Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
08:33:57:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
08:33:57:setup_element:INFO: Setting the data phase to 33 for uplink 0
08:33:57:setup_element:INFO: Setting the data phase to 29 for uplink 1
08:33:57:setup_element:INFO: Setting the data phase to 31 for uplink 2
08:33:57:setup_element:INFO: Setting the data phase to 28 for uplink 3
08:33:57:setup_element:INFO: Setting the data phase to 25 for uplink 4
08:33:57:setup_element:INFO: Setting the data phase to 20 for uplink 5
08:33:57:setup_element:INFO: Setting the data phase to 22 for uplink 6
08:33:57:setup_element:INFO: Setting the data phase to 18 for uplink 7
08:33:57:setup_element:INFO: Setting the data phase to 5 for uplink 8
08:33:57:setup_element:INFO: Setting the data phase to 10 for uplink 9
08:33:57:setup_element:INFO: Setting the data phase to 9 for uplink 10
08:33:57:setup_element:INFO: Setting the data phase to 13 for uplink 11
08:33:57:setup_element:INFO: Setting the data phase to 9 for uplink 12
08:33:57:setup_element:INFO: Setting the data phase to 13 for uplink 13
08:33:57:setup_element:INFO: Setting the data phase to 10 for uplink 14
08:33:57:setup_element:INFO: Setting the data phase to 13 for uplink 15
08:33:57:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXXX
Uplink 1: ________________________________________________________________________XXXXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXXX
Uplink 7: ________________________________________________________________________XXXXXXXX
Uplink 8: ______________________________________________________________________XXXXXXXXX_
Uplink 9: ______________________________________________________________________XXXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: _______________________________________________________________________XXXXXXX__
Uplink 13: _______________________________________________________________________XXXXXXX__
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 4:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 22
Window Length: 36
Eye Window: _XXXX___________________________________
Uplink 7:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 8:
Optimal Phase: 5
Window Length: 36
Eye Window: ________________________XXXX____________
Uplink 9:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 10:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 11:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 12:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
]
08:33:57:setup_element:INFO: Beginning SMX ASICs map scan
08:33:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:33:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:33:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:33:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:33:57:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:33:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:33:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:33:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:33:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:33:57:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:33:57:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:33:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:33:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:33:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:33:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:33:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:33:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:33:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:33:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:33:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:33:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:34:00:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXXX
Uplink 1: ________________________________________________________________________XXXXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: ________________________________________________________________________XXXXXXXX
Uplink 7: ________________________________________________________________________XXXXXXXX
Uplink 8: ______________________________________________________________________XXXXXXXXX_
Uplink 9: ______________________________________________________________________XXXXXXXXX_
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: _______________________________________________________________________XXXXXXX__
Uplink 13: _______________________________________________________________________XXXXXXX__
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 3:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 4:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 5:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 6:
Optimal Phase: 22
Window Length: 36
Eye Window: _XXXX___________________________________
Uplink 7:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 8:
Optimal Phase: 5
Window Length: 36
Eye Window: ________________________XXXX____________
Uplink 9:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 10:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 11:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 12:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
08:34:00:setup_element:INFO: Performing Elink synchronization
08:34:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:34:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:34:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:34:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:34:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:34:00:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:34:00:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
08:34:01:febtest:INFO: Init all SMX (CSA): 30
08:34:16:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:34:16:febtest:INFO: 01-00 | XA-000-08-002-000-007-085-04 | 21.9 | 1201.0
08:34:16:febtest:INFO: 08-01 | XA-000-08-002-000-007-084-04 | 28.2 | 1177.4
08:34:16:febtest:INFO: 03-02 | XA-000-08-002-002-008-156-06 | 40.9 | 1147.8
08:34:17:febtest:INFO: 10-03 | XA-000-08-002-002-008-152-06 | 40.9 | 1135.9
08:34:17:febtest:INFO: 05-04 | XA-000-08-002-000-007-075-03 | 25.1 | 1206.9
08:34:17:febtest:INFO: 12-05 | XA-000-08-002-002-008-150-06 | 28.2 | 1183.3
08:34:17:febtest:INFO: 07-06 | XA-000-08-002-000-007-086-04 | 47.3 | 1130.0
08:34:18:febtest:INFO: 14-07 | XA-000-08-002-002-008-153-06 | 34.6 | 1159.7
08:34:19:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:34:21:ST3_smx:INFO: chip: 1-0 21.902970 C 1218.600960 mV
08:34:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:21:ST3_smx:INFO: Electrons
08:34:21:ST3_smx:INFO: # loops 0
08:34:23:ST3_smx:INFO: # loops 1
08:34:24:ST3_smx:INFO: # loops 2
08:34:26:ST3_smx:INFO: # loops 3
08:34:28:ST3_smx:INFO: # loops 4
08:34:30:ST3_smx:INFO: Total # of broken channels: 0
08:34:30:ST3_smx:INFO: List of broken channels: []
08:34:30:ST3_smx:INFO: Total # of broken channels: 0
08:34:30:ST3_smx:INFO: List of broken channels: []
08:34:31:ST3_smx:INFO: chip: 8-1 28.225000 C 1189.190035 mV
08:34:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:31:ST3_smx:INFO: Electrons
08:34:31:ST3_smx:INFO: # loops 0
08:34:33:ST3_smx:INFO: # loops 1
08:34:35:ST3_smx:INFO: # loops 2
08:34:36:ST3_smx:INFO: # loops 3
08:34:38:ST3_smx:INFO: # loops 4
08:34:39:ST3_smx:INFO: Total # of broken channels: 0
08:34:39:ST3_smx:INFO: List of broken channels: []
08:34:39:ST3_smx:INFO: Total # of broken channels: 0
08:34:39:ST3_smx:INFO: List of broken channels: []
08:34:41:ST3_smx:INFO: chip: 3-2 40.898880 C 1165.571835 mV
08:34:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:41:ST3_smx:INFO: Electrons
08:34:41:ST3_smx:INFO: # loops 0
08:34:43:ST3_smx:INFO: # loops 1
08:34:44:ST3_smx:INFO: # loops 2
08:34:46:ST3_smx:INFO: # loops 3
08:34:48:ST3_smx:INFO: # loops 4
08:34:49:ST3_smx:INFO: Total # of broken channels: 0
08:34:49:ST3_smx:INFO: List of broken channels: []
08:34:49:ST3_smx:INFO: Total # of broken channels: 1
08:34:49:ST3_smx:INFO: List of broken channels: [126]
08:34:51:ST3_smx:INFO: chip: 10-3 40.898880 C 1147.806000 mV
08:34:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:34:51:ST3_smx:INFO: Electrons
08:34:51:ST3_smx:INFO: # loops 0
08:34:53:ST3_smx:INFO: # loops 1
08:34:54:ST3_smx:INFO: # loops 2
08:34:56:ST3_smx:INFO: # loops 3
08:34:58:ST3_smx:INFO: # loops 4
08:34:59:ST3_smx:INFO: Total # of broken channels: 0
08:34:59:ST3_smx:INFO: List of broken channels: []
08:34:59:ST3_smx:INFO: Total # of broken channels: 0
08:34:59:ST3_smx:INFO: List of broken channels: []
08:35:01:ST3_smx:INFO: chip: 5-4 28.225000 C 1218.600960 mV
08:35:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:01:ST3_smx:INFO: Electrons
08:35:01:ST3_smx:INFO: # loops 0
08:35:03:ST3_smx:INFO: # loops 1
08:35:04:ST3_smx:INFO: # loops 2
08:35:06:ST3_smx:INFO: # loops 3
08:35:08:ST3_smx:INFO: # loops 4
08:35:09:ST3_smx:INFO: Total # of broken channels: 0
08:35:09:ST3_smx:INFO: List of broken channels: []
08:35:09:ST3_smx:INFO: Total # of broken channels: 0
08:35:09:ST3_smx:INFO: List of broken channels: []
08:35:11:ST3_smx:INFO: chip: 12-5 28.225000 C 1195.082160 mV
08:35:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:11:ST3_smx:INFO: Electrons
08:35:11:ST3_smx:INFO: # loops 0
08:35:13:ST3_smx:INFO: # loops 1
08:35:14:ST3_smx:INFO: # loops 2
08:35:16:ST3_smx:INFO: # loops 3
08:35:17:ST3_smx:INFO: # loops 4
08:35:19:ST3_smx:INFO: Total # of broken channels: 0
08:35:19:ST3_smx:INFO: List of broken channels: []
08:35:19:ST3_smx:INFO: Total # of broken channels: 0
08:35:19:ST3_smx:INFO: List of broken channels: []
08:35:21:ST3_smx:INFO: chip: 7-6 50.430383 C 1135.937260 mV
08:35:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:21:ST3_smx:INFO: Electrons
08:35:21:ST3_smx:INFO: # loops 0
08:35:23:ST3_smx:INFO: # loops 1
08:35:24:ST3_smx:INFO: # loops 2
08:35:26:ST3_smx:INFO: # loops 3
08:35:28:ST3_smx:INFO: # loops 4
08:35:29:ST3_smx:INFO: Total # of broken channels: 0
08:35:29:ST3_smx:INFO: List of broken channels: []
08:35:29:ST3_smx:INFO: Total # of broken channels: 0
08:35:29:ST3_smx:INFO: List of broken channels: []
08:35:31:ST3_smx:INFO: chip: 14-7 34.556970 C 1171.483840 mV
08:35:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:31:ST3_smx:INFO: Electrons
08:35:31:ST3_smx:INFO: # loops 0
08:35:33:ST3_smx:INFO: # loops 1
08:35:35:ST3_smx:INFO: # loops 2
08:35:36:ST3_smx:INFO: # loops 3
08:35:38:ST3_smx:INFO: # loops 4
08:35:40:ST3_smx:INFO: Total # of broken channels: 0
08:35:40:ST3_smx:INFO: List of broken channels: []
08:35:40:ST3_smx:INFO: Total # of broken channels: 1
08:35:40:ST3_smx:INFO: List of broken channels: [77]
08:35:40:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:35:40:febtest:INFO: 01-00 | XA-000-08-002-000-007-085-04 | 25.1 | 1236.2
08:35:40:febtest:INFO: 08-01 | XA-000-08-002-000-007-084-04 | 28.2 | 1212.7
08:35:41:febtest:INFO: 03-02 | XA-000-08-002-002-008-156-06 | 44.1 | 1189.2
08:35:41:febtest:INFO: 10-03 | XA-000-08-002-002-008-152-06 | 40.9 | 1171.5
08:35:41:febtest:INFO: 05-04 | XA-000-08-002-000-007-075-03 | 28.2 | 1236.2
08:35:41:febtest:INFO: 12-05 | XA-000-08-002-002-008-150-06 | 28.2 | 1218.6
08:35:42:febtest:INFO: 07-06 | XA-000-08-002-000-007-086-04 | 50.4 | 1159.7
08:35:42:febtest:INFO: 14-07 | XA-000-08-002-002-008-153-06 | 37.7 | 1189.2
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_04-08_33_29
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1170| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 25123
MODULE_NAME: L7DL300122 M7DL3T1001221A2 62 B
MODULE_TYPE:
MODULE_LADDER: L7DL300122
MODULE_MODULE: M7DL3T1001221A2
MODULE_SIZE: 62
MODULE_GRADE: B
------------------------------------------------------------
VI_before_Init : ['2.450', '1.4680', '1.850', '2.5130', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0290', '1.850', '2.4550', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9780', '1.850', '0.5239', '0.000', '0.0000', '0.000', '0.0000']