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FEB_1172 29.05.24 12:52:40
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12:52:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:52:40:ST3_Shared:INFO: FEB-Sensor
12:52:40:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:52:54:ST3_ModuleSelector:INFO: New Sensor ID: 1238
12:52:55:ST3_ModuleSelector:INFO: New Sensor ID: 12384
12:52:56:ST3_ModuleSelector:INFO: L4DL000161 M4DL0B2001612B2 124 A
12:52:56:ST3_ModuleSelector:INFO: 12384
12:52:56:febtest:INFO: Testing FEB with SN 1172
12:52:58:smx_tester:INFO: Scanning setup
12:52:58:elinks:INFO: Disabling clock on downlink 0
12:52:58:elinks:INFO: Disabling clock on downlink 1
12:52:58:elinks:INFO: Disabling clock on downlink 2
12:52:58:elinks:INFO: Disabling clock on downlink 3
12:52:58:elinks:INFO: Disabling clock on downlink 4
12:52:58:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
12:52:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:58:elinks:INFO: Disabling clock on downlink 0
12:52:58:elinks:INFO: Disabling clock on downlink 1
12:52:58:elinks:INFO: Disabling clock on downlink 2
12:52:58:elinks:INFO: Disabling clock on downlink 3
12:52:58:elinks:INFO: Disabling clock on downlink 4
12:52:58:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
12:52:58:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
12:52:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:58:elinks:INFO: Disabling clock on downlink 0
12:52:58:elinks:INFO: Disabling clock on downlink 1
12:52:58:elinks:INFO: Disabling clock on downlink 2
12:52:59:elinks:INFO: Disabling clock on downlink 3
12:52:59:elinks:INFO: Disabling clock on downlink 4
12:52:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:52:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:59:elinks:INFO: Disabling clock on downlink 0
12:52:59:elinks:INFO: Disabling clock on downlink 1
12:52:59:elinks:INFO: Disabling clock on downlink 2
12:52:59:elinks:INFO: Disabling clock on downlink 3
12:52:59:elinks:INFO: Disabling clock on downlink 4
12:52:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
12:52:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:59:elinks:INFO: Disabling clock on downlink 0
12:52:59:elinks:INFO: Disabling clock on downlink 1
12:52:59:elinks:INFO: Disabling clock on downlink 2
12:52:59:elinks:INFO: Disabling clock on downlink 3
12:52:59:elinks:INFO: Disabling clock on downlink 4
12:52:59:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:52:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
12:52:59:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:52:59:setup_element:INFO: Scanning clock phase
12:52:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:52:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:52:59:setup_element:INFO: Clock phase scan results for group 0, downlink 1
12:52:59:setup_element:INFO: Eye window for uplink 0 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:52:59:setup_element:INFO: Eye window for uplink 1 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:52:59:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:52:59:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
12:52:59:setup_element:INFO: Eye window for uplink 4 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 5 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXX___
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:52:59:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:59:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
12:52:59:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
12:52:59:setup_element:INFO: Scanning data phases
12:52:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:52:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:53:05:setup_element:INFO: Data phase scan results for group 0, downlink 1
12:53:05:setup_element:INFO: Eye window for uplink 0 : ____________XXXXX_______________________
Data delay found: 34
12:53:05:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________
Data delay found: 29
12:53:05:setup_element:INFO: Eye window for uplink 2 : _______XXXXX____________________________
Data delay found: 29
12:53:05:setup_element:INFO: Eye window for uplink 3 : ____XXXXX_______________________________
Data delay found: 26
12:53:05:setup_element:INFO: Eye window for uplink 4 : _____XXXX_______________________________
Data delay found: 26
12:53:05:setup_element:INFO: Eye window for uplink 5 : _XXXXX__________________________________
Data delay found: 23
12:53:05:setup_element:INFO: Eye window for uplink 6 : XXX____________________________________X
Data delay found: 20
12:53:05:setup_element:INFO: Eye window for uplink 7 : X_________________________________XXXXX_
Data delay found: 17
12:53:05:setup_element:INFO: Eye window for uplink 8 : ________________________XXXXX___________
Data delay found: 6
12:53:05:setup_element:INFO: Eye window for uplink 9 : _____________________________XXXXXX_____
Data delay found: 11
12:53:05:setup_element:INFO: Eye window for uplink 10: __________________________XXXXXX________
Data delay found: 8
12:53:05:setup_element:INFO: Eye window for uplink 11: ______________________________XXXXX_____
Data delay found: 12
12:53:05:setup_element:INFO: Eye window for uplink 12: ____________________________XXXXX_______
Data delay found: 10
12:53:05:setup_element:INFO: Eye window for uplink 13: _______________________________XXXXX____
Data delay found: 13
12:53:05:setup_element:INFO: Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
12:53:05:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
12:53:05:setup_element:INFO: Setting the data phase to 34 for uplink 0
12:53:05:setup_element:INFO: Setting the data phase to 29 for uplink 1
12:53:05:setup_element:INFO: Setting the data phase to 29 for uplink 2
12:53:05:setup_element:INFO: Setting the data phase to 26 for uplink 3
12:53:05:setup_element:INFO: Setting the data phase to 26 for uplink 4
12:53:05:setup_element:INFO: Setting the data phase to 23 for uplink 5
12:53:05:setup_element:INFO: Setting the data phase to 20 for uplink 6
12:53:05:setup_element:INFO: Setting the data phase to 17 for uplink 7
12:53:05:setup_element:INFO: Setting the data phase to 6 for uplink 8
12:53:05:setup_element:INFO: Setting the data phase to 11 for uplink 9
12:53:05:setup_element:INFO: Setting the data phase to 8 for uplink 10
12:53:05:setup_element:INFO: Setting the data phase to 12 for uplink 11
12:53:05:setup_element:INFO: Setting the data phase to 10 for uplink 12
12:53:05:setup_element:INFO: Setting the data phase to 13 for uplink 13
12:53:05:setup_element:INFO: Setting the data phase to 10 for uplink 14
12:53:05:setup_element:INFO: Setting the data phase to 13 for uplink 15
12:53:05:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXXX_
Uplink 1: _______________________________________________________________________XXXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXX___
Uplink 7: _______________________________________________________________________XXXXXX___
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXX___
Uplink 11: ______________________________________________________________________XXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 4:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 36
Eye Window: XXX____________________________________X
Uplink 7:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
]
12:53:05:setup_element:INFO: Beginning SMX ASICs map scan
12:53:05:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:53:05:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:53:05:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
12:53:05:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
12:53:05:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
12:53:05:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
12:53:05:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
12:53:05:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
12:53:05:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
12:53:06:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
12:53:06:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
12:53:06:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
12:53:06:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
12:53:06:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
12:53:06:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
12:53:06:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
12:53:06:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
12:53:06:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
12:53:06:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
12:53:06:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
12:53:07:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
12:53:08:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 71
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXXX_
Uplink 1: _______________________________________________________________________XXXXXXXX_
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXX___
Uplink 7: _______________________________________________________________________XXXXXX___
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXX___
Uplink 11: ______________________________________________________________________XXXXXXX___
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: _______________________________________________________________________XXXXXXX__
Uplink 15: _______________________________________________________________________XXXXXXX__
Data phase characteristics:
Uplink 0:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 3:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 4:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 36
Eye Window: XXX____________________________________X
Uplink 7:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 10:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 11:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 12:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 13:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 14:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
12:53:08:setup_element:INFO: Performing Elink synchronization
12:53:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:53:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:53:08:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
12:53:08:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
12:53:08:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
12:53:08:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
12:53:08:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
12:53:09:febtest:INFO: Init all SMX (CSA): 30
12:53:23:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:53:23:febtest:INFO: 01-00 | XA-000-08-002-002-008-168-15 | 34.6 | 1130.0
12:53:24:febtest:INFO: 08-01 | XA-000-08-002-002-006-148-15 | 28.2 | 1159.7
12:53:24:febtest:INFO: 03-02 | XA-000-08-002-002-008-173-15 | 31.4 | 1153.7
12:53:24:febtest:INFO: 10-03 | XA-000-08-002-002-008-185-08 | 31.4 | 1147.8
12:53:24:febtest:INFO: 05-04 | XA-000-08-002-002-008-169-15 | 40.9 | 1124.0
12:53:24:febtest:INFO: 12-05 | XA-000-08-002-002-008-188-08 | 37.7 | 1135.9
12:53:25:febtest:INFO: 07-06 | XA-000-08-002-002-008-176-08 | 28.2 | 1177.4
12:53:25:febtest:INFO: 14-07 | XA-000-08-002-002-008-179-08 | 34.6 | 1141.9
12:53:26:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
12:53:28:ST3_smx:INFO: chip: 1-0 37.726682 C 1141.874115 mV
12:53:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:28:ST3_smx:INFO: Electrons
12:53:28:ST3_smx:INFO: # loops 0
12:53:30:ST3_smx:INFO: # loops 1
12:53:31:ST3_smx:INFO: # loops 2
12:53:33:ST3_smx:INFO: # loops 3
12:53:35:ST3_smx:INFO: # loops 4
12:53:36:ST3_smx:INFO: Total # of broken channels: 0
12:53:36:ST3_smx:INFO: List of broken channels: []
12:53:36:ST3_smx:INFO: Total # of broken channels: 0
12:53:36:ST3_smx:INFO: List of broken channels: []
12:53:38:ST3_smx:INFO: chip: 8-1 28.225000 C 1171.483840 mV
12:53:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:38:ST3_smx:INFO: Electrons
12:53:38:ST3_smx:INFO: # loops 0
12:53:40:ST3_smx:INFO: # loops 1
12:53:41:ST3_smx:INFO: # loops 2
12:53:43:ST3_smx:INFO: # loops 3
12:53:45:ST3_smx:INFO: # loops 4
12:53:46:ST3_smx:INFO: Total # of broken channels: 0
12:53:46:ST3_smx:INFO: List of broken channels: []
12:53:46:ST3_smx:INFO: Total # of broken channels: 0
12:53:46:ST3_smx:INFO: List of broken channels: []
12:53:48:ST3_smx:INFO: chip: 3-2 34.556970 C 1159.654860 mV
12:53:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:48:ST3_smx:INFO: Electrons
12:53:48:ST3_smx:INFO: # loops 0
12:53:50:ST3_smx:INFO: # loops 1
12:53:51:ST3_smx:INFO: # loops 2
12:53:53:ST3_smx:INFO: # loops 3
12:53:54:ST3_smx:INFO: # loops 4
12:53:56:ST3_smx:INFO: Total # of broken channels: 0
12:53:56:ST3_smx:INFO: List of broken channels: []
12:53:56:ST3_smx:INFO: Total # of broken channels: 0
12:53:56:ST3_smx:INFO: List of broken channels: []
12:53:58:ST3_smx:INFO: chip: 10-3 31.389742 C 1159.654860 mV
12:53:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:53:58:ST3_smx:INFO: Electrons
12:53:58:ST3_smx:INFO: # loops 0
12:54:00:ST3_smx:INFO: # loops 1
12:54:01:ST3_smx:INFO: # loops 2
12:54:03:ST3_smx:INFO: # loops 3
12:54:05:ST3_smx:INFO: # loops 4
12:54:06:ST3_smx:INFO: Total # of broken channels: 0
12:54:06:ST3_smx:INFO: List of broken channels: []
12:54:06:ST3_smx:INFO: Total # of broken channels: 0
12:54:06:ST3_smx:INFO: List of broken channels: []
12:54:08:ST3_smx:INFO: chip: 5-4 40.898880 C 1129.995435 mV
12:54:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:08:ST3_smx:INFO: Electrons
12:54:08:ST3_smx:INFO: # loops 0
12:54:10:ST3_smx:INFO: # loops 1
12:54:11:ST3_smx:INFO: # loops 2
12:54:13:ST3_smx:INFO: # loops 3
12:54:15:ST3_smx:INFO: # loops 4
12:54:16:ST3_smx:INFO: Total # of broken channels: 0
12:54:16:ST3_smx:INFO: List of broken channels: []
12:54:16:ST3_smx:INFO: Total # of broken channels: 0
12:54:16:ST3_smx:INFO: List of broken channels: []
12:54:18:ST3_smx:INFO: chip: 12-5 37.726682 C 1141.874115 mV
12:54:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:18:ST3_smx:INFO: Electrons
12:54:18:ST3_smx:INFO: # loops 0
12:54:19:ST3_smx:INFO: # loops 1
12:54:21:ST3_smx:INFO: # loops 2
12:54:23:ST3_smx:INFO: # loops 3
12:54:24:ST3_smx:INFO: # loops 4
12:54:26:ST3_smx:INFO: Total # of broken channels: 0
12:54:26:ST3_smx:INFO: List of broken channels: []
12:54:26:ST3_smx:INFO: Total # of broken channels: 1
12:54:26:ST3_smx:INFO: List of broken channels: [127]
12:54:28:ST3_smx:INFO: chip: 7-6 28.225000 C 1183.292940 mV
12:54:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:28:ST3_smx:INFO: Electrons
12:54:28:ST3_smx:INFO: # loops 0
12:54:29:ST3_smx:INFO: # loops 1
12:54:31:ST3_smx:INFO: # loops 2
12:54:33:ST3_smx:INFO: # loops 3
12:54:34:ST3_smx:INFO: # loops 4
12:54:36:ST3_smx:INFO: Total # of broken channels: 0
12:54:36:ST3_smx:INFO: List of broken channels: []
12:54:36:ST3_smx:INFO: Total # of broken channels: 0
12:54:36:ST3_smx:INFO: List of broken channels: []
12:54:38:ST3_smx:INFO: chip: 14-7 37.726682 C 1153.732915 mV
12:54:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
12:54:38:ST3_smx:INFO: Electrons
12:54:38:ST3_smx:INFO: # loops 0
12:54:40:ST3_smx:INFO: # loops 1
12:54:41:ST3_smx:INFO: # loops 2
12:54:43:ST3_smx:INFO: # loops 3
12:54:44:ST3_smx:INFO: # loops 4
12:54:46:ST3_smx:INFO: Total # of broken channels: 0
12:54:46:ST3_smx:INFO: List of broken channels: []
12:54:46:ST3_smx:INFO: Total # of broken channels: 0
12:54:46:ST3_smx:INFO: List of broken channels: []
12:54:46:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:54:47:febtest:INFO: 01-00 | XA-000-08-002-002-008-168-15 | 40.9 | 1159.7
12:54:47:febtest:INFO: 08-01 | XA-000-08-002-002-006-148-15 | 31.4 | 1195.1
12:54:47:febtest:INFO: 03-02 | XA-000-08-002-002-008-173-15 | 34.6 | 1183.3
12:54:47:febtest:INFO: 10-03 | XA-000-08-002-002-008-185-08 | 34.6 | 1177.4
12:54:48:febtest:INFO: 05-04 | XA-000-08-002-002-008-169-15 | 44.1 | 1147.8
12:54:48:febtest:INFO: 12-05 | XA-000-08-002-002-008-188-08 | 40.9 | 1165.6
12:54:48:febtest:INFO: 07-06 | XA-000-08-002-002-008-176-08 | 31.4 | 1201.0
12:54:48:febtest:INFO: 14-07 | XA-000-08-002-002-008-179-08 | 40.9 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_05_29-12_52_40
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1172| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 12384
MODULE_NAME: L4DL000161 M4DL0B2001612B2 124 A
MODULE_TYPE:
MODULE_LADDER:
MODULE_MODULE:
MODULE_SIZE: 0
MODULE_GRADE:
------------------------------------------------------------
VI_before_Init : ['2.450', '1.5640', '1.849', '2.7620', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0760', '1.850', '2.5260', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9970', '1.850', '0.5308', '0.000', '0.0000', '0.000', '0.0000']