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FEB_1173 05.06.24 08:27:47
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08:27:47:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:27:47:ST3_Shared:INFO: FEB-Sensor
08:27:47:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:28:16:ST3_ModuleSelector:INFO: New Sensor ID: 0722
08:28:17:ST3_ModuleSelector:INFO: New Sensor ID: 07222
08:28:21:ST3_ModuleSelector:INFO: L7DL300122 M7DL3B0001220B2 42 A
08:28:21:ST3_ModuleSelector:INFO: 07222
08:28:21:febtest:INFO: Testing FEB with SN 1173
08:28:22:smx_tester:INFO: Scanning setup
08:28:22:elinks:INFO: Disabling clock on downlink 0
08:28:22:elinks:INFO: Disabling clock on downlink 1
08:28:22:elinks:INFO: Disabling clock on downlink 2
08:28:22:elinks:INFO: Disabling clock on downlink 3
08:28:22:elinks:INFO: Disabling clock on downlink 4
08:28:22:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:28:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:28:22:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:28:22:elinks:INFO: Disabling clock on downlink 0
08:28:22:elinks:INFO: Disabling clock on downlink 1
08:28:22:elinks:INFO: Disabling clock on downlink 2
08:28:22:elinks:INFO: Disabling clock on downlink 3
08:28:22:elinks:INFO: Disabling clock on downlink 4
08:28:22:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:28:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:28:23:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:28:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:28:23:elinks:INFO: Disabling clock on downlink 0
08:28:23:elinks:INFO: Disabling clock on downlink 1
08:28:23:elinks:INFO: Disabling clock on downlink 2
08:28:23:elinks:INFO: Disabling clock on downlink 3
08:28:23:elinks:INFO: Disabling clock on downlink 4
08:28:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:28:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:28:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:28:23:elinks:INFO: Disabling clock on downlink 0
08:28:23:elinks:INFO: Disabling clock on downlink 1
08:28:23:elinks:INFO: Disabling clock on downlink 2
08:28:23:elinks:INFO: Disabling clock on downlink 3
08:28:23:elinks:INFO: Disabling clock on downlink 4
08:28:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:28:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:28:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:28:23:elinks:INFO: Disabling clock on downlink 0
08:28:23:elinks:INFO: Disabling clock on downlink 1
08:28:23:elinks:INFO: Disabling clock on downlink 2
08:28:23:elinks:INFO: Disabling clock on downlink 3
08:28:23:elinks:INFO: Disabling clock on downlink 4
08:28:23:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:28:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:28:23:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:28:23:setup_element:INFO: Scanning clock phase
08:28:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:28:23:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:28:23:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:28:23:setup_element:INFO: Eye window for uplink 0 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
08:28:23:setup_element:INFO: Eye window for uplink 1 : _________________________________________________________________________XXXXXXX
Clock Delay: 36
08:28:23:setup_element:INFO: Eye window for uplink 2 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 3 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 4 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 5 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:28:23:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:28:23:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:28:23:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:28:23:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:28:23:setup_element:INFO: Eye window for uplink 14: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:28:23:setup_element:INFO: Eye window for uplink 15: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:28:23:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
08:28:23:setup_element:INFO: Scanning data phases
08:28:23:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:28:24:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:28:29:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:28:29:setup_element:INFO: Eye window for uplink 0 : _____________XXXXXX_____________________
Data delay found: 35
08:28:29:setup_element:INFO: Eye window for uplink 1 : _________XXXXX__________________________
Data delay found: 31
08:28:29:setup_element:INFO: Eye window for uplink 2 : _______XXXX_____________________________
Data delay found: 28
08:28:29:setup_element:INFO: Eye window for uplink 3 : ____XXXXX_______________________________
Data delay found: 26
08:28:29:setup_element:INFO: Eye window for uplink 4 : _____XXXXX______________________________
Data delay found: 27
08:28:29:setup_element:INFO: Eye window for uplink 5 : _XXXXX__________________________________
Data delay found: 23
08:28:29:setup_element:INFO: Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
08:28:29:setup_element:INFO: Eye window for uplink 7 : _________________________________XXXXXX_
Data delay found: 15
08:28:29:setup_element:INFO: Eye window for uplink 8 : _________________________XXXX___________
Data delay found: 6
08:28:29:setup_element:INFO: Eye window for uplink 9 : ______________________________XXXXX_____
Data delay found: 12
08:28:29:setup_element:INFO: Eye window for uplink 10: ___________________________XXXXXX_______
Data delay found: 9
08:28:29:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXXX___
Data delay found: 13
08:28:29:setup_element:INFO: Eye window for uplink 12: ___________________________XXXXX________
Data delay found: 9
08:28:29:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXX_____
Data delay found: 12
08:28:29:setup_element:INFO: Eye window for uplink 14: ______________________________XXXX______
Data delay found: 11
08:28:29:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXX____
Data delay found: 13
08:28:29:setup_element:INFO: Setting the data phase to 35 for uplink 0
08:28:29:setup_element:INFO: Setting the data phase to 31 for uplink 1
08:28:29:setup_element:INFO: Setting the data phase to 28 for uplink 2
08:28:29:setup_element:INFO: Setting the data phase to 26 for uplink 3
08:28:29:setup_element:INFO: Setting the data phase to 27 for uplink 4
08:28:29:setup_element:INFO: Setting the data phase to 23 for uplink 5
08:28:29:setup_element:INFO: Setting the data phase to 20 for uplink 6
08:28:29:setup_element:INFO: Setting the data phase to 15 for uplink 7
08:28:29:setup_element:INFO: Setting the data phase to 6 for uplink 8
08:28:29:setup_element:INFO: Setting the data phase to 12 for uplink 9
08:28:29:setup_element:INFO: Setting the data phase to 9 for uplink 10
08:28:29:setup_element:INFO: Setting the data phase to 13 for uplink 11
08:28:29:setup_element:INFO: Setting the data phase to 9 for uplink 12
08:28:29:setup_element:INFO: Setting the data phase to 12 for uplink 13
08:28:29:setup_element:INFO: Setting the data phase to 11 for uplink 14
08:28:29:setup_element:INFO: Setting the data phase to 13 for uplink 15
08:28:29:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ______________________________________________________________________XXXXXXXX__
Uplink 3: ______________________________________________________________________XXXXXXXX__
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXXX__
Uplink 7: _______________________________________________________________________XXXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXXX__
Uplink 9: _____________________________________________________________________XXXXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXXX_
Uplink 13: ______________________________________________________________________XXXXXXXXX_
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 1:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 2:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 3:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 4:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 11:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
]
08:28:29:setup_element:INFO: Beginning SMX ASICs map scan
08:28:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:28:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:28:29:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:28:29:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:28:29:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:28:29:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:28:29:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:28:29:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:28:29:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:28:29:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:28:29:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:28:29:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:28:30:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:28:30:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:28:30:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:28:30:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:28:30:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:28:30:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:28:30:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:28:30:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:28:30:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:28:31:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 69
Eye Windows:
Uplink 0: _________________________________________________________________________XXXXXXX
Uplink 1: _________________________________________________________________________XXXXXXX
Uplink 2: ______________________________________________________________________XXXXXXXX__
Uplink 3: ______________________________________________________________________XXXXXXXX__
Uplink 4: ______________________________________________________________________XXXXXXXX__
Uplink 5: ______________________________________________________________________XXXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXXX__
Uplink 7: _______________________________________________________________________XXXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXXX__
Uplink 9: _____________________________________________________________________XXXXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: ______________________________________________________________________XXXXXXXXX_
Uplink 13: ______________________________________________________________________XXXXXXXXX_
Uplink 14: ________________________________________________________________________XXXXXXX_
Uplink 15: ________________________________________________________________________XXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 1:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 2:
Optimal Phase: 28
Window Length: 36
Eye Window: _______XXXX_____________________________
Uplink 3:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 4:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 35
Eye Window: _XXXXX__________________________________
Uplink 6:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 7:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 8:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 9:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 10:
Optimal Phase: 9
Window Length: 34
Eye Window: ___________________________XXXXXX_______
Uplink 11:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 12:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 13:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 14:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 15:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
08:28:31:setup_element:INFO: Performing Elink synchronization
08:28:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:28:32:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:28:32:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:28:32:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:28:32:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:28:32:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:28:32:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
08:28:32:febtest:INFO: Init all SMX (CSA): 30
08:28:47:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:28:47:febtest:INFO: 01-00 | XA-000-08-002-002-006-175-06 | 15.6 | 1189.2
08:28:47:febtest:INFO: 08-01 | XA-000-08-002-002-006-120-14 | 18.7 | 1183.3
08:28:47:febtest:INFO: 03-02 | XA-000-08-002-002-006-114-14 | 15.6 | 1195.1
08:28:47:febtest:INFO: 10-03 | XA-000-08-002-002-006-132-08 | 15.6 | 1189.2
08:28:48:febtest:INFO: 05-04 | XA-000-08-002-002-006-127-14 | 21.9 | 1183.3
08:28:48:febtest:INFO: 12-05 | XA-000-08-002-002-006-126-14 | 18.7 | 1183.3
08:28:48:febtest:INFO: 07-06 | XA-000-08-002-002-006-171-06 | 21.9 | 1189.2
08:28:48:febtest:INFO: 14-07 | XA-000-08-002-000-007-080-04 | 9.3 | 1212.7
08:28:49:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:28:51:ST3_smx:INFO: chip: 1-0 15.590880 C 1200.969315 mV
08:28:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:51:ST3_smx:INFO: Electrons
08:28:51:ST3_smx:INFO: # loops 0
08:28:53:ST3_smx:INFO: # loops 1
08:28:55:ST3_smx:INFO: # loops 2
08:28:56:ST3_smx:INFO: # loops 3
08:28:58:ST3_smx:INFO: # loops 4
08:28:59:ST3_smx:INFO: Total # of broken channels: 0
08:28:59:ST3_smx:INFO: List of broken channels: []
08:28:59:ST3_smx:INFO: Total # of broken channels: 0
08:28:59:ST3_smx:INFO: List of broken channels: []
08:29:01:ST3_smx:INFO: chip: 8-1 21.902970 C 1195.082160 mV
08:29:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:01:ST3_smx:INFO: Electrons
08:29:01:ST3_smx:INFO: # loops 0
08:29:03:ST3_smx:INFO: # loops 1
08:29:04:ST3_smx:INFO: # loops 2
08:29:06:ST3_smx:INFO: # loops 3
08:29:08:ST3_smx:INFO: # loops 4
08:29:09:ST3_smx:INFO: Total # of broken channels: 0
08:29:09:ST3_smx:INFO: List of broken channels: []
08:29:09:ST3_smx:INFO: Total # of broken channels: 9
08:29:09:ST3_smx:INFO: List of broken channels: [10, 18, 34, 54, 60, 62, 70, 72, 82]
08:29:11:ST3_smx:INFO: chip: 3-2 15.590880 C 1206.851500 mV
08:29:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:11:ST3_smx:INFO: Electrons
08:29:11:ST3_smx:INFO: # loops 0
08:29:13:ST3_smx:INFO: # loops 1
08:29:14:ST3_smx:INFO: # loops 2
08:29:16:ST3_smx:INFO: # loops 3
08:29:18:ST3_smx:INFO: # loops 4
08:29:19:ST3_smx:INFO: Total # of broken channels: 0
08:29:19:ST3_smx:INFO: List of broken channels: []
08:29:19:ST3_smx:INFO: Total # of broken channels: 1
08:29:19:ST3_smx:INFO: List of broken channels: [110]
08:29:21:ST3_smx:INFO: chip: 10-3 15.590880 C 1200.969315 mV
08:29:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:21:ST3_smx:INFO: Electrons
08:29:21:ST3_smx:INFO: # loops 0
08:29:23:ST3_smx:INFO: # loops 1
08:29:24:ST3_smx:INFO: # loops 2
08:29:26:ST3_smx:INFO: # loops 3
08:29:27:ST3_smx:INFO: # loops 4
08:29:29:ST3_smx:INFO: Total # of broken channels: 0
08:29:29:ST3_smx:INFO: List of broken channels: []
08:29:29:ST3_smx:INFO: Total # of broken channels: 1
08:29:29:ST3_smx:INFO: List of broken channels: [70]
08:29:31:ST3_smx:INFO: chip: 5-4 21.902970 C 1195.082160 mV
08:29:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:31:ST3_smx:INFO: Electrons
08:29:31:ST3_smx:INFO: # loops 0
08:29:32:ST3_smx:INFO: # loops 1
08:29:34:ST3_smx:INFO: # loops 2
08:29:36:ST3_smx:INFO: # loops 3
08:29:37:ST3_smx:INFO: # loops 4
08:29:39:ST3_smx:INFO: Total # of broken channels: 0
08:29:39:ST3_smx:INFO: List of broken channels: []
08:29:39:ST3_smx:INFO: Total # of broken channels: 6
08:29:39:ST3_smx:INFO: List of broken channels: [65, 93, 95, 101, 115, 127]
08:29:41:ST3_smx:INFO: chip: 12-5 21.902970 C 1195.082160 mV
08:29:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:41:ST3_smx:INFO: Electrons
08:29:41:ST3_smx:INFO: # loops 0
08:29:42:ST3_smx:INFO: # loops 1
08:29:44:ST3_smx:INFO: # loops 2
08:29:46:ST3_smx:INFO: # loops 3
08:29:47:ST3_smx:INFO: # loops 4
08:29:49:ST3_smx:INFO: Total # of broken channels: 0
08:29:49:ST3_smx:INFO: List of broken channels: []
08:29:49:ST3_smx:INFO: Total # of broken channels: 0
08:29:49:ST3_smx:INFO: List of broken channels: []
08:29:50:ST3_smx:INFO: chip: 7-6 21.902970 C 1200.969315 mV
08:29:50:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:51:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:51:ST3_smx:INFO: Electrons
08:29:51:ST3_smx:INFO: # loops 0
08:29:52:ST3_smx:INFO: # loops 1
08:29:54:ST3_smx:INFO: # loops 2
08:29:55:ST3_smx:INFO: # loops 3
08:29:57:ST3_smx:INFO: # loops 4
08:29:58:ST3_smx:INFO: Total # of broken channels: 0
08:29:58:ST3_smx:INFO: List of broken channels: []
08:29:58:ST3_smx:INFO: Total # of broken channels: 0
08:29:58:ST3_smx:INFO: List of broken channels: []
08:30:00:ST3_smx:INFO: chip: 14-7 12.438562 C 1224.468235 mV
08:30:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:30:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:30:00:ST3_smx:INFO: Electrons
08:30:00:ST3_smx:INFO: # loops 0
08:30:02:ST3_smx:INFO: # loops 1
08:30:03:ST3_smx:INFO: # loops 2
08:30:05:ST3_smx:INFO: # loops 3
08:30:06:ST3_smx:INFO: # loops 4
08:30:08:ST3_smx:INFO: Total # of broken channels: 0
08:30:08:ST3_smx:INFO: List of broken channels: []
08:30:08:ST3_smx:INFO: Total # of broken channels: 1
08:30:08:ST3_smx:INFO: List of broken channels: [15]
08:30:08:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:30:09:febtest:INFO: 01-00 | XA-000-08-002-002-006-175-06 | 18.7 | 1218.6
08:30:09:febtest:INFO: 08-01 | XA-000-08-002-002-006-120-14 | 21.9 | 1218.6
08:30:09:febtest:INFO: 03-02 | XA-000-08-002-002-006-114-14 | 18.7 | 1224.5
08:30:09:febtest:INFO: 10-03 | XA-000-08-002-002-006-132-08 | 18.7 | 1224.5
08:30:09:febtest:INFO: 05-04 | XA-000-08-002-002-006-127-14 | 25.1 | 1212.7
08:30:10:febtest:INFO: 12-05 | XA-000-08-002-002-006-126-14 | 21.9 | 1212.7
08:30:10:febtest:INFO: 07-06 | XA-000-08-002-002-006-171-06 | 25.1 | 1218.6
08:30:10:febtest:INFO: 14-07 | XA-000-08-002-000-007-080-04 | 15.6 | 1242.0
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_05-08_27_47
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1173| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 07222
MODULE_NAME: L7DL300122 M7DL3B0001220B2 42 A
MODULE_TYPE:
MODULE_LADDER: L7DL300122
MODULE_MODULE: M7DL3B0001220B2
MODULE_SIZE: 42
MODULE_GRADE: A
------------------------------------------------------------
VI_before_Init : ['2.450', '1.9960', '1.850', '2.1660', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9570', '1.850', '2.4200', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9660', '1.850', '0.5194', '0.000', '0.0000', '0.000', '0.0000']