Go Back
FEB_1174 03.06.24 11:29:18
Info
11:29:18:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:29:18:ST3_Shared:INFO: FEB-Sensor
11:29:18:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:29:39:ST3_ModuleSelector:INFO: L7DL300122 M7DL3T3001223A2 124 C
11:29:39:ST3_ModuleSelector:INFO: 26124
11:29:39:febtest:INFO: Testing FEB with SN 1174
11:29:41:smx_tester:INFO: Scanning setup
11:29:41:elinks:INFO: Disabling clock on downlink 0
11:29:41:elinks:INFO: Disabling clock on downlink 1
11:29:41:elinks:INFO: Disabling clock on downlink 2
11:29:41:elinks:INFO: Disabling clock on downlink 3
11:29:41:elinks:INFO: Disabling clock on downlink 4
11:29:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:29:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:41:elinks:INFO: Disabling clock on downlink 0
11:29:41:elinks:INFO: Disabling clock on downlink 1
11:29:41:elinks:INFO: Disabling clock on downlink 2
11:29:41:elinks:INFO: Disabling clock on downlink 3
11:29:41:elinks:INFO: Disabling clock on downlink 4
11:29:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
11:29:41:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
11:29:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:41:elinks:INFO: Disabling clock on downlink 0
11:29:41:elinks:INFO: Disabling clock on downlink 1
11:29:41:elinks:INFO: Disabling clock on downlink 2
11:29:41:elinks:INFO: Disabling clock on downlink 3
11:29:41:elinks:INFO: Disabling clock on downlink 4
11:29:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:41:elinks:INFO: Disabling clock on downlink 0
11:29:41:elinks:INFO: Disabling clock on downlink 1
11:29:41:elinks:INFO: Disabling clock on downlink 2
11:29:41:elinks:INFO: Disabling clock on downlink 3
11:29:41:elinks:INFO: Disabling clock on downlink 4
11:29:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:29:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:41:elinks:INFO: Disabling clock on downlink 0
11:29:41:elinks:INFO: Disabling clock on downlink 1
11:29:41:elinks:INFO: Disabling clock on downlink 2
11:29:41:elinks:INFO: Disabling clock on downlink 3
11:29:41:elinks:INFO: Disabling clock on downlink 4
11:29:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:29:42:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:42:setup_element:INFO: Scanning clock phase
11:29:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:29:42:setup_element:INFO: Clock phase scan results for group 0, downlink 1
11:29:42:setup_element:INFO: Eye window for uplink 0 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:29:42:setup_element:INFO: Eye window for uplink 1 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
11:29:42:setup_element:INFO: Eye window for uplink 2 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:29:42:setup_element:INFO: Eye window for uplink 3 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
11:29:42:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:29:42:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:29:42:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:29:42:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:29:42:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:29:42:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:29:42:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:29:42:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:29:42:setup_element:INFO: Eye window for uplink 12: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:29:42:setup_element:INFO: Eye window for uplink 13: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
11:29:42:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:29:42:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:29:42:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
11:29:42:setup_element:INFO: Scanning data phases
11:29:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:29:48:setup_element:INFO: Data phase scan results for group 0, downlink 1
11:29:48:setup_element:INFO: Eye window for uplink 0 : ______________XXXXX_____________________
Data delay found: 36
11:29:48:setup_element:INFO: Eye window for uplink 1 : _________XXXXX__________________________
Data delay found: 31
11:29:48:setup_element:INFO: Eye window for uplink 2 : ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 1
11:29:48:setup_element:INFO: Eye window for uplink 3 : ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 1
11:29:48:setup_element:INFO: Eye window for uplink 4 : _____XXXXX______________________________
Data delay found: 27
11:29:48:setup_element:INFO: Eye window for uplink 5 : __XXXX__________________________________
Data delay found: 23
11:29:48:setup_element:INFO: Eye window for uplink 6 : XXXXX___________________________________
Data delay found: 22
11:29:48:setup_element:INFO: Eye window for uplink 7 : XX__________________________________XXXX
Data delay found: 18
11:29:48:setup_element:INFO: Eye window for uplink 8 : __________________________XXXX__________
Data delay found: 7
11:29:48:setup_element:INFO: Eye window for uplink 9 : _______________________________XXXXX____
Data delay found: 13
11:29:48:setup_element:INFO: Eye window for uplink 10: _____________________________XXXXX______
Data delay found: 11
11:29:48:setup_element:INFO: Eye window for uplink 11: _________________________________XXXXX__
Data delay found: 15
11:29:48:setup_element:INFO: Eye window for uplink 12: _____________________________XXXXX______
Data delay found: 11
11:29:48:setup_element:INFO: Eye window for uplink 13: ________________________________XXXXXX__
Data delay found: 14
11:29:48:setup_element:INFO: Eye window for uplink 14: ____________________________XXXXX_______
Data delay found: 10
11:29:48:setup_element:INFO: Eye window for uplink 15: _____________________________XXXXXXX____
Data delay found: 12
11:29:48:setup_element:INFO: Setting the data phase to 36 for uplink 0
11:29:48:setup_element:INFO: Setting the data phase to 31 for uplink 1
11:29:48:setup_element:INFO: Setting the data phase to 1 for uplink 2
11:29:48:setup_element:INFO: Setting the data phase to 1 for uplink 3
11:29:48:setup_element:INFO: Setting the data phase to 27 for uplink 4
11:29:48:setup_element:INFO: Setting the data phase to 23 for uplink 5
11:29:48:setup_element:INFO: Setting the data phase to 22 for uplink 6
11:29:48:setup_element:INFO: Setting the data phase to 18 for uplink 7
11:29:48:setup_element:INFO: Setting the data phase to 7 for uplink 8
11:29:48:setup_element:INFO: Setting the data phase to 13 for uplink 9
11:29:48:setup_element:INFO: Setting the data phase to 11 for uplink 10
11:29:48:setup_element:INFO: Setting the data phase to 15 for uplink 11
11:29:48:setup_element:INFO: Setting the data phase to 11 for uplink 12
11:29:48:setup_element:INFO: Setting the data phase to 14 for uplink 13
11:29:48:setup_element:INFO: Setting the data phase to 10 for uplink 14
11:29:48:setup_element:INFO: Setting the data phase to 12 for uplink 15
11:29:48:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 1:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 2:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 3:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 4:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 6:
Optimal Phase: 22
Window Length: 35
Eye Window: XXXXX___________________________________
Uplink 7:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 8:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 9:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 10:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 11:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 12:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 13:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 14:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 15:
Optimal Phase: 12
Window Length: 33
Eye Window: _____________________________XXXXXXX____
]
11:29:48:setup_element:INFO: Beginning SMX ASICs map scan
11:29:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:29:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:29:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:29:48:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:29:48:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
11:29:48:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
11:29:48:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
11:29:48:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
11:29:48:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
11:29:48:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
11:29:48:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
11:29:48:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
11:29:48:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
11:29:49:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
11:29:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
11:29:49:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
11:29:49:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
11:29:49:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
11:29:49:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
11:29:49:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
11:29:50:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 69
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: ________________________________________________________________________XXXXXXXX
Uplink 3: ________________________________________________________________________XXXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: _______________________________________________________________________XXXXXXXX_
Uplink 11: _______________________________________________________________________XXXXXXXX_
Uplink 12: ________________________________________________________________________XXXXXXX_
Uplink 13: ________________________________________________________________________XXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 1:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 2:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 3:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 4:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
Uplink 5:
Optimal Phase: 23
Window Length: 36
Eye Window: __XXXX__________________________________
Uplink 6:
Optimal Phase: 22
Window Length: 35
Eye Window: XXXXX___________________________________
Uplink 7:
Optimal Phase: 18
Window Length: 34
Eye Window: XX__________________________________XXXX
Uplink 8:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 9:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 10:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 11:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 12:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 13:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 14:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 15:
Optimal Phase: 12
Window Length: 33
Eye Window: _____________________________XXXXXXX____
11:29:50:setup_element:INFO: Performing Elink synchronization
11:29:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:50:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:29:50:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:29:50:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:29:50:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
11:29:50:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:29:51:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 1 | 0 | [1] | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
11:29:51:febtest:INFO: Init all SMX (CSA): 30
11:30:06:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:30:06:febtest:INFO: 01-00 | XA-000-08-002-002-008-144-06 | 28.2 | 1141.9
11:30:06:febtest:INFO: 08-01 | XA-000-08-002-002-008-159-06 | 31.4 | 1135.9
11:30:07:febtest:INFO: 03-02 | XA-000-08-002-002-008-133-01 | 34.6 | 1124.0
11:30:07:febtest:INFO: 10-03 | XA-000-08-002-002-008-160-15 | 37.7 | 1112.1
11:30:07:febtest:INFO: 05-04 | XA-000-08-002-002-008-134-01 | 21.9 | 1171.5
11:30:07:febtest:INFO: 12-05 | XA-000-08-002-002-008-155-06 | 28.2 | 1147.8
11:30:08:febtest:INFO: 07-06 | XA-000-08-002-002-008-135-01 | 18.7 | 1189.2
11:30:08:febtest:INFO: 14-07 | XA-000-08-002-000-007-049-15 | 3.0 | 1230.3
11:30:09:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
11:30:11:ST3_smx:INFO: chip: 1-0 28.225000 C 1153.732915 mV
11:30:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:11:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:11:ST3_smx:INFO: Electrons
11:30:11:ST3_smx:INFO: # loops 0
11:30:13:ST3_smx:INFO: # loops 1
11:30:14:ST3_smx:INFO: # loops 2
11:30:16:ST3_smx:INFO: # loops 3
11:30:18:ST3_smx:INFO: # loops 4
11:30:19:ST3_smx:INFO: Total # of broken channels: 0
11:30:19:ST3_smx:INFO: List of broken channels: []
11:30:19:ST3_smx:INFO: Total # of broken channels: 0
11:30:19:ST3_smx:INFO: List of broken channels: []
11:30:21:ST3_smx:INFO: chip: 8-1 31.389742 C 1147.806000 mV
11:30:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:21:ST3_smx:INFO: Electrons
11:30:21:ST3_smx:INFO: # loops 0
11:30:23:ST3_smx:INFO: # loops 1
11:30:25:ST3_smx:INFO: # loops 2
11:30:27:ST3_smx:INFO: # loops 3
11:30:28:ST3_smx:INFO: # loops 4
11:30:30:ST3_smx:INFO: Total # of broken channels: 0
11:30:30:ST3_smx:INFO: List of broken channels: []
11:30:30:ST3_smx:INFO: Total # of broken channels: 0
11:30:30:ST3_smx:INFO: List of broken channels: []
11:30:32:ST3_smx:INFO: chip: 3-2 34.556970 C 1135.937260 mV
11:30:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:32:ST3_smx:INFO: Electrons
11:30:32:ST3_smx:INFO: # loops 0
11:30:34:ST3_smx:INFO: # loops 1
11:30:36:ST3_smx:INFO: # loops 2
11:30:38:ST3_smx:INFO: # loops 3
11:30:40:ST3_smx:INFO: # loops 4
11:30:42:ST3_smx:INFO: Total # of broken channels: 0
11:30:42:ST3_smx:INFO: List of broken channels: []
11:30:42:ST3_smx:INFO: Total # of broken channels: 0
11:30:42:ST3_smx:INFO: List of broken channels: []
11:30:44:ST3_smx:INFO: chip: 10-3 40.898880 C 1124.048640 mV
11:30:44:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:44:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:44:ST3_smx:INFO: Electrons
11:30:44:ST3_smx:INFO: # loops 0
11:30:45:ST3_smx:INFO: # loops 1
11:30:47:ST3_smx:INFO: # loops 2
11:30:48:ST3_smx:INFO: # loops 3
11:30:50:ST3_smx:INFO: # loops 4
11:30:52:ST3_smx:INFO: Total # of broken channels: 0
11:30:52:ST3_smx:INFO: List of broken channels: []
11:30:52:ST3_smx:INFO: Total # of broken channels: 0
11:30:52:ST3_smx:INFO: List of broken channels: []
11:30:53:ST3_smx:INFO: chip: 5-4 25.062742 C 1177.390875 mV
11:30:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:30:53:ST3_smx:INFO: Electrons
11:30:53:ST3_smx:INFO: # loops 0
11:30:55:ST3_smx:INFO: # loops 1
11:30:57:ST3_smx:INFO: # loops 2
11:30:58:ST3_smx:INFO: # loops 3
11:31:00:ST3_smx:INFO: # loops 4
11:31:01:ST3_smx:INFO: Total # of broken channels: 0
11:31:01:ST3_smx:INFO: List of broken channels: []
11:31:01:ST3_smx:INFO: Total # of broken channels: 0
11:31:01:ST3_smx:INFO: List of broken channels: []
11:31:03:ST3_smx:INFO: chip: 12-5 28.225000 C 1159.654860 mV
11:31:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:03:ST3_smx:INFO: Electrons
11:31:03:ST3_smx:INFO: # loops 0
11:31:05:ST3_smx:INFO: # loops 1
11:31:06:ST3_smx:INFO: # loops 2
11:31:08:ST3_smx:INFO: # loops 3
11:31:09:ST3_smx:INFO: # loops 4
11:31:11:ST3_smx:INFO: Total # of broken channels: 0
11:31:11:ST3_smx:INFO: List of broken channels: []
11:31:11:ST3_smx:INFO: Total # of broken channels: 0
11:31:11:ST3_smx:INFO: List of broken channels: []
11:31:13:ST3_smx:INFO: chip: 7-6 21.902970 C 1200.969315 mV
11:31:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:13:ST3_smx:INFO: Electrons
11:31:13:ST3_smx:INFO: # loops 0
11:31:15:ST3_smx:INFO: # loops 1
11:31:16:ST3_smx:INFO: # loops 2
11:31:18:ST3_smx:INFO: # loops 3
11:31:19:ST3_smx:INFO: # loops 4
11:31:21:ST3_smx:INFO: Total # of broken channels: 0
11:31:21:ST3_smx:INFO: List of broken channels: []
11:31:21:ST3_smx:INFO: Total # of broken channels: 0
11:31:21:ST3_smx:INFO: List of broken channels: []
11:31:23:ST3_smx:INFO: chip: 14-7 6.141382 C 1236.187875 mV
11:31:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:31:23:ST3_smx:INFO: Electrons
11:31:23:ST3_smx:INFO: # loops 0
11:31:24:ST3_smx:INFO: # loops 1
11:31:26:ST3_smx:INFO: # loops 2
11:31:27:ST3_smx:INFO: # loops 3
11:31:29:ST3_smx:INFO: # loops 4
11:31:30:ST3_smx:INFO: Total # of broken channels: 0
11:31:30:ST3_smx:INFO: List of broken channels: []
11:31:30:ST3_smx:INFO: Total # of broken channels: 0
11:31:30:ST3_smx:INFO: List of broken channels: []
11:31:31:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:31:31:febtest:INFO: 01-00 | XA-000-08-002-002-008-144-06 | 31.4 | 1171.5
11:31:31:febtest:INFO: 08-01 | XA-000-08-002-002-008-159-06 | 31.4 | 1165.6
11:31:31:febtest:INFO: 03-02 | XA-000-08-002-002-008-133-01 | 34.6 | 1159.7
11:31:32:febtest:INFO: 10-03 | XA-000-08-002-002-008-160-15 | 40.9 | 1141.9
11:31:32:febtest:INFO: 05-04 | XA-000-08-002-002-008-134-01 | 25.1 | 1201.0
11:31:32:febtest:INFO: 12-05 | XA-000-08-002-002-008-155-06 | 31.4 | 1177.4
11:31:32:febtest:INFO: 07-06 | XA-000-08-002-002-008-135-01 | 21.9 | 1218.6
11:31:33:febtest:INFO: 14-07 | XA-000-08-002-000-007-049-15 | 9.3 | 1259.6
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_03-11_29_18
OPERATOR : Olga B.; Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1174| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_ID: 26124
MODULE_NAME: L7DL300122 M7DL3T3001223A2 124 C
MODULE_TYPE:
MODULE_LADDER:
MODULE_MODULE:
MODULE_SIZE: 0
MODULE_GRADE:
------------------------------------------------------------
VI_before_Init : ['2.450', '2.0360', '1.850', '2.6040', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0680', '1.850', '2.5050', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9940', '1.850', '0.5233', '0.000', '0.0000', '0.000', '0.0000']