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FEB_1186 28.05.24 13:41:47
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13:41:47:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:41:47:ST3_Shared:INFO: FEB-Microcable
13:41:47:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:41:47:febtest:INFO: Testing FEB with SN 1186
13:41:49:smx_tester:INFO: Scanning setup
13:41:49:elinks:INFO: Disabling clock on downlink 0
13:41:49:elinks:INFO: Disabling clock on downlink 1
13:41:49:elinks:INFO: Disabling clock on downlink 2
13:41:49:elinks:INFO: Disabling clock on downlink 3
13:41:49:elinks:INFO: Disabling clock on downlink 4
13:41:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:41:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:41:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:41:49:elinks:INFO: Disabling clock on downlink 0
13:41:49:elinks:INFO: Disabling clock on downlink 1
13:41:49:elinks:INFO: Disabling clock on downlink 2
13:41:49:elinks:INFO: Disabling clock on downlink 3
13:41:49:elinks:INFO: Disabling clock on downlink 4
13:41:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:41:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
13:41:49:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
13:41:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:41:49:elinks:INFO: Disabling clock on downlink 0
13:41:49:elinks:INFO: Disabling clock on downlink 1
13:41:49:elinks:INFO: Disabling clock on downlink 2
13:41:49:elinks:INFO: Disabling clock on downlink 3
13:41:49:elinks:INFO: Disabling clock on downlink 4
13:41:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:41:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:41:49:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:41:49:elinks:INFO: Disabling clock on downlink 0
13:41:49:elinks:INFO: Disabling clock on downlink 1
13:41:49:elinks:INFO: Disabling clock on downlink 2
13:41:49:elinks:INFO: Disabling clock on downlink 3
13:41:49:elinks:INFO: Disabling clock on downlink 4
13:41:49:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:41:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:41:50:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:41:50:elinks:INFO: Disabling clock on downlink 0
13:41:50:elinks:INFO: Disabling clock on downlink 1
13:41:50:elinks:INFO: Disabling clock on downlink 2
13:41:50:elinks:INFO: Disabling clock on downlink 3
13:41:50:elinks:INFO: Disabling clock on downlink 4
13:41:50:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:41:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:41:50:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:41:50:setup_element:INFO: Scanning clock phase
13:41:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:41:50:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:41:50:setup_element:INFO: Clock phase scan results for group 0, downlink 1
13:41:50:setup_element:INFO: Eye window for uplink 8 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:41:50:setup_element:INFO: Eye window for uplink 9 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
13:41:50:setup_element:INFO: Eye window for uplink 10: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:41:50:setup_element:INFO: Eye window for uplink 11: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:41:50:setup_element:INFO: Eye window for uplink 12: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:41:50:setup_element:INFO: Eye window for uplink 13: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:41:50:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:41:50:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:41:50:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 1
13:41:50:setup_element:INFO: Scanning data phases
13:41:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:41:50:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:41:55:setup_element:INFO: Data phase scan results for group 0, downlink 1
13:41:55:setup_element:INFO: Eye window for uplink 8 : ______________________________XXXXX_____
Data delay found: 12
13:41:55:setup_element:INFO: Eye window for uplink 9 : X__________________________________XXXXX
Data delay found: 17
13:41:55:setup_element:INFO: Eye window for uplink 10: ______________________________XXXXXX____
Data delay found: 12
13:41:55:setup_element:INFO: Eye window for uplink 11: X__________________________________XXXXX
Data delay found: 17
13:41:55:setup_element:INFO: Eye window for uplink 12: _______________________________XXXXX____
Data delay found: 13
13:41:55:setup_element:INFO: Eye window for uplink 13: X__________________________________XXXX_
Data delay found: 17
13:41:55:setup_element:INFO: Eye window for uplink 14: ________________________________XXXX____
Data delay found: 13
13:41:55:setup_element:INFO: Eye window for uplink 15: _________________________________XXXXX__
Data delay found: 15
13:41:55:setup_element:INFO: Setting the data phase to 12 for uplink 8
13:41:55:setup_element:INFO: Setting the data phase to 17 for uplink 9
13:41:55:setup_element:INFO: Setting the data phase to 12 for uplink 10
13:41:55:setup_element:INFO: Setting the data phase to 17 for uplink 11
13:41:55:setup_element:INFO: Setting the data phase to 13 for uplink 12
13:41:55:setup_element:INFO: Setting the data phase to 17 for uplink 13
13:41:55:setup_element:INFO: Setting the data phase to 13 for uplink 14
13:41:55:setup_element:INFO: Setting the data phase to 15 for uplink 15
13:41:55:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 1
Uplinks: [8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 70
Eye Windows:
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: ____________________________________________________________________XXXXXXXXX___
Uplink 11: ____________________________________________________________________XXXXXXXXX___
Uplink 12: _____________________________________________________________________XXXXXXXX___
Uplink 13: _____________________________________________________________________XXXXXXXX___
Uplink 14: ______________________________________________________________________XXXXXXX___
Uplink 15: ______________________________________________________________________XXXXXXX___
Data phase characteristics:
Uplink 8:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 9:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 10:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 11:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 12:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 13:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 14:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 15:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
]
13:41:55:setup_element:INFO: Beginning SMX ASICs map scan
13:41:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:41:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:41:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:41:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:41:55:uplink:INFO: Setting uplinks mask [8, 9, 10, 11, 12, 13, 14, 15]
13:41:55:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
13:41:55:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
13:41:56:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
13:41:56:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
13:41:56:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
13:41:56:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
13:41:57:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
13:41:57:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
13:41:58:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 70
Eye Windows:
Uplink 8: ______________________________________________________________________XXXXXXXX__
Uplink 9: ______________________________________________________________________XXXXXXXX__
Uplink 10: ____________________________________________________________________XXXXXXXXX___
Uplink 11: ____________________________________________________________________XXXXXXXXX___
Uplink 12: _____________________________________________________________________XXXXXXXX___
Uplink 13: _____________________________________________________________________XXXXXXXX___
Uplink 14: ______________________________________________________________________XXXXXXX___
Uplink 15: ______________________________________________________________________XXXXXXX___
Data phase characteristics:
Uplink 8:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 9:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 10:
Optimal Phase: 12
Window Length: 34
Eye Window: ______________________________XXXXXX____
Uplink 11:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 12:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 13:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXX_
Uplink 14:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 15:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
13:41:58:setup_element:INFO: Performing Elink synchronization
13:41:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:41:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:41:58:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
13:41:58:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
13:41:58:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
13:41:58:uplink:INFO: Enabling uplinks [8, 9, 10, 11, 12, 13, 14, 15]
13:41:58:ST3_emu:INFO: Number of chips: 4
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 1 | 0 | [8] | [(0, 8), (1, 9)]
3 | [0] | 1 | 0 | [10] | [(0, 10), (1, 11)]
5 | [0] | 1 | 0 | [12] | [(0, 12), (1, 13)]
7 | [0] | 1 | 0 | [14] | [(0, 14), (1, 15)]
13:41:58:febtest:INFO: Init all SMX (CSA): 30
13:42:06:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:42:06:febtest:INFO: 08-01 | XA-000-08-002-002-006-080-00 | 34.6 | 1159.7
13:42:06:febtest:INFO: 10-03 | XA-000-08-002-002-006-113-14 | 37.7 | 1153.7
13:42:06:febtest:INFO: 12-05 | XA-000-08-002-002-006-110-09 | 25.1 | 1201.0
13:42:06:febtest:INFO: 14-07 | XA-000-08-002-002-006-106-09 | 31.4 | 1177.4
13:42:07:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
13:42:09:ST3_smx:INFO: chip: 8-1 34.556970 C 1171.483840 mV
13:42:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:10:ST3_smx:INFO: Electrons
13:42:10:ST3_smx:INFO: # loops 0
13:42:11:ST3_smx:INFO: # loops 1
13:42:13:ST3_smx:INFO: # loops 2
13:42:14:ST3_smx:INFO: Total # of broken channels: 0
13:42:14:ST3_smx:INFO: List of broken channels: []
13:42:14:ST3_smx:INFO: Total # of broken channels: 0
13:42:14:ST3_smx:INFO: List of broken channels: []
13:42:16:ST3_smx:INFO: chip: 10-3 37.726682 C 1165.571835 mV
13:42:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:16:ST3_smx:INFO: Electrons
13:42:16:ST3_smx:INFO: # loops 0
13:42:18:ST3_smx:INFO: # loops 1
13:42:19:ST3_smx:INFO: # loops 2
13:42:21:ST3_smx:INFO: Total # of broken channels: 0
13:42:21:ST3_smx:INFO: List of broken channels: []
13:42:21:ST3_smx:INFO: Total # of broken channels: 0
13:42:21:ST3_smx:INFO: List of broken channels: []
13:42:22:ST3_smx:INFO: chip: 12-5 25.062742 C 1206.851500 mV
13:42:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:22:ST3_smx:INFO: Electrons
13:42:22:ST3_smx:INFO: # loops 0
13:42:24:ST3_smx:INFO: # loops 1
13:42:25:ST3_smx:INFO: # loops 2
13:42:27:ST3_smx:INFO: Total # of broken channels: 0
13:42:27:ST3_smx:INFO: List of broken channels: []
13:42:27:ST3_smx:INFO: Total # of broken channels: 0
13:42:27:ST3_smx:INFO: List of broken channels: []
13:42:29:ST3_smx:INFO: chip: 14-7 31.389742 C 1183.292940 mV
13:42:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:42:29:ST3_smx:INFO: Electrons
13:42:29:ST3_smx:INFO: # loops 0
13:42:30:ST3_smx:INFO: # loops 1
13:42:32:ST3_smx:INFO: # loops 2
13:42:33:ST3_smx:INFO: Total # of broken channels: 0
13:42:33:ST3_smx:INFO: List of broken channels: []
13:42:33:ST3_smx:INFO: Total # of broken channels: 0
13:42:33:ST3_smx:INFO: List of broken channels: []
13:42:34:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:42:34:febtest:INFO: 08-01 | XA-000-08-002-002-006-080-00 | 34.6 | 1189.2
13:42:34:febtest:INFO: 10-03 | XA-000-08-002-002-006-113-14 | 37.7 | 1189.2
13:42:34:febtest:INFO: 12-05 | XA-000-08-002-002-006-110-09 | 25.1 | 1230.3
13:42:35:febtest:INFO: 14-07 | XA-000-08-002-002-006-106-09 | 31.4 | 1206.9
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_05_28-13_41_47
OPERATOR : Oleksandr S.; Robert V.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1186| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.451', '0.7467', '1.850', '0.9227', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '0.9811', '1.850', '1.0160', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '0.9944', '1.850', '0.2658', '0.000', '0.0000', '0.000', '0.0000']