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FEB_1211 05.12.24 11:43:19
Info
11:43:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:43:19:ST3_Shared:INFO: FEB-Sensor
11:43:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:43:31:ST3_Shared:INFO: STS mode selected
11:43:34:ST3_ModuleSelector:DEBUG: M3DR4B2000132A2
11:43:34:ST3_ModuleSelector:DEBUG: L3DR400013
11:43:34:ST3_ModuleSelector:DEBUG: 22373
11:43:34:ST3_ModuleSelector:DEBUG: 62x62
11:43:34:ST3_ModuleSelector:DEBUG: A
11:43:34:ST3_ModuleSelector:DEBUG: M3DR4B2000132A2
11:43:34:ST3_ModuleSelector:DEBUG: L3DR400013
11:43:34:ST3_ModuleSelector:DEBUG: 22373
11:43:34:ST3_ModuleSelector:DEBUG: 62x62
11:43:34:ST3_ModuleSelector:DEBUG: A
11:43:43:ST3_ModuleSelector:INFO: M3DR4B2000132A2
11:43:43:ST3_ModuleSelector:INFO: 22373
11:43:44:febtest:INFO: Testing FEB with SN 1211
11:43:45:smx_tester:INFO: Scanning setup
11:43:45:elinks:INFO: Disabling clock on downlink 0
11:43:45:elinks:INFO: Disabling clock on downlink 1
11:43:45:elinks:INFO: Disabling clock on downlink 2
11:43:45:elinks:INFO: Disabling clock on downlink 3
11:43:45:elinks:INFO: Disabling clock on downlink 4
11:43:45:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:43:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:43:45:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:43:45:elinks:INFO: Disabling clock on downlink 0
11:43:45:elinks:INFO: Disabling clock on downlink 1
11:43:45:elinks:INFO: Disabling clock on downlink 2
11:43:45:elinks:INFO: Disabling clock on downlink 3
11:43:45:elinks:INFO: Disabling clock on downlink 4
11:43:45:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:43:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
11:43:45:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
11:43:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
11:43:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
11:43:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
11:43:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
11:43:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
11:43:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:43:46:elinks:INFO: Disabling clock on downlink 0
11:43:46:elinks:INFO: Disabling clock on downlink 1
11:43:46:elinks:INFO: Disabling clock on downlink 2
11:43:46:elinks:INFO: Disabling clock on downlink 3
11:43:46:elinks:INFO: Disabling clock on downlink 4
11:43:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:43:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:43:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:43:46:elinks:INFO: Disabling clock on downlink 0
11:43:46:elinks:INFO: Disabling clock on downlink 1
11:43:46:elinks:INFO: Disabling clock on downlink 2
11:43:46:elinks:INFO: Disabling clock on downlink 3
11:43:46:elinks:INFO: Disabling clock on downlink 4
11:43:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:43:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:43:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:43:46:elinks:INFO: Disabling clock on downlink 0
11:43:46:elinks:INFO: Disabling clock on downlink 1
11:43:46:elinks:INFO: Disabling clock on downlink 2
11:43:46:elinks:INFO: Disabling clock on downlink 3
11:43:46:elinks:INFO: Disabling clock on downlink 4
11:43:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:43:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:43:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:43:46:setup_element:INFO: Scanning clock phase
11:43:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:43:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:43:46:setup_element:INFO: Clock phase scan results for group 0, downlink 1
11:43:46:setup_element:INFO: Eye window for uplink 0 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 1 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:43:46:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
11:43:46:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:43:46:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
11:43:46:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 14: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:43:46:setup_element:INFO: Eye window for uplink 15: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
11:43:46:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
11:43:46:setup_element:INFO: Scanning data phases
11:43:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:43:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:43:52:setup_element:INFO: Data phase scan results for group 0, downlink 1
11:43:52:setup_element:INFO: Eye window for uplink 0 : ____________XXXXXXX_____________________
Data delay found: 35
11:43:52:setup_element:INFO: Eye window for uplink 1 : ________XXXXXXX_________________________
Data delay found: 31
11:43:52:setup_element:INFO: Eye window for uplink 2 : _____XXXXXXX____________________________
Data delay found: 28
11:43:52:setup_element:INFO: Eye window for uplink 3 : __XXXXXXXX______________________________
Data delay found: 25
11:43:52:setup_element:INFO: Eye window for uplink 4 : _______XXXXX____________________________
Data delay found: 29
11:43:52:setup_element:INFO: Eye window for uplink 5 : __XXXXXXX_______________________________
Data delay found: 25
11:43:52:setup_element:INFO: Eye window for uplink 6 : XXXX_________________________________XXX
Data delay found: 20
11:43:52:setup_element:INFO: Eye window for uplink 7 : X________________________________XXXXXX_
Data delay found: 16
11:43:52:setup_element:INFO: Eye window for uplink 8 : _________________________XXXXX__________
Data delay found: 7
11:43:52:setup_element:INFO: Eye window for uplink 9 : _____________________________XXXXXXX____
Data delay found: 12
11:43:52:setup_element:INFO: Eye window for uplink 10: ___________________________XXXXXXXX_____
Data delay found: 10
11:43:52:setup_element:INFO: Eye window for uplink 11: _______________________________XXXXXXX__
Data delay found: 14
11:43:52:setup_element:INFO: Eye window for uplink 12: ___________________________XXXXXXXX_____
Data delay found: 10
11:43:52:setup_element:INFO: Eye window for uplink 13: ____________________________XXXXXXXXXX__
Data delay found: 12
11:43:52:setup_element:INFO: Eye window for uplink 14: _________________________XXXXXXXXXXX____
Data delay found: 10
11:43:52:setup_element:INFO: Eye window for uplink 15: ___________________________XXXXXXXXXXX__
Data delay found: 12
11:43:52:setup_element:INFO: Setting the data phase to 35 for uplink 0
11:43:52:setup_element:INFO: Setting the data phase to 31 for uplink 1
11:43:52:setup_element:INFO: Setting the data phase to 28 for uplink 2
11:43:52:setup_element:INFO: Setting the data phase to 25 for uplink 3
11:43:52:setup_element:INFO: Setting the data phase to 29 for uplink 4
11:43:52:setup_element:INFO: Setting the data phase to 25 for uplink 5
11:43:52:setup_element:INFO: Setting the data phase to 20 for uplink 6
11:43:52:setup_element:INFO: Setting the data phase to 16 for uplink 7
11:43:52:setup_element:INFO: Setting the data phase to 7 for uplink 8
11:43:52:setup_element:INFO: Setting the data phase to 12 for uplink 9
11:43:52:setup_element:INFO: Setting the data phase to 10 for uplink 10
11:43:52:setup_element:INFO: Setting the data phase to 14 for uplink 11
11:43:52:setup_element:INFO: Setting the data phase to 10 for uplink 12
11:43:52:setup_element:INFO: Setting the data phase to 12 for uplink 13
11:43:52:setup_element:INFO: Setting the data phase to 10 for uplink 14
11:43:52:setup_element:INFO: Setting the data phase to 12 for uplink 15
==============================================OOO==============================================
11:43:52:setup_element:INFO: Beginning SMX ASICs map scan
11:43:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:43:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:43:52:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:43:52:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
11:43:52:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
11:43:52:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
11:43:52:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
11:43:52:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
11:43:52:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
11:43:52:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
11:43:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
11:43:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
11:43:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
11:43:53:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
11:43:53:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
11:43:53:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
11:43:53:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
11:43:53:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
11:43:53:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
11:43:53:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
11:43:53:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
11:43:55:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 70
Eye Windows:
Uplink 0: _______________________________________________________________________XXXXXXX__
Uplink 1: _______________________________________________________________________XXXXXXX__
Uplink 2: _______________________________________________________________________XXXXXXX__
Uplink 3: _______________________________________________________________________XXXXXXX__
Uplink 4: _______________________________________________________________________XXXXXXX__
Uplink 5: _______________________________________________________________________XXXXXXX__
Uplink 6: _______________________________________________________________________XXXXXXX__
Uplink 7: _______________________________________________________________________XXXXXXX__
Uplink 8: _____________________________________________________________________XXXXXXXXX__
Uplink 9: _____________________________________________________________________XXXXXXXXX__
Uplink 10: ______________________________________________________________________XXXXXXXX__
Uplink 11: ______________________________________________________________________XXXXXXXX__
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _______________________________________________________________________XXXXXXXX_
Uplink 15: _______________________________________________________________________XXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 35
Window Length: 33
Eye Window: ____________XXXXXXX_____________________
Uplink 1:
Optimal Phase: 31
Window Length: 33
Eye Window: ________XXXXXXX_________________________
Uplink 2:
Optimal Phase: 28
Window Length: 33
Eye Window: _____XXXXXXX____________________________
Uplink 3:
Optimal Phase: 25
Window Length: 32
Eye Window: __XXXXXXXX______________________________
Uplink 4:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 5:
Optimal Phase: 25
Window Length: 33
Eye Window: __XXXXXXX_______________________________
Uplink 6:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 7:
Optimal Phase: 16
Window Length: 32
Eye Window: X________________________________XXXXXX_
Uplink 8:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 9:
Optimal Phase: 12
Window Length: 33
Eye Window: _____________________________XXXXXXX____
Uplink 10:
Optimal Phase: 10
Window Length: 32
Eye Window: ___________________________XXXXXXXX_____
Uplink 11:
Optimal Phase: 14
Window Length: 33
Eye Window: _______________________________XXXXXXX__
Uplink 12:
Optimal Phase: 10
Window Length: 32
Eye Window: ___________________________XXXXXXXX_____
Uplink 13:
Optimal Phase: 12
Window Length: 30
Eye Window: ____________________________XXXXXXXXXX__
Uplink 14:
Optimal Phase: 10
Window Length: 29
Eye Window: _________________________XXXXXXXXXXX____
Uplink 15:
Optimal Phase: 12
Window Length: 29
Eye Window: ___________________________XXXXXXXXXXX__
==============================================OOO==============================================
11:43:55:setup_element:INFO: Performing Elink synchronization
11:43:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:43:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
11:43:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
11:43:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
11:43:55:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
11:43:55:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
11:43:56:febtest:INFO: Init all SMX (CSA): 30
11:44:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:44:10:febtest:INFO: 01-00 | XA-000-09-004-007-013-011-09 | 40.9 | 1147.8
11:44:11:febtest:INFO: 08-01 | XA-000-09-004-007-014-013-07 | 44.1 | 1130.0
11:44:11:febtest:INFO: 03-02 | XA-000-09-004-007-014-009-07 | 44.1 | 1130.0
11:44:11:febtest:INFO: 10-03 | XA-000-09-004-007-015-010-10 | 40.9 | 1135.9
11:44:11:febtest:INFO: 05-04 | XA-000-09-004-007-015-013-10 | 28.2 | 1183.3
11:44:11:febtest:INFO: 12-05 | XA-000-09-004-007-014-011-07 | 34.6 | 1153.7
11:44:12:febtest:INFO: 07-06 | XA-000-09-004-007-015-012-10 | 28.2 | 1189.2
11:44:12:febtest:INFO: 14-07 | XA-000-09-004-007-013-013-09 | 28.2 | 1183.3
11:44:13:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
11:44:15:ST3_smx:INFO: chip: 1-0 40.898880 C 1159.654860 mV
11:44:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:15:ST3_smx:INFO: Electrons
11:44:15:ST3_smx:INFO: # loops 0
11:44:17:ST3_smx:INFO: # loops 1
11:44:18:ST3_smx:INFO: # loops 2
11:44:20:ST3_smx:INFO: # loops 3
11:44:22:ST3_smx:INFO: # loops 4
11:44:23:ST3_smx:INFO: Total # of broken channels: 0
11:44:23:ST3_smx:INFO: List of broken channels: []
11:44:23:ST3_smx:INFO: Total # of broken channels: 0
11:44:23:ST3_smx:INFO: List of broken channels: []
11:44:25:ST3_smx:INFO: chip: 8-1 44.073563 C 1141.874115 mV
11:44:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:25:ST3_smx:INFO: Electrons
11:44:25:ST3_smx:INFO: # loops 0
11:44:27:ST3_smx:INFO: # loops 1
11:44:28:ST3_smx:INFO: # loops 2
11:44:30:ST3_smx:INFO: # loops 3
11:44:32:ST3_smx:INFO: # loops 4
11:44:33:ST3_smx:INFO: Total # of broken channels: 0
11:44:33:ST3_smx:INFO: List of broken channels: []
11:44:33:ST3_smx:INFO: Total # of broken channels: 0
11:44:33:ST3_smx:INFO: List of broken channels: []
11:44:35:ST3_smx:INFO: chip: 3-2 47.250730 C 1141.874115 mV
11:44:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:35:ST3_smx:INFO: Electrons
11:44:35:ST3_smx:INFO: # loops 0
11:44:37:ST3_smx:INFO: # loops 1
11:44:38:ST3_smx:INFO: # loops 2
11:44:40:ST3_smx:INFO: # loops 3
11:44:42:ST3_smx:INFO: # loops 4
11:44:43:ST3_smx:INFO: Total # of broken channels: 0
11:44:43:ST3_smx:INFO: List of broken channels: []
11:44:43:ST3_smx:INFO: Total # of broken channels: 0
11:44:43:ST3_smx:INFO: List of broken channels: []
11:44:45:ST3_smx:INFO: chip: 10-3 40.898880 C 1147.806000 mV
11:44:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:45:ST3_smx:INFO: Electrons
11:44:45:ST3_smx:INFO: # loops 0
11:44:47:ST3_smx:INFO: # loops 1
11:44:49:ST3_smx:INFO: # loops 2
11:44:50:ST3_smx:INFO: # loops 3
11:44:52:ST3_smx:INFO: # loops 4
11:44:53:ST3_smx:INFO: Total # of broken channels: 0
11:44:53:ST3_smx:INFO: List of broken channels: []
11:44:53:ST3_smx:INFO: Total # of broken channels: 0
11:44:54:ST3_smx:INFO: List of broken channels: []
11:44:55:ST3_smx:INFO: chip: 5-4 31.389742 C 1189.190035 mV
11:44:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:44:55:ST3_smx:INFO: Electrons
11:44:55:ST3_smx:INFO: # loops 0
11:44:57:ST3_smx:INFO: # loops 1
11:44:58:ST3_smx:INFO: # loops 2
11:45:00:ST3_smx:INFO: # loops 3
11:45:02:ST3_smx:INFO: # loops 4
11:45:04:ST3_smx:INFO: Total # of broken channels: 0
11:45:04:ST3_smx:INFO: List of broken channels: []
11:45:04:ST3_smx:INFO: Total # of broken channels: 0
11:45:04:ST3_smx:INFO: List of broken channels: []
11:45:05:ST3_smx:INFO: chip: 12-5 34.556970 C 1165.571835 mV
11:45:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:45:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:45:05:ST3_smx:INFO: Electrons
11:45:05:ST3_smx:INFO: # loops 0
11:45:07:ST3_smx:INFO: # loops 1
11:45:09:ST3_smx:INFO: # loops 2
11:45:10:ST3_smx:INFO: # loops 3
11:45:12:ST3_smx:INFO: # loops 4
11:45:13:ST3_smx:INFO: Total # of broken channels: 0
11:45:13:ST3_smx:INFO: List of broken channels: []
11:45:13:ST3_smx:INFO: Total # of broken channels: 0
11:45:13:ST3_smx:INFO: List of broken channels: []
11:45:15:ST3_smx:INFO: chip: 7-6 28.225000 C 1195.082160 mV
11:45:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:45:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:45:15:ST3_smx:INFO: Electrons
11:45:15:ST3_smx:INFO: # loops 0
11:45:17:ST3_smx:INFO: # loops 1
11:45:18:ST3_smx:INFO: # loops 2
11:45:20:ST3_smx:INFO: # loops 3
11:45:22:ST3_smx:INFO: # loops 4
11:45:23:ST3_smx:INFO: Total # of broken channels: 0
11:45:23:ST3_smx:INFO: List of broken channels: []
11:45:23:ST3_smx:INFO: Total # of broken channels: 0
11:45:23:ST3_smx:INFO: List of broken channels: []
11:45:25:ST3_smx:INFO: chip: 14-7 28.225000 C 1189.190035 mV
11:45:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:45:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
11:45:25:ST3_smx:INFO: Electrons
11:45:25:ST3_smx:INFO: # loops 0
11:45:27:ST3_smx:INFO: # loops 1
11:45:28:ST3_smx:INFO: # loops 2
11:45:30:ST3_smx:INFO: # loops 3
11:45:31:ST3_smx:INFO: # loops 4
11:45:33:ST3_smx:INFO: Total # of broken channels: 0
11:45:33:ST3_smx:INFO: List of broken channels: []
11:45:33:ST3_smx:INFO: Total # of broken channels: 0
11:45:33:ST3_smx:INFO: List of broken channels: []
11:45:33:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:45:34:febtest:INFO: 01-00 | XA-000-09-004-007-013-011-09 | 40.9 | 1177.4
11:45:34:febtest:INFO: 08-01 | XA-000-09-004-007-014-013-07 | 44.1 | 1165.6
11:45:34:febtest:INFO: 03-02 | XA-000-09-004-007-014-009-07 | 47.3 | 1165.6
11:45:34:febtest:INFO: 10-03 | XA-000-09-004-007-015-010-10 | 40.9 | 1171.5
11:45:35:febtest:INFO: 05-04 | XA-000-09-004-007-015-013-10 | 31.4 | 1212.7
11:45:35:febtest:INFO: 12-05 | XA-000-09-004-007-014-011-07 | 37.7 | 1195.1
11:45:35:febtest:INFO: 07-06 | XA-000-09-004-007-015-012-10 | 31.4 | 1218.6
11:45:35:febtest:INFO: 14-07 | XA-000-09-004-007-013-013-09 | 31.4 | 1212.7
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_12_05-11_43_19
OPERATOR : Kerstin S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1211| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 22373 | SIZE: 62x62 | GRADE: A
MODULE_NAME: M3DR4B2000132A2
LADDER_NAME: L3DR400013
------------------------------------------------------------
VI_before_Init : ['2.449', '1.6340', '1.848', '2.2380', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0440', '1.850', '2.4980', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '2.0050', '1.850', '0.5393', '0.000', '0.0000', '0.000', '0.0000']