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LDO/GSI
LDO/KIT

FEB_1235    27.08.24 13:45:01

Ladder: L8UL601024
Module: M8UL6T0010240B2
Sensor: 27072
link: XA-050-08-002-003-007-021-00
SMX_1
...SMX_1.root
link: XA-049-08-002-003-007-021-04
SMX_3
...SMX_3.root
link: XA-000-08-002-003-007-047-09
SMX_5
...SMX_5.root
link: XA-000-08-002-003-007-046-09
SMX_7
...SMX_7.root
link: XA-054-08-002-003-007-021-07
SMX_0
...SMX_0.root
link: XA-053-08-002-003-007-021-03
SMX_2
...SMX_2.root
link: XA-052-08-002-003-007-021-08
SMX_4
...SMX_4.root
link: XA-051-08-002-003-007-021-11
SMX_6
...SMX_6.root
link: XA-051-08-002-003-007-021-11
VddmCSAstatus.png
...VddmCSAstatus.root
TextEdit.txt 
            13:45:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:45:01:ST3_Shared:INFO:	                       FEB-Microcable                       
13:45:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:45:01:febtest:INFO:	Testing FEB with SN 1235
13:45:02:smx_tester:INFO:	Scanning setup
13:45:02:elinks:INFO:	Disabling clock on downlink 0
13:45:02:elinks:INFO:	Disabling clock on downlink 1
13:45:02:elinks:INFO:	Disabling clock on downlink 2
13:45:02:elinks:INFO:	Disabling clock on downlink 3
13:45:02:elinks:INFO:	Disabling clock on downlink 4
13:45:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:45:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:45:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:45:03:elinks:INFO:	Disabling clock on downlink 0
13:45:03:elinks:INFO:	Disabling clock on downlink 1
13:45:03:elinks:INFO:	Disabling clock on downlink 2
13:45:03:elinks:INFO:	Disabling clock on downlink 3
13:45:03:elinks:INFO:	Disabling clock on downlink 4
13:45:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:45:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
13:45:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
13:45:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:45:03:elinks:INFO:	Disabling clock on downlink 0
13:45:03:elinks:INFO:	Disabling clock on downlink 1
13:45:03:elinks:INFO:	Disabling clock on downlink 2
13:45:03:elinks:INFO:	Disabling clock on downlink 3
13:45:03:elinks:INFO:	Disabling clock on downlink 4
13:45:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:45:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:45:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:45:03:elinks:INFO:	Disabling clock on downlink 0
13:45:03:elinks:INFO:	Disabling clock on downlink 1
13:45:03:elinks:INFO:	Disabling clock on downlink 2
13:45:03:elinks:INFO:	Disabling clock on downlink 3
13:45:03:elinks:INFO:	Disabling clock on downlink 4
13:45:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:45:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:45:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:45:03:elinks:INFO:	Disabling clock on downlink 0
13:45:03:elinks:INFO:	Disabling clock on downlink 1
13:45:03:elinks:INFO:	Disabling clock on downlink 2
13:45:03:elinks:INFO:	Disabling clock on downlink 3
13:45:03:elinks:INFO:	Disabling clock on downlink 4
13:45:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:45:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:45:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:45:03:setup_element:INFO:	Scanning clock phase
13:45:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:45:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:45:03:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
13:45:03:setup_element:INFO:	Eye window for uplink 0 : ______________________________________________________________________XXXXXX____
Clock Delay: 32
13:45:03:setup_element:INFO:	Eye window for uplink 1 : ______________________________________________________________________XXXXXX____
Clock Delay: 32
13:45:03:setup_element:INFO:	Eye window for uplink 2 : ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:45:03:setup_element:INFO:	Eye window for uplink 3 : ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:45:03:setup_element:INFO:	Eye window for uplink 4 : ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:45:03:setup_element:INFO:	Eye window for uplink 5 : ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:45:03:setup_element:INFO:	Eye window for uplink 6 : ______________________________________________________________________XXXXXX____
Clock Delay: 32
13:45:03:setup_element:INFO:	Eye window for uplink 7 : ______________________________________________________________________XXXXXX____
Clock Delay: 32
13:45:03:setup_element:INFO:	Eye window for uplink 8 : _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
13:45:03:setup_element:INFO:	Eye window for uplink 9 : _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
13:45:03:setup_element:INFO:	Eye window for uplink 10: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:45:03:setup_element:INFO:	Eye window for uplink 11: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
13:45:03:setup_element:INFO:	Eye window for uplink 12: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:45:03:setup_element:INFO:	Eye window for uplink 13: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:45:03:setup_element:INFO:	Eye window for uplink 14: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:45:03:setup_element:INFO:	Eye window for uplink 15: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
13:45:03:setup_element:INFO:	Setting the clock phase to 30 for group 0, downlink 1
13:45:03:setup_element:INFO:	Scanning data phases
13:45:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:45:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:45:09:setup_element:INFO:	Data phase scan results for group 0, downlink 1
13:45:09:setup_element:INFO:	Eye window for uplink 0 : ___________XXXXX________________________
Data delay found: 33
13:45:09:setup_element:INFO:	Eye window for uplink 1 : _______XXXXX____________________________
Data delay found: 29
13:45:09:setup_element:INFO:	Eye window for uplink 2 : _____XXXXXX_____________________________
Data delay found: 27
13:45:09:setup_element:INFO:	Eye window for uplink 3 : __XXXXXX________________________________
Data delay found: 24
13:45:09:setup_element:INFO:	Eye window for uplink 4 : __XXXXX_________________________________
Data delay found: 24
13:45:09:setup_element:INFO:	Eye window for uplink 5 : XXX__________________________________XXX
Data delay found: 19
13:45:09:setup_element:INFO:	Eye window for uplink 6 : XXX___________________________________XX
Data delay found: 20
13:45:09:setup_element:INFO:	Eye window for uplink 7 : X_________________________________XXXXX_
Data delay found: 17
13:45:09:setup_element:INFO:	Eye window for uplink 8 : ___________________XXXXXX_______________
Data delay found: 1
13:45:09:setup_element:INFO:	Eye window for uplink 9 : _________________________XXXXX__________
Data delay found: 7
13:45:09:setup_element:INFO:	Eye window for uplink 10: _______________________XXXXXX___________
Data delay found: 5
13:45:09:setup_element:INFO:	Eye window for uplink 11: ___________________________XXXXX________
Data delay found: 9
13:45:09:setup_element:INFO:	Eye window for uplink 12: _____________________________XXXXX______
Data delay found: 11
13:45:09:setup_element:INFO:	Eye window for uplink 13: ________________________________XXXXX___
Data delay found: 14
13:45:09:setup_element:INFO:	Eye window for uplink 14: _____________________________XXXX_______
Data delay found: 10
13:45:09:setup_element:INFO:	Eye window for uplink 15: ________________________________XXX_____
Data delay found: 13
13:45:09:setup_element:INFO:	Setting the data phase to 33 for uplink 0
13:45:09:setup_element:INFO:	Setting the data phase to 29 for uplink 1
13:45:09:setup_element:INFO:	Setting the data phase to 27 for uplink 2
13:45:09:setup_element:INFO:	Setting the data phase to 24 for uplink 3
13:45:09:setup_element:INFO:	Setting the data phase to 24 for uplink 4
13:45:09:setup_element:INFO:	Setting the data phase to 19 for uplink 5
13:45:09:setup_element:INFO:	Setting the data phase to 20 for uplink 6
13:45:09:setup_element:INFO:	Setting the data phase to 17 for uplink 7
13:45:09:setup_element:INFO:	Setting the data phase to 1 for uplink 8
13:45:09:setup_element:INFO:	Setting the data phase to 7 for uplink 9
13:45:09:setup_element:INFO:	Setting the data phase to 5 for uplink 10
13:45:09:setup_element:INFO:	Setting the data phase to 9 for uplink 11
13:45:09:setup_element:INFO:	Setting the data phase to 11 for uplink 12
13:45:09:setup_element:INFO:	Setting the data phase to 14 for uplink 13
13:45:09:setup_element:INFO:	Setting the data phase to 10 for uplink 14
13:45:09:setup_element:INFO:	Setting the data phase to 13 for uplink 15
13:45:09:setup_element:INFO:	Beginning SMX ASICs map scan
13:45:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:45:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:45:09:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
13:45:09:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
13:45:09:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:45:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
13:45:09:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
13:45:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
13:45:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
13:45:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
13:45:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
13:45:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
13:45:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
13:45:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
13:45:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
13:45:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
13:45:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
13:45:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
13:45:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
13:45:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
13:45:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
13:45:12:setup_element:INFO:	Performing Elink synchronization
13:45:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:45:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:45:12:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
13:45:12:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
13:45:12:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
13:45:12:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
13:45:12:ST3_emu_feb:DEBUG:	Chip address:  	0x0
13:45:12:ST3_emu_feb:DEBUG:	Chip address:  	0x1
13:45:12:ST3_emu_feb:DEBUG:	Chip address:  	0x2
13:45:12:ST3_emu_feb:DEBUG:	Chip address:  	0x3
13:45:12:ST3_emu_feb:DEBUG:	Chip address:  	0x4
13:45:13:ST3_emu_feb:DEBUG:	Chip address:  	0x5
13:45:13:ST3_emu_feb:DEBUG:	Chip address:  	0x6
13:45:13:ST3_emu_feb:DEBUG:	Chip address:  	0x7
13:45:13:febtest:INFO:	Init all SMX (CSA): 30
13:45:27:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:45:27:febtest:INFO:	01-00 | XA-054-08-002-003-007-021-07 |  40.9 | 1147.8
13:45:27:febtest:INFO:	08-01 | XA-050-08-002-003-007-021-00 |  60.0 | 1082.3
13:45:28:febtest:INFO:	03-02 | XA-053-08-002-003-007-021-03 |  50.4 | 1130.0
13:45:28:febtest:INFO:	10-03 | XA-049-08-002-003-007-021-04 |  53.6 | 1112.1
13:45:28:febtest:INFO:	05-04 | XA-052-08-002-003-007-021-08 |  53.6 | 1112.1
13:45:28:febtest:INFO:	12-05 | XA-000-08-002-003-007-047-09 |  37.7 | 1147.8
13:45:29:febtest:INFO:	07-06 | XA-051-08-002-003-007-021-11 |  53.6 | 1130.0
13:45:29:febtest:INFO:	14-07 | XA-000-08-002-003-007-046-09 |  34.6 | 1159.7
13:45:30:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
13:45:32:ST3_smx:INFO:	chip: 1-0 	 44.073563 C 	 1153.732915 mV
13:45:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:32:ST3_smx:INFO:		Electrons
13:45:32:ST3_smx:INFO:	# loops 0
13:45:33:ST3_smx:INFO:	# loops 1
13:45:35:ST3_smx:INFO:	# loops 2
13:45:37:ST3_smx:INFO:	Total # of broken channels: 0
13:45:37:ST3_smx:INFO:	List of broken channels: []
13:45:37:ST3_smx:INFO:	Total # of broken channels: 0
13:45:37:ST3_smx:INFO:	List of broken channels: []
13:45:38:ST3_smx:INFO:	chip: 8-1 	 59.984250 C 	 1088.263500 mV
13:45:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:38:ST3_smx:INFO:		Electrons
13:45:38:ST3_smx:INFO:	# loops 0
13:45:40:ST3_smx:INFO:	# loops 1
13:45:42:ST3_smx:INFO:	# loops 2
13:45:43:ST3_smx:INFO:	Total # of broken channels: 0
13:45:43:ST3_smx:INFO:	List of broken channels: []
13:45:43:ST3_smx:INFO:	Total # of broken channels: 0
13:45:43:ST3_smx:INFO:	List of broken channels: []
13:45:45:ST3_smx:INFO:	chip: 3-2 	 50.430383 C 	 1135.937260 mV
13:45:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:45:ST3_smx:INFO:		Electrons
13:45:45:ST3_smx:INFO:	# loops 0
13:45:47:ST3_smx:INFO:	# loops 1
13:45:48:ST3_smx:INFO:	# loops 2
13:45:50:ST3_smx:INFO:	Total # of broken channels: 0
13:45:50:ST3_smx:INFO:	List of broken channels: []
13:45:50:ST3_smx:INFO:	Total # of broken channels: 7
13:45:50:ST3_smx:INFO:	List of broken channels: [13, 15, 19, 21, 27, 34, 62]
13:45:52:ST3_smx:INFO:	chip: 10-3 	 53.612520 C 	 1124.048640 mV
13:45:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:52:ST3_smx:INFO:		Electrons
13:45:52:ST3_smx:INFO:	# loops 0
13:45:53:ST3_smx:INFO:	# loops 1
13:45:55:ST3_smx:INFO:	# loops 2
13:45:57:ST3_smx:INFO:	Total # of broken channels: 0
13:45:57:ST3_smx:INFO:	List of broken channels: []
13:45:57:ST3_smx:INFO:	Total # of broken channels: 0
13:45:57:ST3_smx:INFO:	List of broken channels: []
13:45:58:ST3_smx:INFO:	chip: 5-4 	 53.612520 C 	 1124.048640 mV
13:45:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:45:59:ST3_smx:INFO:		Electrons
13:45:59:ST3_smx:INFO:	# loops 0
13:46:00:ST3_smx:INFO:	# loops 1
13:46:02:ST3_smx:INFO:	# loops 2
13:46:03:ST3_smx:INFO:	Total # of broken channels: 0
13:46:03:ST3_smx:INFO:	List of broken channels: []
13:46:03:ST3_smx:INFO:	Total # of broken channels: 0
13:46:03:ST3_smx:INFO:	List of broken channels: []
13:46:05:ST3_smx:INFO:	chip: 12-5 	 37.726682 C 	 1159.654860 mV
13:46:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:46:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:46:05:ST3_smx:INFO:		Electrons
13:46:05:ST3_smx:INFO:	# loops 0
13:46:07:ST3_smx:INFO:	# loops 1
13:46:08:ST3_smx:INFO:	# loops 2
13:46:10:ST3_smx:INFO:	Total # of broken channels: 0
13:46:10:ST3_smx:INFO:	List of broken channels: []
13:46:10:ST3_smx:INFO:	Total # of broken channels: 0
13:46:10:ST3_smx:INFO:	List of broken channels: []
13:46:12:ST3_smx:INFO:	chip: 7-6 	 53.612520 C 	 1135.937260 mV
13:46:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:46:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:46:12:ST3_smx:INFO:		Electrons
13:46:12:ST3_smx:INFO:	# loops 0
13:46:13:ST3_smx:INFO:	# loops 1
13:46:15:ST3_smx:INFO:	# loops 2
13:46:17:ST3_smx:INFO:	Total # of broken channels: 0
13:46:17:ST3_smx:INFO:	List of broken channels: []
13:46:17:ST3_smx:INFO:	Total # of broken channels: 30
13:46:17:ST3_smx:INFO:	List of broken channels: [22, 24, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 74, 76, 78, 80, 82, 86, 90]
13:46:19:ST3_smx:INFO:	chip: 14-7 	 34.556970 C 	 1171.483840 mV
13:46:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:46:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:46:19:ST3_smx:INFO:		Electrons
13:46:19:ST3_smx:INFO:	# loops 0
13:46:20:ST3_smx:INFO:	# loops 1
13:46:22:ST3_smx:INFO:	# loops 2
13:46:24:ST3_smx:INFO:	Total # of broken channels: 0
13:46:24:ST3_smx:INFO:	List of broken channels: []
13:46:24:ST3_smx:INFO:	Total # of broken channels: 0
13:46:24:ST3_smx:INFO:	List of broken channels: []
13:46:24:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:46:24:febtest:INFO:	01-00 | XA-054-08-002-003-007-021-07 |  44.1 | 1177.4
13:46:24:febtest:INFO:	08-01 | XA-050-08-002-003-007-021-00 |  63.2 | 1112.1
13:46:25:febtest:INFO:	03-02 | XA-053-08-002-003-007-021-03 |  50.4 | 1159.7
13:46:25:febtest:INFO:	10-03 | XA-049-08-002-003-007-021-04 |  56.8 | 1147.8
13:46:25:febtest:INFO:	05-04 | XA-052-08-002-003-007-021-08 |  56.8 | 1141.9
13:46:25:febtest:INFO:	12-05 | XA-000-08-002-003-007-047-09 |  40.9 | 1183.3
13:46:25:febtest:INFO:	07-06 | XA-051-08-002-003-007-021-11 |  56.8 | 1153.7
13:46:26:febtest:INFO:	14-07 | XA-000-08-002-003-007-046-09 |  37.7 | 1189.2
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_08_27-13_45_01
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1235| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.449', '1.5760', '1.848', '2.1200', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0280', '1.850', '2.3010', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9940', '1.850', '0.5230', '0.000', '0.0000', '0.000', '0.0000']
Comment.txt