FEB_1240    23.09.24 13:22:01

TextEdit.txt
            13:22:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:22:01:ST3_Shared:INFO:	                       FEB-Microcable                       
13:22:01:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:22:01:febtest:INFO:	Testing FEB with SN 1240
13:22:02:smx_tester:INFO:	Scanning setup
13:22:02:elinks:INFO:	Disabling clock on downlink 0
13:22:02:elinks:INFO:	Disabling clock on downlink 1
13:22:02:elinks:INFO:	Disabling clock on downlink 2
13:22:02:elinks:INFO:	Disabling clock on downlink 3
13:22:02:elinks:INFO:	Disabling clock on downlink 4
13:22:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:22:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:22:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:22:02:elinks:INFO:	Disabling clock on downlink 0
13:22:02:elinks:INFO:	Disabling clock on downlink 1
13:22:02:elinks:INFO:	Disabling clock on downlink 2
13:22:02:elinks:INFO:	Disabling clock on downlink 3
13:22:02:elinks:INFO:	Disabling clock on downlink 4
13:22:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:22:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
13:22:03:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
13:22:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:22:03:elinks:INFO:	Disabling clock on downlink 0
13:22:03:elinks:INFO:	Disabling clock on downlink 1
13:22:03:elinks:INFO:	Disabling clock on downlink 2
13:22:03:elinks:INFO:	Disabling clock on downlink 3
13:22:03:elinks:INFO:	Disabling clock on downlink 4
13:22:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:22:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:22:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:22:03:elinks:INFO:	Disabling clock on downlink 0
13:22:03:elinks:INFO:	Disabling clock on downlink 1
13:22:03:elinks:INFO:	Disabling clock on downlink 2
13:22:03:elinks:INFO:	Disabling clock on downlink 3
13:22:03:elinks:INFO:	Disabling clock on downlink 4
13:22:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:22:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:22:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:22:03:elinks:INFO:	Disabling clock on downlink 0
13:22:03:elinks:INFO:	Disabling clock on downlink 1
13:22:03:elinks:INFO:	Disabling clock on downlink 2
13:22:03:elinks:INFO:	Disabling clock on downlink 3
13:22:03:elinks:INFO:	Disabling clock on downlink 4
13:22:03:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:22:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:22:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:22:03:setup_element:INFO:	Scanning clock phase
13:22:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:22:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:22:03:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
13:22:03:setup_element:INFO:	Eye window for uplink 2 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 3 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 4 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
13:22:03:setup_element:INFO:	Eye window for uplink 5 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
13:22:03:setup_element:INFO:	Eye window for uplink 6 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 7 : _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 8 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:22:03:setup_element:INFO:	Eye window for uplink 9 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:22:03:setup_element:INFO:	Eye window for uplink 10: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 11: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 12: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
13:22:03:setup_element:INFO:	Eye window for uplink 13: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
13:22:03:setup_element:INFO:	Eye window for uplink 14: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Eye window for uplink 15: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:22:03:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 1
13:22:03:setup_element:INFO:	Scanning data phases
13:22:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:22:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:22:09:setup_element:INFO:	Data phase scan results for group 0, downlink 1
13:22:09:setup_element:INFO:	Eye window for uplink 2 : ______XXXXXX____________________________
Data delay found: 28
13:22:09:setup_element:INFO:	Eye window for uplink 3 : __XXXXXXXX______________________________
Data delay found: 25
13:22:09:setup_element:INFO:	Eye window for uplink 4 : ____XXXXXXXX____________________________
Data delay found: 27
13:22:09:setup_element:INFO:	Eye window for uplink 5 : _XXXXXXX_______________________________X
Data delay found: 23
13:22:09:setup_element:INFO:	Eye window for uplink 6 : XXXXXX__________________________________
Data delay found: 22
13:22:09:setup_element:INFO:	Eye window for uplink 7 : XXX________________________________XXXXX
Data delay found: 18
13:22:09:setup_element:INFO:	Eye window for uplink 8 : ________________________XXXX____________
Data delay found: 5
13:22:09:setup_element:INFO:	Eye window for uplink 9 : ____________________________XXXXXXX_____
Data delay found: 11
13:22:09:setup_element:INFO:	Eye window for uplink 10: ____________________________XXXXXX______
Data delay found: 10
13:22:09:setup_element:INFO:	Eye window for uplink 11: _______________________________XXXXXX___
Data delay found: 13
13:22:09:setup_element:INFO:	Eye window for uplink 12: ______________________________XXXXXX____
Data delay found: 12
13:22:09:setup_element:INFO:	Eye window for uplink 13: X_______________________________XXXXXXXX
Data delay found: 16
13:22:09:setup_element:INFO:	Eye window for uplink 14: ____________________________XXXXXXXX____
Data delay found: 11
13:22:09:setup_element:INFO:	Eye window for uplink 15: ______________________________XXXXXXXX__
Data delay found: 13
13:22:09:setup_element:INFO:	Setting the data phase to 28 for uplink 2
13:22:09:setup_element:INFO:	Setting the data phase to 25 for uplink 3
13:22:09:setup_element:INFO:	Setting the data phase to 27 for uplink 4
13:22:09:setup_element:INFO:	Setting the data phase to 23 for uplink 5
13:22:09:setup_element:INFO:	Setting the data phase to 22 for uplink 6
13:22:09:setup_element:INFO:	Setting the data phase to 18 for uplink 7
13:22:09:setup_element:INFO:	Setting the data phase to 5 for uplink 8
13:22:09:setup_element:INFO:	Setting the data phase to 11 for uplink 9
13:22:09:setup_element:INFO:	Setting the data phase to 10 for uplink 10
13:22:09:setup_element:INFO:	Setting the data phase to 13 for uplink 11
13:22:09:setup_element:INFO:	Setting the data phase to 12 for uplink 12
13:22:09:setup_element:INFO:	Setting the data phase to 16 for uplink 13
13:22:09:setup_element:INFO:	Setting the data phase to 11 for uplink 14
13:22:09:setup_element:INFO:	Setting the data phase to 13 for uplink 15
13:22:09:setup_element:INFO:	Beginning SMX ASICs map scan
13:22:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:22:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:22:09:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
13:22:09:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
13:22:09:uplink:INFO:	Setting uplinks mask [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
13:22:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
13:22:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
13:22:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
13:22:10:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
13:22:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
13:22:10:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
13:22:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
13:22:10:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
13:22:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
13:22:10:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
13:22:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
13:22:10:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
13:22:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
13:22:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
13:22:12:setup_element:INFO:	Performing Elink synchronization
13:22:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:22:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
13:22:12:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
13:22:12:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
13:22:12:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
13:22:12:uplink:INFO:	Enabling uplinks [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
13:22:12:ST3_emu_feb:DEBUG:	Chip address:  	0x1
13:22:12:ST3_emu_feb:DEBUG:	Chip address:  	0x2
13:22:12:ST3_emu_feb:DEBUG:	Chip address:  	0x3
13:22:13:ST3_emu_feb:DEBUG:	Chip address:  	0x4
13:22:13:ST3_emu_feb:DEBUG:	Chip address:  	0x5
13:22:13:ST3_emu_feb:DEBUG:	Chip address:  	0x6
13:22:13:ST3_emu_feb:DEBUG:	Chip address:  	0x7
13:22:13:febtest:INFO:	Init all SMX (CSA): 30
13:22:25:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:22:26:febtest:INFO:	08-01 | XA-000-09-004-003-008-018-14 |  18.7 | 1195.1
13:22:26:febtest:INFO:	03-02 | XA-000-09-004-006-015-009-02 |  25.1 | 1189.2
13:22:26:febtest:INFO:	10-03 | XA-000-09-004-003-008-022-14 |  31.4 | 1153.7
13:22:26:febtest:INFO:	05-04 | XA-000-09-004-006-006-013-03 |  34.6 | 1141.9
13:22:27:febtest:INFO:	12-05 | XA-000-09-004-003-009-026-03 |  28.2 | 1165.6
13:22:27:febtest:INFO:	07-06 | XA-000-08-002-003-007-132-13 |  25.1 | 1195.1
13:22:27:febtest:INFO:	14-07 | XA-000-09-004-003-008-019-14 |  47.3 | 1094.2
13:22:28:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
13:22:29:febtest:ERROR:	HW addres 1 != 0
13:22:36:ST3_smx:INFO:	chip: 8-1 	 18.745682 C 	 1206.851500 mV
13:22:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:36:ST3_smx:INFO:		Electrons
13:22:36:ST3_smx:INFO:	# loops 0
13:22:37:ST3_smx:INFO:	# loops 1
13:22:39:ST3_smx:INFO:	# loops 2
13:22:41:ST3_smx:INFO:	Total # of broken channels: 1
13:22:41:ST3_smx:INFO:	List of broken channels: [38]
13:22:41:ST3_smx:INFO:	Total # of broken channels: 1
13:22:41:ST3_smx:INFO:	List of broken channels: [14]
13:22:42:ST3_smx:INFO:	chip: 3-2 	 25.062742 C 	 1195.082160 mV
13:22:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:42:ST3_smx:INFO:		Electrons
13:22:42:ST3_smx:INFO:	# loops 0
13:22:44:ST3_smx:INFO:	# loops 1
13:22:46:ST3_smx:INFO:	# loops 2
13:22:47:ST3_smx:INFO:	Total # of broken channels: 0
13:22:47:ST3_smx:INFO:	List of broken channels: []
13:22:47:ST3_smx:INFO:	Total # of broken channels: 0
13:22:47:ST3_smx:INFO:	List of broken channels: []
13:22:49:ST3_smx:INFO:	chip: 10-3 	 31.389742 C 	 1165.571835 mV
13:22:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:49:ST3_smx:INFO:		Electrons
13:22:49:ST3_smx:INFO:	# loops 0
13:22:51:ST3_smx:INFO:	# loops 1
13:22:52:ST3_smx:INFO:	# loops 2
13:22:54:ST3_smx:INFO:	Total # of broken channels: 0
13:22:54:ST3_smx:INFO:	List of broken channels: []
13:22:54:ST3_smx:INFO:	Total # of broken channels: 3
13:22:54:ST3_smx:INFO:	List of broken channels: [3, 5, 7]
13:22:56:ST3_smx:INFO:	chip: 5-4 	 34.556970 C 	 1147.806000 mV
13:22:56:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:56:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:22:56:ST3_smx:INFO:		Electrons
13:22:56:ST3_smx:INFO:	# loops 0
13:22:57:ST3_smx:INFO:	# loops 1
13:22:59:ST3_smx:INFO:	# loops 2
13:23:01:ST3_smx:INFO:	Total # of broken channels: 0
13:23:01:ST3_smx:INFO:	List of broken channels: []
13:23:01:ST3_smx:INFO:	Total # of broken channels: 0
13:23:01:ST3_smx:INFO:	List of broken channels: []
13:23:02:ST3_smx:INFO:	chip: 12-5 	 28.225000 C 	 1183.292940 mV
13:23:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:23:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:23:02:ST3_smx:INFO:		Electrons
13:23:02:ST3_smx:INFO:	# loops 0
13:23:04:ST3_smx:INFO:	# loops 1
13:23:06:ST3_smx:INFO:	# loops 2
13:23:08:ST3_smx:INFO:	Total # of broken channels: 0
13:23:08:ST3_smx:INFO:	List of broken channels: []
13:23:08:ST3_smx:INFO:	Total # of broken channels: 0
13:23:08:ST3_smx:INFO:	List of broken channels: []
13:23:09:ST3_smx:INFO:	chip: 7-6 	 25.062742 C 	 1200.969315 mV
13:23:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:23:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:23:09:ST3_smx:INFO:		Electrons
13:23:09:ST3_smx:INFO:	# loops 0
13:23:11:ST3_smx:INFO:	# loops 1
13:23:13:ST3_smx:INFO:	# loops 2
13:23:14:ST3_smx:INFO:	Total # of broken channels: 0
13:23:14:ST3_smx:INFO:	List of broken channels: []
13:23:14:ST3_smx:INFO:	Total # of broken channels: 21
13:23:14:ST3_smx:INFO:	List of broken channels: [70, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112]
13:23:16:ST3_smx:INFO:	chip: 14-7 	 47.250730 C 	 1106.178435 mV
13:23:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:23:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:23:16:ST3_smx:INFO:		Electrons
13:23:16:ST3_smx:INFO:	# loops 0
13:23:18:ST3_smx:INFO:	# loops 1
13:23:19:ST3_smx:INFO:	# loops 2
13:23:21:ST3_smx:INFO:	Total # of broken channels: 0
13:23:21:ST3_smx:INFO:	List of broken channels: []
13:23:21:ST3_smx:INFO:	Total # of broken channels: 2
13:23:21:ST3_smx:INFO:	List of broken channels: [17, 23]
13:23:21:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:23:21:febtest:INFO:	08-01 | XA-000-09-004-003-008-018-14 |  18.7 | 1230.3
13:23:22:febtest:INFO:	03-02 | XA-000-09-004-006-015-009-02 |  25.1 | 1218.6
13:23:22:febtest:INFO:	10-03 | XA-000-09-004-003-008-022-14 |  31.4 | 1183.3
13:23:22:febtest:INFO:	05-04 | XA-000-09-004-006-006-013-03 |  37.7 | 1171.5
13:23:22:febtest:INFO:	12-05 | XA-000-09-004-003-009-026-03 |  28.2 | 1218.6
13:23:22:febtest:INFO:	07-06 | XA-000-08-002-003-007-132-13 |  25.1 | 1224.5
13:23:23:febtest:INFO:	14-07 | XA-000-09-004-003-008-019-14 |  50.4 | 1124.0
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_09_23-13_22_01
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1240| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.450', '1.4710', '1.849', '2.3060', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9590', '1.850', '2.5880', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9180', '1.850', '0.9344', '0.000', '0.0000', '0.000', '0.0000']