14:30:50:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:30:50:ST3_Shared:INFO:	                       FEB-Microcable                       
14:30:50:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:30:50:febtest:INFO:	Testing FEB with SN 1263
14:30:52:smx_tester:INFO:	Scanning setup
14:30:52:elinks:INFO:	Disabling clock on downlink 0
14:30:52:elinks:INFO:	Disabling clock on downlink 1
14:30:52:elinks:INFO:	Disabling clock on downlink 2
14:30:52:elinks:INFO:	Disabling clock on downlink 3
14:30:52:elinks:INFO:	Disabling clock on downlink 4
14:30:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:30:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:30:52:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:30:52:elinks:INFO:	Disabling clock on downlink 0
14:30:52:elinks:INFO:	Disabling clock on downlink 1
14:30:52:elinks:INFO:	Disabling clock on downlink 2
14:30:52:elinks:INFO:	Disabling clock on downlink 3
14:30:52:elinks:INFO:	Disabling clock on downlink 4
14:30:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:30:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
14:30:52:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
14:30:52:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:30:52:elinks:INFO:	Disabling clock on downlink 0
14:30:52:elinks:INFO:	Disabling clock on downlink 1
14:30:52:elinks:INFO:	Disabling clock on downlink 2
14:30:52:elinks:INFO:	Disabling clock on downlink 3
14:30:52:elinks:INFO:	Disabling clock on downlink 4
14:30:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:30:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:30:52:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:30:52:elinks:INFO:	Disabling clock on downlink 0
14:30:52:elinks:INFO:	Disabling clock on downlink 1
14:30:52:elinks:INFO:	Disabling clock on downlink 2
14:30:52:elinks:INFO:	Disabling clock on downlink 3
14:30:52:elinks:INFO:	Disabling clock on downlink 4
14:30:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:30:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:30:52:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:30:52:elinks:INFO:	Disabling clock on downlink 0
14:30:52:elinks:INFO:	Disabling clock on downlink 1
14:30:52:elinks:INFO:	Disabling clock on downlink 2
14:30:52:elinks:INFO:	Disabling clock on downlink 3
14:30:52:elinks:INFO:	Disabling clock on downlink 4
14:30:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:30:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:30:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:30:53:setup_element:INFO:	Scanning clock phase
14:30:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:30:53:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:30:53:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
14:30:53:setup_element:INFO:	Eye window for uplink 0 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:30:53:setup_element:INFO:	Eye window for uplink 1 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:30:53:setup_element:INFO:	Eye window for uplink 4 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:30:53:setup_element:INFO:	Eye window for uplink 5 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:30:53:setup_element:INFO:	Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
14:30:53:setup_element:INFO:	Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
14:30:53:setup_element:INFO:	Eye window for uplink 10: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:30:53:setup_element:INFO:	Eye window for uplink 11: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:30:53:setup_element:INFO:	Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:30:53:setup_element:INFO:	Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:30:53:setup_element:INFO:	Eye window for uplink 14: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:30:53:setup_element:INFO:	Eye window for uplink 15: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:30:53:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
14:30:53:setup_element:INFO:	Scanning data phases
14:30:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:30:53:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:30:58:setup_element:INFO:	Data phase scan results for group 0, downlink 1
14:30:58:setup_element:INFO:	Eye window for uplink 0 : _____________XXXXXX_____________________
Data delay found: 35
14:30:58:setup_element:INFO:	Eye window for uplink 1 : ________XXXXXX__________________________
Data delay found: 30
14:30:58:setup_element:INFO:	Eye window for uplink 4 : ________XXXXXX__________________________
Data delay found: 30
14:30:58:setup_element:INFO:	Eye window for uplink 5 : ____XXXXXX______________________________
Data delay found: 26
14:30:58:setup_element:INFO:	Eye window for uplink 8 : __________________________XXXXXX________
Data delay found: 8
14:30:58:setup_element:INFO:	Eye window for uplink 9 : ________________________________XXXXXX__
Data delay found: 14
14:30:58:setup_element:INFO:	Eye window for uplink 10: ____________________________XXXXXXXX____
Data delay found: 11
14:30:58:setup_element:INFO:	Eye window for uplink 11: X______________________________XXXXXXXXX
Data delay found: 15
14:30:58:setup_element:INFO:	Eye window for uplink 12: _____________________________XXXXXX_____
Data delay found: 11
14:30:58:setup_element:INFO:	Eye window for uplink 13: __________________________________XXXXX_
Data delay found: 16
14:30:58:setup_element:INFO:	Eye window for uplink 14: ____________________________XXXXXXX_____
Data delay found: 11
14:30:58:setup_element:INFO:	Eye window for uplink 15: ______________________________XXXXXXXX__
Data delay found: 13
14:30:58:setup_element:INFO:	Setting the data phase to 35 for uplink 0
14:30:58:setup_element:INFO:	Setting the data phase to 30 for uplink 1
14:30:58:setup_element:INFO:	Setting the data phase to 30 for uplink 4
14:30:58:setup_element:INFO:	Setting the data phase to 26 for uplink 5
14:30:58:setup_element:INFO:	Setting the data phase to 8 for uplink 8
14:30:58:setup_element:INFO:	Setting the data phase to 14 for uplink 9
14:30:58:setup_element:INFO:	Setting the data phase to 11 for uplink 10
14:30:58:setup_element:INFO:	Setting the data phase to 15 for uplink 11
14:30:58:setup_element:INFO:	Setting the data phase to 11 for uplink 12
14:30:58:setup_element:INFO:	Setting the data phase to 16 for uplink 13
14:30:58:setup_element:INFO:	Setting the data phase to 11 for uplink 14
14:30:58:setup_element:INFO:	Setting the data phase to 13 for uplink 15
==============================================OOO==============================================
14:30:58:setup_element:INFO:	Beginning SMX ASICs map scan
14:30:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:30:58:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:30:58:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:30:59:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:30:59:uplink:INFO:	Setting uplinks mask [0, 1, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15]
14:30:59:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:30:59:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:30:59:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:30:59:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:30:59:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:30:59:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:30:59:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:30:59:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:31:00:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:31:00:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:31:00:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:31:00:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:31:01:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 70
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXXXXX__
      Uplink  1: _______________________________________________________________________XXXXXXX__
      Uplink  4: ______________________________________________________________________XXXXXXXX__
      Uplink  5: ______________________________________________________________________XXXXXXXX__
      Uplink  8: _____________________________________________________________________XXXXXXXX___
      Uplink  9: _____________________________________________________________________XXXXXXXX___
      Uplink 10: _______________________________________________________________________XXXXXXXX_
      Uplink 11: _______________________________________________________________________XXXXXXXX_
      Uplink 12: ______________________________________________________________________XXXXXXXX__
      Uplink 13: ______________________________________________________________________XXXXXXXX__
      Uplink 14: _______________________________________________________________________XXXXXXX__
      Uplink 15: _______________________________________________________________________XXXXXXX__
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 1:
      Optimal Phase: 30
      Window Length: 34
      Eye Window: ________XXXXXX__________________________
    Uplink 4:
      Optimal Phase: 30
      Window Length: 34
      Eye Window: ________XXXXXX__________________________
    Uplink 5:
      Optimal Phase: 26
      Window Length: 34
      Eye Window: ____XXXXXX______________________________
    Uplink 8:
      Optimal Phase: 8
      Window Length: 34
      Eye Window: __________________________XXXXXX________
    Uplink 9:
      Optimal Phase: 14
      Window Length: 34
      Eye Window: ________________________________XXXXXX__
    Uplink 10:
      Optimal Phase: 11
      Window Length: 32
      Eye Window: ____________________________XXXXXXXX____
    Uplink 11:
      Optimal Phase: 15
      Window Length: 30
      Eye Window: X______________________________XXXXXXXXX
    Uplink 12:
      Optimal Phase: 11
      Window Length: 34
      Eye Window: _____________________________XXXXXX_____
    Uplink 13:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 14:
      Optimal Phase: 11
      Window Length: 33
      Eye Window: ____________________________XXXXXXX_____
    Uplink 15:
      Optimal Phase: 13
      Window Length: 32
      Eye Window: ______________________________XXXXXXXX__

==============================================OOO==============================================
14:31:01:setup_element:INFO:	Performing Elink synchronization
14:31:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:31:01:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:31:01:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:31:01:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
14:31:01:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
14:31:01:uplink:INFO:	Enabling uplinks [0, 1, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:31:02:febtest:INFO:	Init all SMX (CSA): 30
14:31:13:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:31:13:febtest:INFO:	01-00 | XA-000-09-004-004-013-024-15 |  25.1 | 1195.1
14:31:13:febtest:INFO:	08-01 | XA-000-09-004-003-010-019-13 |  21.9 | 1195.1
14:31:13:febtest:INFO:	10-03 | XA-000-09-004-003-015-019-06 |  34.6 | 1159.7
14:31:13:febtest:INFO:	05-04 | XA-000-09-004-003-013-019-05 |  34.6 | 1171.5
14:31:14:febtest:INFO:	12-05 | XA-000-09-004-003-014-019-11 |  15.6 | 1218.6
14:31:14:febtest:INFO:	14-07 | XA-000-09-004-003-014-018-11 |  25.1 | 1195.1
14:31:15:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:31:16:febtest:ERROR:	HW addres 3 != 2
14:31:20:ST3_smx:INFO:	chip: 1-0 	 25.062742 C 	 1200.969315 mV
14:31:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:20:ST3_smx:INFO:		Electrons
14:31:20:ST3_smx:INFO:	# loops 0
14:31:22:ST3_smx:INFO:	# loops 1
14:31:23:ST3_smx:INFO:	# loops 2
14:31:25:ST3_smx:INFO:	Total # of broken channels: 0
14:31:25:ST3_smx:INFO:	List of broken channels: []
14:31:25:ST3_smx:INFO:	Total # of broken channels: 0
14:31:25:ST3_smx:INFO:	List of broken channels: []
14:31:27:ST3_smx:INFO:	chip: 8-1 	 21.902970 C 	 1206.851500 mV
14:31:27:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:27:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:27:ST3_smx:INFO:		Electrons
14:31:27:ST3_smx:INFO:	# loops 0
14:31:28:ST3_smx:INFO:	# loops 1
14:31:30:ST3_smx:INFO:	# loops 2
14:31:31:ST3_smx:INFO:	Total # of broken channels: 0
14:31:31:ST3_smx:INFO:	List of broken channels: []
14:31:31:ST3_smx:INFO:	Total # of broken channels: 0
14:31:31:ST3_smx:INFO:	List of broken channels: []
14:31:33:ST3_smx:INFO:	chip: 10-3 	 34.556970 C 	 1165.571835 mV
14:31:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:33:ST3_smx:INFO:		Electrons
14:31:33:ST3_smx:INFO:	# loops 0
14:31:35:ST3_smx:INFO:	# loops 1
14:31:36:ST3_smx:INFO:	# loops 2
14:31:38:ST3_smx:INFO:	Total # of broken channels: 0
14:31:38:ST3_smx:INFO:	List of broken channels: []
14:31:38:ST3_smx:INFO:	Total # of broken channels: 0
14:31:38:ST3_smx:INFO:	List of broken channels: []
14:31:40:ST3_smx:INFO:	chip: 5-4 	 34.556970 C 	 1177.390875 mV
14:31:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:40:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:40:ST3_smx:INFO:		Electrons
14:31:40:ST3_smx:INFO:	# loops 0
14:31:41:ST3_smx:INFO:	# loops 1
14:31:43:ST3_smx:INFO:	# loops 2
14:31:44:ST3_smx:INFO:	Total # of broken channels: 0
14:31:44:ST3_smx:INFO:	List of broken channels: []
14:31:44:ST3_smx:INFO:	Total # of broken channels: 4
14:31:44:ST3_smx:INFO:	List of broken channels: [4, 6, 8, 10]
14:31:46:ST3_smx:INFO:	chip: 12-5 	 15.590880 C 	 1236.187875 mV
14:31:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:46:ST3_smx:INFO:		Electrons
14:31:46:ST3_smx:INFO:	# loops 0
14:31:48:ST3_smx:INFO:	# loops 1
14:31:49:ST3_smx:INFO:	# loops 2
14:31:51:ST3_smx:INFO:	Total # of broken channels: 0
14:31:51:ST3_smx:INFO:	List of broken channels: []
14:31:51:ST3_smx:INFO:	Total # of broken channels: 19
14:31:51:ST3_smx:INFO:	List of broken channels: [3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 39, 41]
14:31:53:ST3_smx:INFO:	chip: 14-7 	 25.062742 C 	 1212.728715 mV
14:31:53:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:53:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:53:ST3_smx:INFO:		Electrons
14:31:53:ST3_smx:INFO:	# loops 0
14:31:54:ST3_smx:INFO:	# loops 1
14:31:56:ST3_smx:INFO:	# loops 2
14:31:57:ST3_smx:INFO:	Total # of broken channels: 0
14:31:57:ST3_smx:INFO:	List of broken channels: []
14:31:57:ST3_smx:INFO:	Total # of broken channels: 0
14:31:57:ST3_smx:INFO:	List of broken channels: []
14:31:58:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:31:58:febtest:INFO:	01-00 | XA-000-09-004-004-013-024-15 |  25.1 | 1230.3
14:31:58:febtest:INFO:	08-01 | XA-000-09-004-003-010-019-13 |  25.1 | 1230.3
14:31:58:febtest:INFO:	10-03 | XA-000-09-004-003-015-019-06 |  34.6 | 1189.2
14:31:59:febtest:INFO:	05-04 | XA-000-09-004-003-013-019-05 |  34.6 | 1195.1
14:31:59:febtest:INFO:	12-05 | XA-000-09-004-003-014-019-11 |  18.7 | 1253.7
14:31:59:febtest:INFO:	14-07 | XA-000-09-004-003-014-018-11 |  25.1 | 1236.2
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_10_09-14_30_50
OPERATOR  : Oleksandr S.; Irakli K.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1263| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.449', '1.8620', '1.849', '2.2890', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9110', '1.850', '2.4070', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.8600', '1.850', '0.9650', '0.000', '0.0000', '0.000', '0.0000']