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FEB_1284 15.11.24 09:15:00
Info
09:15:00:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:15:00:ST3_Shared:INFO: FEB-Sensor
09:15:00:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:15:10:ST3_ModuleSelector:DEBUG:
09:15:10:ST3_ModuleSelector:DEBUG:
09:15:10:ST3_ModuleSelector:DEBUG:
09:15:10:ST3_ModuleSelector:DEBUG:
09:15:10:ST3_ModuleSelector:DEBUG: Unknown
09:15:19:ST3_ModuleSelector:DEBUG: M3DR2T1000121B2
09:15:19:ST3_ModuleSelector:DEBUG: L3DR200012
09:15:19:ST3_ModuleSelector:DEBUG: 07102
09:15:19:ST3_ModuleSelector:DEBUG: 62x42
09:15:19:ST3_ModuleSelector:DEBUG: A
09:15:19:ST3_ModuleSelector:DEBUG: M3DR2T1000121B2
09:15:19:ST3_ModuleSelector:DEBUG: L3DR200012
09:15:19:ST3_ModuleSelector:DEBUG: 07102
09:15:19:ST3_ModuleSelector:DEBUG: 62x42
09:15:19:ST3_ModuleSelector:DEBUG: A
09:15:26:ST3_ModuleSelector:INFO: M3DR2T1000121B2
09:15:26:ST3_ModuleSelector:INFO: 07102
09:15:26:febtest:INFO: Testing FEB with SN 1284
09:15:28:smx_tester:INFO: Scanning setup
09:15:28:elinks:INFO: Disabling clock on downlink 0
09:15:28:elinks:INFO: Disabling clock on downlink 1
09:15:28:elinks:INFO: Disabling clock on downlink 2
09:15:28:elinks:INFO: Disabling clock on downlink 3
09:15:28:elinks:INFO: Disabling clock on downlink 4
09:15:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:15:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
09:15:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:15:28:elinks:INFO: Disabling clock on downlink 0
09:15:28:elinks:INFO: Disabling clock on downlink 1
09:15:28:elinks:INFO: Disabling clock on downlink 2
09:15:28:elinks:INFO: Disabling clock on downlink 3
09:15:28:elinks:INFO: Disabling clock on downlink 4
09:15:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:15:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
09:15:28:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
09:15:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:15:28:elinks:INFO: Disabling clock on downlink 0
09:15:28:elinks:INFO: Disabling clock on downlink 1
09:15:28:elinks:INFO: Disabling clock on downlink 2
09:15:28:elinks:INFO: Disabling clock on downlink 3
09:15:28:elinks:INFO: Disabling clock on downlink 4
09:15:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:15:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:15:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:15:28:elinks:INFO: Disabling clock on downlink 0
09:15:28:elinks:INFO: Disabling clock on downlink 1
09:15:28:elinks:INFO: Disabling clock on downlink 2
09:15:28:elinks:INFO: Disabling clock on downlink 3
09:15:28:elinks:INFO: Disabling clock on downlink 4
09:15:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:15:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
09:15:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:15:28:elinks:INFO: Disabling clock on downlink 0
09:15:28:elinks:INFO: Disabling clock on downlink 1
09:15:28:elinks:INFO: Disabling clock on downlink 2
09:15:28:elinks:INFO: Disabling clock on downlink 3
09:15:28:elinks:INFO: Disabling clock on downlink 4
09:15:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:15:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
09:15:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
09:15:28:setup_element:INFO: Scanning clock phase
09:15:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:15:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:15:29:setup_element:INFO: Clock phase scan results for group 0, downlink 1
09:15:29:setup_element:INFO: Eye window for uplink 0 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
09:15:29:setup_element:INFO: Eye window for uplink 1 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
09:15:29:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:15:29:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:15:29:setup_element:INFO: Eye window for uplink 10: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
09:15:29:setup_element:INFO: Eye window for uplink 11: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
09:15:29:setup_element:INFO: Eye window for uplink 12: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:15:29:setup_element:INFO: Eye window for uplink 13: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
09:15:29:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
09:15:29:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 1
==============================================OOO==============================================
09:15:29:setup_element:INFO: Scanning data phases
09:15:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:15:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:15:34:setup_element:INFO: Data phase scan results for group 0, downlink 1
09:15:34:setup_element:INFO: Eye window for uplink 0 : ____________XXXXXXXXXX__________________
Data delay found: 36
09:15:34:setup_element:INFO: Eye window for uplink 1 : ______XXXXXXXXXX________________________
Data delay found: 30
09:15:34:setup_element:INFO: Eye window for uplink 2 : ______XXXXXXXXX_________________________
Data delay found: 30
09:15:34:setup_element:INFO: Eye window for uplink 3 : ___XXXXXXXXX____________________________
Data delay found: 27
09:15:34:setup_element:INFO: Eye window for uplink 4 : ______XXXXXXX___________________________
Data delay found: 29
09:15:34:setup_element:INFO: Eye window for uplink 5 : __XXXXXXX_______________________________
Data delay found: 25
09:15:34:setup_element:INFO: Eye window for uplink 6 : XXXXXX__________________________________
Data delay found: 22
09:15:34:setup_element:INFO: Eye window for uplink 7 : XXX_________________________________XXXX
Data delay found: 19
09:15:34:setup_element:INFO: Eye window for uplink 8 : ______________________XXXXXXX___________
Data delay found: 5
09:15:34:setup_element:INFO: Eye window for uplink 9 : __________________________XXXXXXXX______
Data delay found: 9
09:15:34:setup_element:INFO: Eye window for uplink 10: ___________________________XXXXXXX______
Data delay found: 10
09:15:34:setup_element:INFO: Eye window for uplink 11: ______________________________XXXXXXXX__
Data delay found: 13
09:15:34:setup_element:INFO: Eye window for uplink 12: _________________________XXXXXXXX_______
Data delay found: 8
09:15:34:setup_element:INFO: Eye window for uplink 13: ___________________________X_XXXXXXX____
Data delay found: 11
09:15:34:setup_element:INFO: Eye window for uplink 14: _____________________________XXXXXXX____
Data delay found: 12
09:15:34:setup_element:INFO: Eye window for uplink 15: _______________________________XXXXXXX__
Data delay found: 14
09:15:34:setup_element:INFO: Setting the data phase to 36 for uplink 0
09:15:34:setup_element:INFO: Setting the data phase to 30 for uplink 1
09:15:34:setup_element:INFO: Setting the data phase to 30 for uplink 2
09:15:34:setup_element:INFO: Setting the data phase to 27 for uplink 3
09:15:34:setup_element:INFO: Setting the data phase to 29 for uplink 4
09:15:34:setup_element:INFO: Setting the data phase to 25 for uplink 5
09:15:34:setup_element:INFO: Setting the data phase to 22 for uplink 6
09:15:34:setup_element:INFO: Setting the data phase to 19 for uplink 7
09:15:34:setup_element:INFO: Setting the data phase to 5 for uplink 8
09:15:34:setup_element:INFO: Setting the data phase to 9 for uplink 9
09:15:34:setup_element:INFO: Setting the data phase to 10 for uplink 10
09:15:34:setup_element:INFO: Setting the data phase to 13 for uplink 11
09:15:34:setup_element:INFO: Setting the data phase to 8 for uplink 12
09:15:34:setup_element:INFO: Setting the data phase to 11 for uplink 13
09:15:34:setup_element:INFO: Setting the data phase to 12 for uplink 14
09:15:34:setup_element:INFO: Setting the data phase to 14 for uplink 15
==============================================OOO==============================================
09:15:34:setup_element:INFO: Beginning SMX ASICs map scan
09:15:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:15:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:15:34:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
09:15:34:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
09:15:34:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
09:15:34:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
09:15:34:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
09:15:35:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
09:15:35:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
09:15:35:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
09:15:35:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
09:15:35:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
09:15:35:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
09:15:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
09:15:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
09:15:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
09:15:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
09:15:35:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
09:15:36:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
09:15:36:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
09:15:36:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
09:15:37:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 68
Eye Windows:
Uplink 0: X________________________________________________________________________XXXXXXX
Uplink 1: X________________________________________________________________________XXXXXXX
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: _______________________________________________________________________XXXXXXXX_
Uplink 7: _______________________________________________________________________XXXXXXXX_
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: _____________________________________________________________________XXXXXXXXX__
Uplink 11: _____________________________________________________________________XXXXXXXXX__
Uplink 12: _____________________________________________________________________XXXXXXXX___
Uplink 13: _____________________________________________________________________XXXXXXXX___
Uplink 14: ______________________________________________________________________XXXXXXXXX_
Uplink 15: ______________________________________________________________________XXXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 36
Window Length: 30
Eye Window: ____________XXXXXXXXXX__________________
Uplink 1:
Optimal Phase: 30
Window Length: 30
Eye Window: ______XXXXXXXXXX________________________
Uplink 2:
Optimal Phase: 30
Window Length: 31
Eye Window: ______XXXXXXXXX_________________________
Uplink 3:
Optimal Phase: 27
Window Length: 31
Eye Window: ___XXXXXXXXX____________________________
Uplink 4:
Optimal Phase: 29
Window Length: 33
Eye Window: ______XXXXXXX___________________________
Uplink 5:
Optimal Phase: 25
Window Length: 33
Eye Window: __XXXXXXX_______________________________
Uplink 6:
Optimal Phase: 22
Window Length: 34
Eye Window: XXXXXX__________________________________
Uplink 7:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 8:
Optimal Phase: 5
Window Length: 33
Eye Window: ______________________XXXXXXX___________
Uplink 9:
Optimal Phase: 9
Window Length: 32
Eye Window: __________________________XXXXXXXX______
Uplink 10:
Optimal Phase: 10
Window Length: 33
Eye Window: ___________________________XXXXXXX______
Uplink 11:
Optimal Phase: 13
Window Length: 32
Eye Window: ______________________________XXXXXXXX__
Uplink 12:
Optimal Phase: 8
Window Length: 32
Eye Window: _________________________XXXXXXXX_______
Uplink 13:
Optimal Phase: 11
Window Length: 31
Eye Window: ___________________________X_XXXXXXX____
Uplink 14:
Optimal Phase: 12
Window Length: 33
Eye Window: _____________________________XXXXXXX____
Uplink 15:
Optimal Phase: 14
Window Length: 33
Eye Window: _______________________________XXXXXXX__
==============================================OOO==============================================
09:15:37:setup_element:INFO: Performing Elink synchronization
09:15:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:15:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:15:37:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
09:15:37:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
09:15:37:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
09:15:37:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
09:15:38:febtest:INFO: Init all SMX (CSA): 30
09:15:53:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:15:53:febtest:INFO: 01-00 | XA-000-09-004-003-004-023-04 | 21.9 | 1177.4
09:15:53:febtest:INFO: 08-01 | XA-000-09-004-003-004-009-03 | 21.9 | 1165.6
09:15:53:febtest:INFO: 03-02 | XA-000-09-004-002-015-016-14 | 15.6 | 1195.1
09:15:53:febtest:INFO: 10-03 | XA-000-09-004-003-004-016-04 | 28.2 | 1147.8
09:15:54:febtest:INFO: 05-04 | XA-000-09-004-003-004-017-04 | 12.4 | 1206.9
09:15:54:febtest:INFO: 12-05 | XA-000-09-004-003-004-012-03 | 3.0 | 1224.5
09:15:54:febtest:INFO: 07-06 | XA-000-09-004-003-004-013-03 | 28.2 | 1153.7
09:15:54:febtest:INFO: 14-07 | XA-000-09-004-003-004-008-03 | 21.9 | 1177.4
09:15:55:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
09:15:57:ST3_smx:INFO: chip: 1-0 21.902970 C 1189.190035 mV
09:15:57:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:15:57:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:15:57:ST3_smx:INFO: Electrons
09:15:57:ST3_smx:INFO: # loops 0
09:15:59:ST3_smx:INFO: # loops 1
09:16:01:ST3_smx:INFO: # loops 2
09:16:02:ST3_smx:INFO: # loops 3
09:16:04:ST3_smx:INFO: # loops 4
09:16:06:ST3_smx:INFO: Total # of broken channels: 0
09:16:06:ST3_smx:INFO: List of broken channels: []
09:16:06:ST3_smx:INFO: Total # of broken channels: 1
09:16:06:ST3_smx:INFO: List of broken channels: [126]
09:16:07:ST3_smx:INFO: chip: 8-1 21.902970 C 1183.292940 mV
09:16:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:07:ST3_smx:INFO: Electrons
09:16:07:ST3_smx:INFO: # loops 0
09:16:09:ST3_smx:INFO: # loops 1
09:16:11:ST3_smx:INFO: # loops 2
09:16:13:ST3_smx:INFO: # loops 3
09:16:14:ST3_smx:INFO: # loops 4
09:16:16:ST3_smx:INFO: Total # of broken channels: 0
09:16:16:ST3_smx:INFO: List of broken channels: []
09:16:16:ST3_smx:INFO: Total # of broken channels: 1
09:16:16:ST3_smx:INFO: List of broken channels: [1]
09:16:18:ST3_smx:INFO: chip: 3-2 18.745682 C 1206.851500 mV
09:16:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:18:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:18:ST3_smx:INFO: Electrons
09:16:18:ST3_smx:INFO: # loops 0
09:16:19:ST3_smx:INFO: # loops 1
09:16:21:ST3_smx:INFO: # loops 2
09:16:23:ST3_smx:INFO: # loops 3
09:16:24:ST3_smx:INFO: # loops 4
09:16:26:ST3_smx:INFO: Total # of broken channels: 0
09:16:26:ST3_smx:INFO: List of broken channels: []
09:16:26:ST3_smx:INFO: Total # of broken channels: 4
09:16:26:ST3_smx:INFO: List of broken channels: [118, 120, 122, 126]
09:16:27:ST3_smx:INFO: chip: 10-3 28.225000 C 1153.732915 mV
09:16:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:27:ST3_smx:INFO: Electrons
09:16:28:ST3_smx:INFO: # loops 0
09:16:29:ST3_smx:INFO: # loops 1
09:16:31:ST3_smx:INFO: # loops 2
09:16:33:ST3_smx:INFO: # loops 3
09:16:34:ST3_smx:INFO: # loops 4
09:16:36:ST3_smx:INFO: Total # of broken channels: 0
09:16:36:ST3_smx:INFO: List of broken channels: []
09:16:36:ST3_smx:INFO: Total # of broken channels: 0
09:16:36:ST3_smx:INFO: List of broken channels: []
09:16:38:ST3_smx:INFO: chip: 5-4 15.590880 C 1212.728715 mV
09:16:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:38:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:38:ST3_smx:INFO: Electrons
09:16:38:ST3_smx:INFO: # loops 0
09:16:39:ST3_smx:INFO: # loops 1
09:16:41:ST3_smx:INFO: # loops 2
09:16:43:ST3_smx:INFO: # loops 3
09:16:44:ST3_smx:INFO: # loops 4
09:16:46:ST3_smx:INFO: Total # of broken channels: 0
09:16:46:ST3_smx:INFO: List of broken channels: []
09:16:46:ST3_smx:INFO: Total # of broken channels: 0
09:16:46:ST3_smx:INFO: List of broken channels: []
09:16:48:ST3_smx:INFO: chip: 12-5 6.141382 C 1236.187875 mV
09:16:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:48:ST3_smx:INFO: Electrons
09:16:48:ST3_smx:INFO: # loops 0
09:16:49:ST3_smx:INFO: # loops 1
09:16:51:ST3_smx:INFO: # loops 2
09:16:53:ST3_smx:INFO: # loops 3
09:16:54:ST3_smx:INFO: # loops 4
09:16:56:ST3_smx:INFO: Total # of broken channels: 0
09:16:56:ST3_smx:INFO: List of broken channels: []
09:16:56:ST3_smx:INFO: Total # of broken channels: 0
09:16:56:ST3_smx:INFO: List of broken channels: []
09:16:58:ST3_smx:INFO: chip: 7-6 28.225000 C 1165.571835 mV
09:16:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:16:58:ST3_smx:INFO: Electrons
09:16:58:ST3_smx:INFO: # loops 0
09:16:59:ST3_smx:INFO: # loops 1
09:17:01:ST3_smx:INFO: # loops 2
09:17:03:ST3_smx:INFO: # loops 3
09:17:04:ST3_smx:INFO: # loops 4
09:17:06:ST3_smx:INFO: Total # of broken channels: 0
09:17:06:ST3_smx:INFO: List of broken channels: []
09:17:06:ST3_smx:INFO: Total # of broken channels: 0
09:17:06:ST3_smx:INFO: List of broken channels: []
09:17:08:ST3_smx:INFO: chip: 14-7 21.902970 C 1195.082160 mV
09:17:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:17:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:17:08:ST3_smx:INFO: Electrons
09:17:08:ST3_smx:INFO: # loops 0
09:17:09:ST3_smx:INFO: # loops 1
09:17:11:ST3_smx:INFO: # loops 2
09:17:13:ST3_smx:INFO: # loops 3
09:17:14:ST3_smx:INFO: # loops 4
09:17:16:ST3_smx:INFO: Total # of broken channels: 0
09:17:16:ST3_smx:INFO: List of broken channels: []
09:17:16:ST3_smx:INFO: Total # of broken channels: 0
09:17:16:ST3_smx:INFO: List of broken channels: []
09:17:16:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:17:16:febtest:INFO: 01-00 | XA-000-09-004-003-004-023-04 | 21.9 | 1206.9
09:17:17:febtest:INFO: 08-01 | XA-000-09-004-003-004-009-03 | 25.1 | 1201.0
09:17:17:febtest:INFO: 03-02 | XA-000-09-004-002-015-016-14 | 18.7 | 1224.5
09:17:17:febtest:INFO: 10-03 | XA-000-09-004-003-004-016-04 | 31.4 | 1177.4
09:17:17:febtest:INFO: 05-04 | XA-000-09-004-003-004-017-04 | 15.6 | 1230.3
09:17:18:febtest:INFO: 12-05 | XA-000-09-004-003-004-012-03 | 6.1 | 1259.6
09:17:18:febtest:INFO: 07-06 | XA-000-09-004-003-004-013-03 | 28.2 | 1183.3
09:17:18:febtest:INFO: 14-07 | XA-000-09-004-003-004-008-03 | 21.9 | 1236.2
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_11_15-09_15_00
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1284| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
SENSOR_NAME: 07102 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M3DR2T1000121B2
LADDER_NAME: L3DR200012
------------------------------------------------------------
VI_before_Init : ['2.449', '1.8370', '1.849', '1.9910', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9430', '1.850', '2.3900', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9430', '1.850', '0.5162', '0.000', '0.0000', '0.000', '0.0000']