14:13:49:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:13:49:ST3_Shared:INFO:	                         FEB-Sensor                         
14:13:49:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:13:58:ST3_Shared:INFO:	STS mode selected
14:14:05:ST3_ModuleSelector:DEBUG:	M3DR4T1000131B2
14:14:05:ST3_ModuleSelector:DEBUG:	L3DR400013
14:14:05:ST3_ModuleSelector:DEBUG:	01062
14:14:05:ST3_ModuleSelector:DEBUG:	62x42
14:14:05:ST3_ModuleSelector:DEBUG:	C
14:14:05:ST3_ModuleSelector:DEBUG:	M3DR4T1000131B2
14:14:05:ST3_ModuleSelector:DEBUG:	L3DR400013
14:14:05:ST3_ModuleSelector:DEBUG:	01062
14:14:05:ST3_ModuleSelector:DEBUG:	62x42
14:14:05:ST3_ModuleSelector:DEBUG:	C
14:14:10:ST3_ModuleSelector:INFO:	M3DR4T1000131B2
14:14:10:ST3_ModuleSelector:INFO:	01062
14:14:10:febtest:INFO:	Testing FEB with SN 1287
14:14:12:smx_tester:INFO:	Scanning setup
14:14:12:elinks:INFO:	Disabling clock on downlink 0
14:14:12:elinks:INFO:	Disabling clock on downlink 1
14:14:12:elinks:INFO:	Disabling clock on downlink 2
14:14:12:elinks:INFO:	Disabling clock on downlink 3
14:14:12:elinks:INFO:	Disabling clock on downlink 4
14:14:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:14:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:14:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:14:12:elinks:INFO:	Disabling clock on downlink 0
14:14:12:elinks:INFO:	Disabling clock on downlink 1
14:14:12:elinks:INFO:	Disabling clock on downlink 2
14:14:12:elinks:INFO:	Disabling clock on downlink 3
14:14:12:elinks:INFO:	Disabling clock on downlink 4
14:14:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:14:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
14:14:12:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
14:14:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:14:12:elinks:INFO:	Disabling clock on downlink 0
14:14:12:elinks:INFO:	Disabling clock on downlink 1
14:14:12:elinks:INFO:	Disabling clock on downlink 2
14:14:12:elinks:INFO:	Disabling clock on downlink 3
14:14:12:elinks:INFO:	Disabling clock on downlink 4
14:14:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:14:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:14:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:14:12:elinks:INFO:	Disabling clock on downlink 0
14:14:12:elinks:INFO:	Disabling clock on downlink 1
14:14:12:elinks:INFO:	Disabling clock on downlink 2
14:14:12:elinks:INFO:	Disabling clock on downlink 3
14:14:12:elinks:INFO:	Disabling clock on downlink 4
14:14:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:14:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:14:13:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:14:13:elinks:INFO:	Disabling clock on downlink 0
14:14:13:elinks:INFO:	Disabling clock on downlink 1
14:14:13:elinks:INFO:	Disabling clock on downlink 2
14:14:13:elinks:INFO:	Disabling clock on downlink 3
14:14:13:elinks:INFO:	Disabling clock on downlink 4
14:14:13:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:14:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:14:13:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:14:13:setup_element:INFO:	Scanning clock phase
14:14:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:14:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:14:13:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
14:14:13:setup_element:INFO:	Eye window for uplink 0 : XXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXXXX
Clock Delay: 46
14:14:13:setup_element:INFO:	Eye window for uplink 1 : XXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXXXX
Clock Delay: 46
14:14:13:setup_element:INFO:	Eye window for uplink 2 : ________________________________________________________________________________
Clock Delay: 40
14:14:13:setup_element:INFO:	Eye window for uplink 3 : ________________________________________________________________________________
Clock Delay: 40
14:14:13:setup_element:INFO:	Eye window for uplink 4 : XXXXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXX
Clock Delay: 45
14:14:13:setup_element:INFO:	Eye window for uplink 5 : XXXXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXX
Clock Delay: 45
14:14:13:setup_element:INFO:	Eye window for uplink 6 : XXXXXXXXXXXXXX_X_________________________________________________________XXXXXXX
Clock Delay: 44
14:14:13:setup_element:INFO:	Eye window for uplink 7 : XXXXXXXXXXXXXX_X_________________________________________________________XXXXXXX
Clock Delay: 44
14:14:13:setup_element:INFO:	Eye window for uplink 8 : X_____________________________________________________________________XXXXXXXXXX
Clock Delay: 35
14:14:13:setup_element:INFO:	Eye window for uplink 9 : X_____________________________________________________________________XXXXXXXXXX
Clock Delay: 35
14:14:13:setup_element:INFO:	Eye window for uplink 10: X_______________________________________________________________________________
Clock Delay: 40
14:14:13:setup_element:INFO:	Eye window for uplink 11: X_______________________________________________________________________________
Clock Delay: 40
14:14:13:setup_element:INFO:	Eye window for uplink 12: XX______________________________________________________________________________
Clock Delay: 40
14:14:13:setup_element:INFO:	Eye window for uplink 13: XX______________________________________________________________________________
Clock Delay: 40
14:14:13:setup_element:INFO:	Eye window for uplink 14: XXXXXXXXXXXX____________________________________________________________XXXXXXXX
Clock Delay: 41
14:14:13:setup_element:INFO:	Eye window for uplink 15: XXXXXXXXXXXX____________________________________________________________XXXXXXXX
Clock Delay: 41
14:14:13:setup_element:INFO:	Setting the clock phase to 45 for group 0, downlink 1
==============================================OOO==============================================
14:14:13:setup_element:INFO:	Scanning data phases
14:14:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:14:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:14:18:setup_element:INFO:	Data phase scan results for group 0, downlink 1
14:14:18:setup_element:INFO:	Eye window for uplink 0 : XXXXXXXXXX____________________________XX
Data delay found: 23
14:14:18:setup_element:INFO:	Eye window for uplink 1 : XXXXX____________________________XXXXXXX
Data delay found: 18
14:14:18:setup_element:INFO:	Eye window for uplink 2 : XXXXXXXXXXXXXXXXXXXXXXXX______XXXXXXXXXX
Data delay found: 26
14:14:19:setup_element:INFO:	Eye window for uplink 3 : XXXXXXXXXXXXXXXXXXXXXXXX______XXXXXXXXXX
Data delay found: 26
14:14:19:setup_element:INFO:	Eye window for uplink 4 : X_________________________________XXXXXX
Data delay found: 17
14:14:19:setup_element:INFO:	Eye window for uplink 5 : ____________________________XXXXXXXX____
Data delay found: 11
14:14:19:setup_element:INFO:	Eye window for uplink 6 : __________________XXXXXXXXXXXXXXXXX_____
Data delay found: 6
14:14:19:setup_element:INFO:	Eye window for uplink 7 : _______________XXXXXXXXXXXXXXXXX________
Data delay found: 3
14:14:19:setup_element:INFO:	Eye window for uplink 8 : ____________XXXXX_______________________
Data delay found: 34
14:14:19:setup_element:INFO:	Eye window for uplink 9 : ________________XXXXXX__________________
Data delay found: 38
14:14:19:setup_element:INFO:	Eye window for uplink 10: ______________XXXXXXXXX_________________
Data delay found: 38
14:14:19:setup_element:INFO:	Eye window for uplink 11: _________________XXXXXXXX_______________
Data delay found: 0
14:14:19:setup_element:INFO:	Eye window for uplink 12: __XXXXX______XXXXXXXXX_________________X
Data delay found: 30
14:14:19:setup_element:INFO:	Eye window for uplink 13: __XXXXX_______XXXXXXXXXX_______________X
Data delay found: 31
14:14:19:setup_element:INFO:	Eye window for uplink 14: __________XXXXXXXXXXXXXXX_______________
Data delay found: 37
14:14:19:setup_element:INFO:	Eye window for uplink 15: ____________X_XXXXXXXXXXXXXX____________
Data delay found: 39
14:14:19:setup_element:INFO:	Setting the data phase to 23 for uplink 0
14:14:19:setup_element:INFO:	Setting the data phase to 18 for uplink 1
14:14:19:setup_element:INFO:	Setting the data phase to 26 for uplink 2
14:14:19:setup_element:INFO:	Setting the data phase to 26 for uplink 3
14:14:19:setup_element:INFO:	Setting the data phase to 17 for uplink 4
14:14:19:setup_element:INFO:	Setting the data phase to 11 for uplink 5
14:14:19:setup_element:INFO:	Setting the data phase to 6 for uplink 6
14:14:19:setup_element:INFO:	Setting the data phase to 3 for uplink 7
14:14:19:setup_element:INFO:	Setting the data phase to 34 for uplink 8
14:14:19:setup_element:INFO:	Setting the data phase to 38 for uplink 9
14:14:19:setup_element:INFO:	Setting the data phase to 38 for uplink 10
14:14:19:setup_element:INFO:	Setting the data phase to 0 for uplink 11
14:14:19:setup_element:INFO:	Setting the data phase to 30 for uplink 12
14:14:19:setup_element:INFO:	Setting the data phase to 31 for uplink 13
14:14:19:setup_element:INFO:	Setting the data phase to 37 for uplink 14
14:14:19:setup_element:INFO:	Setting the data phase to 39 for uplink 15
==============================================OOO==============================================
14:14:19:setup_element:INFO:	Beginning SMX ASICs map scan
14:14:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:14:19:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:14:19:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:14:19:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:14:19:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:14:19:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:14:19:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:14:19:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:14:19:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:14:19:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:14:19:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:14:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:14:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:14:19:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:14:19:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:14:20:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:14:20:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:14:20:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:14:20:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:14:20:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:14:20:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:14:21:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 45
    Window Length: 49
    Eye Windows:
      Uplink  0: XXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXXXX
      Uplink  1: XXXXXXXXXXXXXXXXXXXXX___________________________________________________XXXXXXXX
      Uplink  2: ________________________________________________________________________________
      Uplink  3: ________________________________________________________________________________
      Uplink  4: XXXXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXX
      Uplink  5: XXXXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXX
      Uplink  6: XXXXXXXXXXXXXX_X_________________________________________________________XXXXXXX
      Uplink  7: XXXXXXXXXXXXXX_X_________________________________________________________XXXXXXX
      Uplink  8: X_____________________________________________________________________XXXXXXXXXX
      Uplink  9: X_____________________________________________________________________XXXXXXXXXX
      Uplink 10: X_______________________________________________________________________________
      Uplink 11: X_______________________________________________________________________________
      Uplink 12: XX______________________________________________________________________________
      Uplink 13: XX______________________________________________________________________________
      Uplink 14: XXXXXXXXXXXX____________________________________________________________XXXXXXXX
      Uplink 15: XXXXXXXXXXXX____________________________________________________________XXXXXXXX
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 23
      Window Length: 28
      Eye Window: XXXXXXXXXX____________________________XX
    Uplink 1:
      Optimal Phase: 18
      Window Length: 28
      Eye Window: XXXXX____________________________XXXXXXX
    Uplink 2:
      Optimal Phase: 26
      Window Length: 6
      Eye Window: XXXXXXXXXXXXXXXXXXXXXXXX______XXXXXXXXXX
    Uplink 3:
      Optimal Phase: 26
      Window Length: 6
      Eye Window: XXXXXXXXXXXXXXXXXXXXXXXX______XXXXXXXXXX
    Uplink 4:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 5:
      Optimal Phase: 11
      Window Length: 32
      Eye Window: ____________________________XXXXXXXX____
    Uplink 6:
      Optimal Phase: 6
      Window Length: 23
      Eye Window: __________________XXXXXXXXXXXXXXXXX_____
    Uplink 7:
      Optimal Phase: 3
      Window Length: 23
      Eye Window: _______________XXXXXXXXXXXXXXXXX________
    Uplink 8:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 9:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 10:
      Optimal Phase: 38
      Window Length: 31
      Eye Window: ______________XXXXXXXXX_________________
    Uplink 11:
      Optimal Phase: 0
      Window Length: 32
      Eye Window: _________________XXXXXXXX_______________
    Uplink 12:
      Optimal Phase: 30
      Window Length: 17
      Eye Window: __XXXXX______XXXXXXXXX_________________X
    Uplink 13:
      Optimal Phase: 31
      Window Length: 15
      Eye Window: __XXXXX_______XXXXXXXXXX_______________X
    Uplink 14:
      Optimal Phase: 37
      Window Length: 25
      Eye Window: __________XXXXXXXXXXXXXXX_______________
    Uplink 15:
      Optimal Phase: 39
      Window Length: 24
      Eye Window: ____________X_XXXXXXXXXXXXXX____________

==============================================OOO==============================================
14:14:21:setup_element:INFO:	Performing Elink synchronization
14:14:21:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:14:21:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:14:21:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:14:21:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
14:14:21:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
14:14:21:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:14:22:febtest:INFO:	Init all SMX (CSA): 30
14:14:37:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:14:37:febtest:INFO:	01-00 | XA-000-09-004-003-005-004-14 |  28.2 | 1183.3
14:14:37:febtest:INFO:	08-01 | XA-000-09-004-003-006-009-00 |  25.1 | 1195.1
14:14:38:febtest:INFO:	03-02 | XA-000-09-004-003-006-004-00 |  40.9 | 1141.9
14:14:38:febtest:INFO:	10-03 | XA-000-09-004-003-006-010-00 |  31.4 | 1165.6
14:14:38:febtest:INFO:	05-04 | XA-000-09-004-003-006-011-00 |  28.2 | 1183.3
14:14:38:febtest:INFO:	12-05 | XA-000-09-004-003-006-012-00 |  34.6 | 1153.7
14:14:39:febtest:INFO:	07-06 | XA-000-09-004-003-006-008-00 |  37.7 | 1147.8
14:14:39:febtest:INFO:	14-07 | XA-000-09-004-003-006-007-00 |  40.9 | 1135.9
14:14:40:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:14:42:ST3_smx:INFO:	chip: 1-0 	 31.389742 C 	 1195.082160 mV
14:14:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:42:ST3_smx:INFO:		Electrons
14:14:42:ST3_smx:INFO:	# loops 0
14:14:43:ST3_smx:INFO:	# loops 1
14:14:45:ST3_smx:INFO:	# loops 2
14:14:47:ST3_smx:INFO:	# loops 3
14:14:49:ST3_smx:INFO:	# loops 4
14:14:50:ST3_smx:INFO:	Total # of broken channels: 0
14:14:50:ST3_smx:INFO:	List of broken channels: []
14:14:50:ST3_smx:INFO:	Total # of broken channels: 0
14:14:50:ST3_smx:INFO:	List of broken channels: []
14:14:52:ST3_smx:INFO:	chip: 8-1 	 25.062742 C 	 1206.851500 mV
14:14:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:52:ST3_smx:INFO:		Electrons
14:14:52:ST3_smx:INFO:	# loops 0
14:14:54:ST3_smx:INFO:	# loops 1
14:14:55:ST3_smx:INFO:	# loops 2
14:14:57:ST3_smx:INFO:	# loops 3
14:14:59:ST3_smx:INFO:	# loops 4
14:15:00:ST3_smx:INFO:	Total # of broken channels: 0
14:15:00:ST3_smx:INFO:	List of broken channels: []
14:15:00:ST3_smx:INFO:	Total # of broken channels: 0
14:15:00:ST3_smx:INFO:	List of broken channels: []
14:15:02:ST3_smx:INFO:	chip: 3-2 	 40.898880 C 	 1153.732915 mV
14:15:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:02:ST3_smx:INFO:		Electrons
14:15:02:ST3_smx:INFO:	# loops 0
14:15:04:ST3_smx:INFO:	# loops 1
14:15:05:ST3_smx:INFO:	# loops 2
14:15:07:ST3_smx:INFO:	# loops 3
14:15:09:ST3_smx:INFO:	# loops 4
14:15:11:ST3_smx:INFO:	Total # of broken channels: 0
14:15:11:ST3_smx:INFO:	List of broken channels: []
14:15:11:ST3_smx:INFO:	Total # of broken channels: 1
14:15:11:ST3_smx:INFO:	List of broken channels: [123]
14:15:12:ST3_smx:INFO:	chip: 10-3 	 31.389742 C 	 1177.390875 mV
14:15:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:12:ST3_smx:INFO:		Electrons
14:15:12:ST3_smx:INFO:	# loops 0
14:15:14:ST3_smx:INFO:	# loops 1
14:15:16:ST3_smx:INFO:	# loops 2
14:15:17:ST3_smx:INFO:	# loops 3
14:15:19:ST3_smx:INFO:	# loops 4
14:15:21:ST3_smx:INFO:	Total # of broken channels: 1
14:15:21:ST3_smx:INFO:	List of broken channels: [90]
14:15:21:ST3_smx:INFO:	Total # of broken channels: 1
14:15:21:ST3_smx:INFO:	List of broken channels: [90]
14:15:22:ST3_smx:INFO:	chip: 5-4 	 31.389742 C 	 1195.082160 mV
14:15:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:22:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:22:ST3_smx:INFO:		Electrons
14:15:22:ST3_smx:INFO:	# loops 0
14:15:24:ST3_smx:INFO:	# loops 1
14:15:26:ST3_smx:INFO:	# loops 2
14:15:27:ST3_smx:INFO:	# loops 3
14:15:29:ST3_smx:INFO:	# loops 4
14:15:31:ST3_smx:INFO:	Total # of broken channels: 0
14:15:31:ST3_smx:INFO:	List of broken channels: []
14:15:31:ST3_smx:INFO:	Total # of broken channels: 1
14:15:31:ST3_smx:INFO:	List of broken channels: [47]
14:15:32:ST3_smx:INFO:	chip: 12-5 	 34.556970 C 	 1165.571835 mV
14:15:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:32:ST3_smx:INFO:		Electrons
14:15:32:ST3_smx:INFO:	# loops 0
14:15:34:ST3_smx:INFO:	# loops 1
14:15:36:ST3_smx:INFO:	# loops 2
14:15:37:ST3_smx:INFO:	# loops 3
14:15:39:ST3_smx:INFO:	# loops 4
14:15:40:ST3_smx:INFO:	Total # of broken channels: 0
14:15:40:ST3_smx:INFO:	List of broken channels: []
14:15:40:ST3_smx:INFO:	Total # of broken channels: 0
14:15:40:ST3_smx:INFO:	List of broken channels: []
14:15:42:ST3_smx:INFO:	chip: 7-6 	 37.726682 C 	 1159.654860 mV
14:15:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:42:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:42:ST3_smx:INFO:		Electrons
14:15:42:ST3_smx:INFO:	# loops 0
14:15:44:ST3_smx:INFO:	# loops 1
14:15:45:ST3_smx:INFO:	# loops 2
14:15:47:ST3_smx:INFO:	# loops 3
14:15:49:ST3_smx:INFO:	# loops 4
14:15:50:ST3_smx:INFO:	Total # of broken channels: 0
14:15:50:ST3_smx:INFO:	List of broken channels: []
14:15:50:ST3_smx:INFO:	Total # of broken channels: 0
14:15:50:ST3_smx:INFO:	List of broken channels: []
14:15:52:ST3_smx:INFO:	chip: 14-7 	 40.898880 C 	 1147.806000 mV
14:15:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:15:52:ST3_smx:INFO:		Electrons
14:15:52:ST3_smx:INFO:	# loops 0
14:15:53:ST3_smx:INFO:	# loops 1
14:15:55:ST3_smx:INFO:	# loops 2
14:15:57:ST3_smx:INFO:	# loops 3
14:15:58:ST3_smx:INFO:	# loops 4
14:16:00:ST3_smx:INFO:	Total # of broken channels: 0
14:16:00:ST3_smx:INFO:	List of broken channels: []
14:16:00:ST3_smx:INFO:	Total # of broken channels: 0
14:16:00:ST3_smx:INFO:	List of broken channels: []
14:16:00:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:16:00:febtest:INFO:	01-00 | XA-000-09-004-003-005-004-14 |  31.4 | 1212.7
14:16:01:febtest:INFO:	08-01 | XA-000-09-004-003-006-009-00 |  25.1 | 1230.3
14:16:01:febtest:INFO:	03-02 | XA-000-09-004-003-006-004-00 |  44.1 | 1177.4
14:16:01:febtest:INFO:	10-03 | XA-000-09-004-003-006-010-00 |  34.6 | 1201.0
14:16:01:febtest:INFO:	05-04 | XA-000-09-004-003-006-011-00 |  31.4 | 1212.7
14:16:02:febtest:INFO:	12-05 | XA-000-09-004-003-006-012-00 |  37.7 | 1189.2
14:16:02:febtest:INFO:	07-06 | XA-000-09-004-003-006-008-00 |  40.9 | 1177.4
14:16:02:febtest:INFO:	14-07 | XA-000-09-004-003-006-007-00 |  40.9 | 1171.5
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_11_19-14_13_49
OPERATOR  : Kerstin S.; Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1287| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 01062 | SIZE: 62x42 | GRADE: C
MODULE_NAME: M3DR4T1000131B2
LADDER_NAME: L3DR400013
------------------------------------------------------------
VI_before_Init : ['2.449', '1.5820', '1.849', '2.7410', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0550', '1.850', '2.5050', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9940', '1.850', '0.5281', '0.000', '0.0000', '0.000', '0.0000']
14:16:03:ST3_Shared:INFO:	Listo of operators:Kerstin S.;