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FEB_1288 21.11.24 08:27:17
Info
08:27:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:27:17:ST3_Shared:INFO: FEB-Sensor
08:27:17:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:27:21:ST3_Shared:INFO: STS mode selected
08:27:32:ST3_ModuleSelector:DEBUG: M3DR6T0000150B2
08:27:32:ST3_ModuleSelector:DEBUG: L3DR600015
08:27:32:ST3_ModuleSelector:DEBUG: 15103
08:27:32:ST3_ModuleSelector:DEBUG: 62x62
08:27:32:ST3_ModuleSelector:DEBUG: B
08:27:32:ST3_ModuleSelector:DEBUG: M3DR6T0000150B2
08:27:32:ST3_ModuleSelector:DEBUG: L3DR600015
08:27:32:ST3_ModuleSelector:DEBUG: 15103
08:27:32:ST3_ModuleSelector:DEBUG: 62x62
08:27:32:ST3_ModuleSelector:DEBUG: B
08:27:37:ST3_ModuleSelector:INFO: M3DR6T0000150B2
08:27:37:ST3_ModuleSelector:INFO: 15103
08:27:37:febtest:INFO: Testing FEB with SN 1288
08:27:39:smx_tester:INFO: Scanning setup
08:27:39:elinks:INFO: Disabling clock on downlink 0
08:27:39:elinks:INFO: Disabling clock on downlink 1
08:27:39:elinks:INFO: Disabling clock on downlink 2
08:27:39:elinks:INFO: Disabling clock on downlink 3
08:27:39:elinks:INFO: Disabling clock on downlink 4
08:27:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:27:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:27:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO: Disabling clock on downlink 0
08:27:39:elinks:INFO: Disabling clock on downlink 1
08:27:39:elinks:INFO: Disabling clock on downlink 2
08:27:39:elinks:INFO: Disabling clock on downlink 3
08:27:39:elinks:INFO: Disabling clock on downlink 4
08:27:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:27:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:27:39:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:27:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO: Disabling clock on downlink 0
08:27:39:elinks:INFO: Disabling clock on downlink 1
08:27:39:elinks:INFO: Disabling clock on downlink 2
08:27:39:elinks:INFO: Disabling clock on downlink 3
08:27:39:elinks:INFO: Disabling clock on downlink 4
08:27:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:27:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:27:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO: Disabling clock on downlink 0
08:27:39:elinks:INFO: Disabling clock on downlink 1
08:27:39:elinks:INFO: Disabling clock on downlink 2
08:27:39:elinks:INFO: Disabling clock on downlink 3
08:27:39:elinks:INFO: Disabling clock on downlink 4
08:27:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:27:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:27:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO: Disabling clock on downlink 0
08:27:39:elinks:INFO: Disabling clock on downlink 1
08:27:39:elinks:INFO: Disabling clock on downlink 2
08:27:39:elinks:INFO: Disabling clock on downlink 3
08:27:39:elinks:INFO: Disabling clock on downlink 4
08:27:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:27:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:27:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:27:39:setup_element:INFO: Scanning clock phase
08:27:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:27:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:27:40:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:27:40:setup_element:INFO: Eye window for uplink 0 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:27:40:setup_element:INFO: Eye window for uplink 1 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:27:40:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:27:40:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
08:27:40:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:27:40:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:27:40:setup_element:INFO: Eye window for uplink 6 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:27:40:setup_element:INFO: Eye window for uplink 7 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
08:27:40:setup_element:INFO: Eye window for uplink 8 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:27:40:setup_element:INFO: Eye window for uplink 9 : _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:27:40:setup_element:INFO: Eye window for uplink 10: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:27:40:setup_element:INFO: Eye window for uplink 11: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:27:40:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:27:40:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:27:40:setup_element:INFO: Eye window for uplink 14: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:27:40:setup_element:INFO: Eye window for uplink 15: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
08:27:40:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
08:27:40:setup_element:INFO: Scanning data phases
08:27:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:27:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:27:45:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:27:45:setup_element:INFO: Eye window for uplink 0 : _____________XXXXXXXX___________________
Data delay found: 36
08:27:45:setup_element:INFO: Eye window for uplink 1 : _________XXXXXX_________________________
Data delay found: 31
08:27:45:setup_element:INFO: Eye window for uplink 2 : _______XXXXXXX__________________________
Data delay found: 30
08:27:45:setup_element:INFO: Eye window for uplink 3 : ____XXXXXXXX____________________________
Data delay found: 27
08:27:45:setup_element:INFO: Eye window for uplink 4 : _____XXXXXXXX___________________________
Data delay found: 28
08:27:45:setup_element:INFO: Eye window for uplink 5 : _XXXXXXX________________________________
Data delay found: 24
08:27:45:setup_element:INFO: Eye window for uplink 6 : XXXXXX________________________________XX
Data delay found: 21
08:27:45:setup_element:INFO: Eye window for uplink 7 : XXX_______________________________XXXXXX
Data delay found: 18
08:27:45:setup_element:INFO: Eye window for uplink 8 : _______________________XXXXXX___________
Data delay found: 5
08:27:45:setup_element:INFO: Eye window for uplink 9 : ____________________________XXXXXXX_____
Data delay found: 11
08:27:45:setup_element:INFO: Eye window for uplink 10: ________________________XXXXXXXX________
Data delay found: 7
08:27:45:setup_element:INFO: Eye window for uplink 11: ____________________________X_XXXXXX____
Data delay found: 11
08:27:45:setup_element:INFO: Eye window for uplink 12: ______________________________XXXXXXX___
Data delay found: 13
08:27:45:setup_element:INFO: Eye window for uplink 13: XX_______________________________XXXXXXX
Data delay found: 17
08:27:45:setup_element:INFO: Eye window for uplink 14: _____________________________XXXXXXXX___
Data delay found: 12
08:27:45:setup_element:INFO: Eye window for uplink 15: X______________________________XXXXXXXXX
Data delay found: 15
08:27:45:setup_element:INFO: Setting the data phase to 36 for uplink 0
08:27:45:setup_element:INFO: Setting the data phase to 31 for uplink 1
08:27:45:setup_element:INFO: Setting the data phase to 30 for uplink 2
08:27:45:setup_element:INFO: Setting the data phase to 27 for uplink 3
08:27:45:setup_element:INFO: Setting the data phase to 28 for uplink 4
08:27:45:setup_element:INFO: Setting the data phase to 24 for uplink 5
08:27:45:setup_element:INFO: Setting the data phase to 21 for uplink 6
08:27:45:setup_element:INFO: Setting the data phase to 18 for uplink 7
08:27:45:setup_element:INFO: Setting the data phase to 5 for uplink 8
08:27:45:setup_element:INFO: Setting the data phase to 11 for uplink 9
08:27:45:setup_element:INFO: Setting the data phase to 7 for uplink 10
08:27:45:setup_element:INFO: Setting the data phase to 11 for uplink 11
08:27:45:setup_element:INFO: Setting the data phase to 13 for uplink 12
08:27:45:setup_element:INFO: Setting the data phase to 17 for uplink 13
08:27:45:setup_element:INFO: Setting the data phase to 12 for uplink 14
08:27:45:setup_element:INFO: Setting the data phase to 15 for uplink 15
==============================================OOO==============================================
08:27:45:setup_element:INFO: Beginning SMX ASICs map scan
08:27:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:27:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:27:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:27:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:27:45:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:27:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:27:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:27:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:27:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:27:45:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:27:45:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:27:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:27:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:27:45:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:27:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:27:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:27:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:27:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:27:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:27:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:27:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:27:47:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 68
Eye Windows:
Uplink 0: ________________________________________________________________________XXXXXXXX
Uplink 1: ________________________________________________________________________XXXXXXXX
Uplink 2: _______________________________________________________________________XXXXXXX__
Uplink 3: _______________________________________________________________________XXXXXXX__
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ________________________________________________________________________XXXXXXX_
Uplink 7: ________________________________________________________________________XXXXXXX_
Uplink 8: _____________________________________________________________________XXXXXXXX___
Uplink 9: _____________________________________________________________________XXXXXXXX___
Uplink 10: ____________________________________________________________________XXXXXXXXX___
Uplink 11: ____________________________________________________________________XXXXXXXXX___
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: ________________________________________________________________________XXXXXXXX
Uplink 15: ________________________________________________________________________XXXXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 36
Window Length: 32
Eye Window: _____________XXXXXXXX___________________
Uplink 1:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 2:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 3:
Optimal Phase: 27
Window Length: 32
Eye Window: ____XXXXXXXX____________________________
Uplink 4:
Optimal Phase: 28
Window Length: 32
Eye Window: _____XXXXXXXX___________________________
Uplink 5:
Optimal Phase: 24
Window Length: 33
Eye Window: _XXXXXXX________________________________
Uplink 6:
Optimal Phase: 21
Window Length: 32
Eye Window: XXXXXX________________________________XX
Uplink 7:
Optimal Phase: 18
Window Length: 31
Eye Window: XXX_______________________________XXXXXX
Uplink 8:
Optimal Phase: 5
Window Length: 34
Eye Window: _______________________XXXXXX___________
Uplink 9:
Optimal Phase: 11
Window Length: 33
Eye Window: ____________________________XXXXXXX_____
Uplink 10:
Optimal Phase: 7
Window Length: 32
Eye Window: ________________________XXXXXXXX________
Uplink 11:
Optimal Phase: 11
Window Length: 32
Eye Window: ____________________________X_XXXXXX____
Uplink 12:
Optimal Phase: 13
Window Length: 33
Eye Window: ______________________________XXXXXXX___
Uplink 13:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXXX
Uplink 14:
Optimal Phase: 12
Window Length: 32
Eye Window: _____________________________XXXXXXXX___
Uplink 15:
Optimal Phase: 15
Window Length: 30
Eye Window: X______________________________XXXXXXXXX
==============================================OOO==============================================
08:27:47:setup_element:INFO: Performing Elink synchronization
08:27:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:27:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:27:47:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:27:47:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
08:27:47:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:27:47:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
08:27:48:febtest:INFO: Init all SMX (CSA): 30
08:28:03:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:28:03:febtest:INFO: 01-00 | XA-000-09-004-002-015-010-09 | 34.6 | 1159.7
08:28:03:febtest:INFO: 08-01 | XA-000-09-004-002-015-021-14 | 21.9 | 1201.0
08:28:03:febtest:INFO: 03-02 | XA-000-09-004-002-015-006-09 | 21.9 | 1224.5
08:28:03:febtest:INFO: 10-03 | XA-000-09-004-012-013-006-07 | 25.1 | 1189.2
08:28:04:febtest:INFO: 05-04 | XA-000-09-004-002-014-011-04 | 31.4 | 1171.5
08:28:04:febtest:INFO: 12-05 | XA-000-09-004-012-017-008-01 | 28.2 | 1201.0
08:28:04:febtest:INFO: 07-06 | XA-000-09-004-002-014-019-03 | 12.4 | 1242.0
08:28:04:febtest:INFO: 14-07 | XA-000-09-004-012-016-008-12 | 31.4 | 1165.6
08:28:05:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:28:07:ST3_smx:INFO: chip: 1-0 34.556970 C 1171.483840 mV
08:28:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:07:ST3_smx:INFO: Electrons
08:28:07:ST3_smx:INFO: # loops 0
08:28:09:ST3_smx:INFO: # loops 1
08:28:11:ST3_smx:INFO: # loops 2
08:28:12:ST3_smx:INFO: # loops 3
08:28:14:ST3_smx:INFO: # loops 4
08:28:16:ST3_smx:INFO: Total # of broken channels: 0
08:28:16:ST3_smx:INFO: List of broken channels: []
08:28:16:ST3_smx:INFO: Total # of broken channels: 0
08:28:16:ST3_smx:INFO: List of broken channels: []
08:28:17:ST3_smx:INFO: chip: 8-1 21.902970 C 1212.728715 mV
08:28:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:17:ST3_smx:INFO: Electrons
08:28:17:ST3_smx:INFO: # loops 0
08:28:19:ST3_smx:INFO: # loops 1
08:28:21:ST3_smx:INFO: # loops 2
08:28:22:ST3_smx:INFO: # loops 3
08:28:24:ST3_smx:INFO: # loops 4
08:28:26:ST3_smx:INFO: Total # of broken channels: 1
08:28:26:ST3_smx:INFO: List of broken channels: [0]
08:28:26:ST3_smx:INFO: Total # of broken channels: 1
08:28:26:ST3_smx:INFO: List of broken channels: [0]
08:28:27:ST3_smx:INFO: chip: 3-2 21.902970 C 1242.040240 mV
08:28:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:27:ST3_smx:INFO: Electrons
08:28:27:ST3_smx:INFO: # loops 0
08:28:29:ST3_smx:INFO: # loops 1
08:28:31:ST3_smx:INFO: # loops 2
08:28:32:ST3_smx:INFO: # loops 3
08:28:34:ST3_smx:INFO: # loops 4
08:28:35:ST3_smx:INFO: Total # of broken channels: 0
08:28:35:ST3_smx:INFO: List of broken channels: []
08:28:35:ST3_smx:INFO: Total # of broken channels: 0
08:28:35:ST3_smx:INFO: List of broken channels: []
08:28:37:ST3_smx:INFO: chip: 10-3 25.062742 C 1200.969315 mV
08:28:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:37:ST3_smx:INFO: Electrons
08:28:37:ST3_smx:INFO: # loops 0
08:28:39:ST3_smx:INFO: # loops 1
08:28:40:ST3_smx:INFO: # loops 2
08:28:42:ST3_smx:INFO: # loops 3
08:28:44:ST3_smx:INFO: # loops 4
08:28:45:ST3_smx:INFO: Total # of broken channels: 0
08:28:45:ST3_smx:INFO: List of broken channels: []
08:28:45:ST3_smx:INFO: Total # of broken channels: 0
08:28:45:ST3_smx:INFO: List of broken channels: []
08:28:47:ST3_smx:INFO: chip: 5-4 31.389742 C 1183.292940 mV
08:28:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:47:ST3_smx:INFO: Electrons
08:28:47:ST3_smx:INFO: # loops 0
08:28:49:ST3_smx:INFO: # loops 1
08:28:50:ST3_smx:INFO: # loops 2
08:28:52:ST3_smx:INFO: # loops 3
08:28:54:ST3_smx:INFO: # loops 4
08:28:55:ST3_smx:INFO: Total # of broken channels: 0
08:28:55:ST3_smx:INFO: List of broken channels: []
08:28:55:ST3_smx:INFO: Total # of broken channels: 0
08:28:55:ST3_smx:INFO: List of broken channels: []
08:28:57:ST3_smx:INFO: chip: 12-5 28.225000 C 1236.187875 mV
08:28:57:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:57:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:28:57:ST3_smx:INFO: Electrons
08:28:57:ST3_smx:INFO: # loops 0
08:28:59:ST3_smx:INFO: # loops 1
08:29:00:ST3_smx:INFO: # loops 2
08:29:02:ST3_smx:INFO: # loops 3
08:29:03:ST3_smx:INFO: # loops 4
08:29:05:ST3_smx:INFO: Total # of broken channels: 1
08:29:05:ST3_smx:INFO: List of broken channels: [34]
08:29:05:ST3_smx:INFO: Total # of broken channels: 1
08:29:05:ST3_smx:INFO: List of broken channels: [34]
08:29:07:ST3_smx:INFO: chip: 7-6 15.590880 C 1253.730060 mV
08:29:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:07:ST3_smx:INFO: Electrons
08:29:07:ST3_smx:INFO: # loops 0
08:29:08:ST3_smx:INFO: # loops 1
08:29:10:ST3_smx:INFO: # loops 2
08:29:12:ST3_smx:INFO: # loops 3
08:29:13:ST3_smx:INFO: # loops 4
08:29:15:ST3_smx:INFO: Total # of broken channels: 0
08:29:15:ST3_smx:INFO: List of broken channels: []
08:29:15:ST3_smx:INFO: Total # of broken channels: 0
08:29:15:ST3_smx:INFO: List of broken channels: []
08:29:17:ST3_smx:INFO: chip: 14-7 31.389742 C 1171.483840 mV
08:29:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:29:17:ST3_smx:INFO: Electrons
08:29:17:ST3_smx:INFO: # loops 0
08:29:18:ST3_smx:INFO: # loops 1
08:29:20:ST3_smx:INFO: # loops 2
08:29:22:ST3_smx:INFO: # loops 3
08:29:23:ST3_smx:INFO: # loops 4
08:29:25:ST3_smx:INFO: Total # of broken channels: 0
08:29:25:ST3_smx:INFO: List of broken channels: []
08:29:25:ST3_smx:INFO: Total # of broken channels: 0
08:29:25:ST3_smx:INFO: List of broken channels: []
08:29:25:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:29:25:febtest:INFO: 01-00 | XA-000-09-004-002-015-010-09 | 37.7 | 1195.1
08:29:26:febtest:INFO: 08-01 | XA-000-09-004-002-015-021-14 | 21.9 | 1236.2
08:29:26:febtest:INFO: 03-02 | XA-000-09-004-002-015-006-09 | 21.9 | 1282.9
08:29:26:febtest:INFO: 10-03 | XA-000-09-004-012-013-006-07 | 28.2 | 1230.3
08:29:26:febtest:INFO: 05-04 | XA-000-09-004-002-014-011-04 | 34.6 | 1206.9
08:29:27:febtest:INFO: 12-05 | XA-000-09-004-012-017-008-01 | 28.2 | 1578.5
08:29:27:febtest:INFO: 07-06 | XA-000-09-004-002-014-019-03 | 15.6 | 1277.1
08:29:27:febtest:INFO: 14-07 | XA-000-09-004-012-016-008-12 | 34.6 | 1195.1
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_11_21-08_27_17
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1288| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 15103 | SIZE: 62x62 | GRADE: B
MODULE_NAME: M3DR6T0000150B2
LADDER_NAME: L3DR600015
------------------------------------------------------------
VI_before_Init : ['2.449', '1.4030', '1.849', '2.2590', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9770', '1.850', '2.3260', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9510', '1.850', '0.5234', '0.000', '0.0000', '0.000', '0.0000']