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FEB_1295 19.11.24 14:42:52
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14:42:52:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:42:52:ST3_Shared:INFO: FEB-ASIC
14:42:52:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:42:52:febtest:INFO: Testing FEB with SN 1295
14:42:54:smx_tester:INFO: Scanning setup
14:42:54:elinks:INFO: Disabling clock on downlink 0
14:42:54:elinks:INFO: Disabling clock on downlink 1
14:42:54:elinks:INFO: Disabling clock on downlink 2
14:42:54:elinks:INFO: Disabling clock on downlink 3
14:42:54:elinks:INFO: Disabling clock on downlink 4
14:42:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:42:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:42:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:42:54:elinks:INFO: Disabling clock on downlink 0
14:42:54:elinks:INFO: Disabling clock on downlink 1
14:42:54:elinks:INFO: Disabling clock on downlink 2
14:42:54:elinks:INFO: Disabling clock on downlink 3
14:42:54:elinks:INFO: Disabling clock on downlink 4
14:42:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:42:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
14:42:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
14:42:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:42:54:elinks:INFO: Disabling clock on downlink 0
14:42:54:elinks:INFO: Disabling clock on downlink 1
14:42:54:elinks:INFO: Disabling clock on downlink 2
14:42:54:elinks:INFO: Disabling clock on downlink 3
14:42:54:elinks:INFO: Disabling clock on downlink 4
14:42:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:42:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:42:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:42:55:elinks:INFO: Disabling clock on downlink 0
14:42:55:elinks:INFO: Disabling clock on downlink 1
14:42:55:elinks:INFO: Disabling clock on downlink 2
14:42:55:elinks:INFO: Disabling clock on downlink 3
14:42:55:elinks:INFO: Disabling clock on downlink 4
14:42:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:42:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:42:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:42:55:elinks:INFO: Disabling clock on downlink 0
14:42:55:elinks:INFO: Disabling clock on downlink 1
14:42:55:elinks:INFO: Disabling clock on downlink 2
14:42:55:elinks:INFO: Disabling clock on downlink 3
14:42:55:elinks:INFO: Disabling clock on downlink 4
14:42:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:42:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:42:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:42:55:setup_element:INFO: Scanning clock phase
14:42:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:42:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:42:55:setup_element:INFO: Clock phase scan results for group 0, downlink 1
14:42:55:setup_element:INFO: Eye window for uplink 2 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:42:55:setup_element:INFO: Eye window for uplink 3 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:42:55:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:42:55:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:42:55:setup_element:INFO: Eye window for uplink 6 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:42:55:setup_element:INFO: Eye window for uplink 7 : ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
14:42:55:setup_element:INFO: Eye window for uplink 8 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:42:55:setup_element:INFO: Eye window for uplink 9 : ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:42:55:setup_element:INFO: Eye window for uplink 10: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
14:42:55:setup_element:INFO: Eye window for uplink 11: _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
14:42:55:setup_element:INFO: Eye window for uplink 12: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:42:55:setup_element:INFO: Eye window for uplink 13: _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
14:42:55:setup_element:INFO: Eye window for uplink 14: _________________________________________________________________________XXXXXXX
Clock Delay: 36
14:42:55:setup_element:INFO: Eye window for uplink 15: _________________________________________________________________________XXXXXXX
Clock Delay: 36
14:42:55:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 1
==============================================OOO==============================================
14:42:55:setup_element:INFO: Scanning data phases
14:42:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:42:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:43:00:setup_element:INFO: Data phase scan results for group 0, downlink 1
14:43:00:setup_element:INFO: Eye window for uplink 2 : _____XXXXXXXXXX_________________________
Data delay found: 29
14:43:00:setup_element:INFO: Eye window for uplink 3 : ___XXXXXXXXX____________________________
Data delay found: 27
14:43:00:setup_element:INFO: Eye window for uplink 4 : ________XXXXXXX_____XXXXXXXXXXXXXXXXXXXX
Data delay found: 3
14:43:00:setup_element:INFO: Eye window for uplink 5 : ____XXXXXXX_________XXXXXXXXXXXXXXXXXXXX
Data delay found: 15
14:43:00:setup_element:INFO: Eye window for uplink 6 : XXXXXX_________________________________X
Data delay found: 22
14:43:00:setup_element:INFO: Eye window for uplink 7 : XXXX________________________________XXXX
Data delay found: 19
14:43:00:setup_element:INFO: Eye window for uplink 8 : __________________________XXXXX_________
Data delay found: 8
14:43:00:setup_element:INFO: Eye window for uplink 9 : _______________________________XXXXXX___
Data delay found: 13
14:43:00:setup_element:INFO: Eye window for uplink 10: _____________________________XXXXXXXXXX_
Data delay found: 13
14:43:00:setup_element:INFO: Eye window for uplink 11: XXX_______________________________XXXXXX
Data delay found: 18
14:43:00:setup_element:INFO: Eye window for uplink 12: ____________________________XXXXXXXXX___
Data delay found: 12
14:43:00:setup_element:INFO: Eye window for uplink 13: _X____________________________XXXXXXXXXX
Data delay found: 15
14:43:00:setup_element:INFO: Eye window for uplink 14: _______________________________XXXXXXXX_
Data delay found: 14
14:43:00:setup_element:INFO: Eye window for uplink 15: XXXX____________________________XXXXXXXX
Data delay found: 17
14:43:00:setup_element:INFO: Setting the data phase to 29 for uplink 2
14:43:00:setup_element:INFO: Setting the data phase to 27 for uplink 3
14:43:00:setup_element:INFO: Setting the data phase to 3 for uplink 4
14:43:00:setup_element:INFO: Setting the data phase to 15 for uplink 5
14:43:00:setup_element:INFO: Setting the data phase to 22 for uplink 6
14:43:00:setup_element:INFO: Setting the data phase to 19 for uplink 7
14:43:00:setup_element:INFO: Setting the data phase to 8 for uplink 8
14:43:00:setup_element:INFO: Setting the data phase to 13 for uplink 9
14:43:00:setup_element:INFO: Setting the data phase to 13 for uplink 10
14:43:00:setup_element:INFO: Setting the data phase to 18 for uplink 11
14:43:00:setup_element:INFO: Setting the data phase to 12 for uplink 12
14:43:00:setup_element:INFO: Setting the data phase to 15 for uplink 13
14:43:00:setup_element:INFO: Setting the data phase to 14 for uplink 14
14:43:00:setup_element:INFO: Setting the data phase to 17 for uplink 15
==============================================OOO==============================================
14:43:00:setup_element:INFO: Beginning SMX ASICs map scan
14:43:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:43:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:43:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:43:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
14:43:00:uplink:INFO: Setting uplinks mask [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:43:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:43:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:43:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:43:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:43:01:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:43:01:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:43:01:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:43:01:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:43:01:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:43:01:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:43:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:43:02:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:43:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:43:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:43:03:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 68
Eye Windows:
Uplink 2: _______________________________________________________________________XXXXXXXX_
Uplink 3: _______________________________________________________________________XXXXXXXX_
Uplink 4: _______________________________________________________________________XXXXXXXX_
Uplink 5: _______________________________________________________________________XXXXXXXX_
Uplink 6: ______________________________________________________________________XXXXXXXX__
Uplink 7: ______________________________________________________________________XXXXXXXX__
Uplink 8: ____________________________________________________________________XXXXXXXXX___
Uplink 9: ____________________________________________________________________XXXXXXXXX___
Uplink 10: _______________________________________________________________________XXXXXXXXX
Uplink 11: _______________________________________________________________________XXXXXXXXX
Uplink 12: _______________________________________________________________________XXXXXXXX_
Uplink 13: _______________________________________________________________________XXXXXXXX_
Uplink 14: _________________________________________________________________________XXXXXXX
Uplink 15: _________________________________________________________________________XXXXXXX
Data phase characteristics:
Uplink 2:
Optimal Phase: 29
Window Length: 30
Eye Window: _____XXXXXXXXXX_________________________
Uplink 3:
Optimal Phase: 27
Window Length: 31
Eye Window: ___XXXXXXXXX____________________________
Uplink 4:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXX_____XXXXXXXXXXXXXXXXXXXX
Uplink 5:
Optimal Phase: 15
Window Length: 9
Eye Window: ____XXXXXXX_________XXXXXXXXXXXXXXXXXXXX
Uplink 6:
Optimal Phase: 22
Window Length: 33
Eye Window: XXXXXX_________________________________X
Uplink 7:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
Uplink 8:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 9:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 10:
Optimal Phase: 13
Window Length: 30
Eye Window: _____________________________XXXXXXXXXX_
Uplink 11:
Optimal Phase: 18
Window Length: 31
Eye Window: XXX_______________________________XXXXXX
Uplink 12:
Optimal Phase: 12
Window Length: 31
Eye Window: ____________________________XXXXXXXXX___
Uplink 13:
Optimal Phase: 15
Window Length: 28
Eye Window: _X____________________________XXXXXXXXXX
Uplink 14:
Optimal Phase: 14
Window Length: 32
Eye Window: _______________________________XXXXXXXX_
Uplink 15:
Optimal Phase: 17
Window Length: 28
Eye Window: XXXX____________________________XXXXXXXX
==============================================OOO==============================================
14:43:03:setup_element:INFO: Performing Elink synchronization
14:43:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:43:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:43:03:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:43:03:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
14:43:03:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
14:43:03:uplink:INFO: Enabling uplinks [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_8 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_1__upli_8
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5_12 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5_12 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_5__upli_12
14:43:04:febtest:INFO: Init all SMX (CSA): 30
14:43:17:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:43:17:febtest:INFO: 08-01 | XA-000-09-004-008-006-011-14 | 40.9 | 1171.5
14:43:17:febtest:INFO: 03-02 | XA-000-09-004-008-003-018-02 | 31.4 | 1230.3
14:43:17:febtest:INFO: 10-03 | XA-000-09-004-008-017-022-13 | 21.9 | 1212.7
14:43:18:febtest:INFO: 05-04 | XA-000-09-004-008-017-019-13 | 18.7 | 1242.0
14:43:18:febtest:INFO: 12-05 | XA-000-09-004-008-011-027-14 | 21.9 | 1224.5
14:43:18:febtest:INFO: 07-06 | XA-000-09-004-008-008-007-07 | 25.1 | 1218.6
14:43:18:febtest:INFO: 14-07 | XA-000-09-004-008-018-017-03 | 28.2 | 1201.0
14:43:19:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:43:20:febtest:ERROR: HW addres 1 != 0
14:43:28:ST3_smx:INFO: chip: 8-1 40.898880 C 1177.390875 mV
14:43:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:28:ST3_smx:INFO: Electrons
14:43:28:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:30:ST3_smx:INFO: ----> Checking Analog response
14:43:30:ST3_smx:INFO: ----> Checking broken channels
14:43:31:ST3_smx:INFO: Total # broken ch: 2
14:43:31:ST3_smx:INFO: List FAST: [64]
14:43:31:ST3_smx:INFO: List SLOW: [64]
14:43:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:31:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:31:ST3_smx:INFO: Holes
14:43:31:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:33:ST3_smx:INFO: ----> Checking Analog response
14:43:33:ST3_smx:INFO: ----> Checking broken channels
14:43:33:ST3_smx:INFO: Total # broken ch: 2
14:43:33:ST3_smx:INFO: List FAST: [64]
14:43:33:ST3_smx:INFO: List SLOW: [64]
14:43:35:ST3_smx:INFO: chip: 3-2 34.556970 C 1230.330540 mV
14:43:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:35:ST3_smx:INFO: Electrons
14:43:35:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:37:ST3_smx:INFO: ----> Checking Analog response
14:43:37:ST3_smx:INFO: ----> Checking broken channels
14:43:37:ST3_smx:INFO: Total # broken ch: 0
14:43:37:ST3_smx:INFO: List FAST: []
14:43:37:ST3_smx:INFO: List SLOW: []
14:43:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:37:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:37:ST3_smx:INFO: Holes
14:43:37:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:40:ST3_smx:INFO: ----> Checking Analog response
14:43:40:ST3_smx:INFO: ----> Checking broken channels
14:43:40:ST3_smx:INFO: Total # broken ch: 0
14:43:40:ST3_smx:INFO: List FAST: []
14:43:40:ST3_smx:INFO: List SLOW: []
14:43:41:ST3_smx:INFO: chip: 10-3 25.062742 C 1218.600960 mV
14:43:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:41:ST3_smx:INFO: Electrons
14:43:41:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:43:ST3_smx:INFO: ----> Checking Analog response
14:43:43:ST3_smx:INFO: ----> Checking broken channels
14:43:44:ST3_smx:INFO: Total # broken ch: 0
14:43:44:ST3_smx:INFO: List FAST: []
14:43:44:ST3_smx:INFO: List SLOW: []
14:43:44:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:44:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:44:ST3_smx:INFO: Holes
14:43:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:46:ST3_smx:INFO: ----> Checking Analog response
14:43:46:ST3_smx:INFO: ----> Checking broken channels
14:43:46:ST3_smx:INFO: Total # broken ch: 0
14:43:46:ST3_smx:INFO: List FAST: []
14:43:46:ST3_smx:INFO: List SLOW: []
14:43:48:ST3_smx:INFO: chip: 5-4 18.745682 C 1236.187875 mV
14:43:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:48:ST3_smx:INFO: Electrons
14:43:48:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:50:ST3_smx:INFO: ----> Checking Analog response
14:43:50:ST3_smx:INFO: ----> Checking broken channels
14:43:50:ST3_smx:INFO: Total # broken ch: 0
14:43:50:ST3_smx:INFO: List FAST: []
14:43:50:ST3_smx:INFO: List SLOW: []
14:43:50:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:50:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:50:ST3_smx:INFO: Holes
14:43:50:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:52:ST3_smx:INFO: ----> Checking Analog response
14:43:52:ST3_smx:INFO: ----> Checking broken channels
14:43:53:ST3_smx:INFO: Total # broken ch: 0
14:43:53:ST3_smx:INFO: List FAST: []
14:43:53:ST3_smx:INFO: List SLOW: []
14:43:54:ST3_smx:INFO: chip: 12-5 21.902970 C 1224.468235 mV
14:43:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:54:ST3_smx:INFO: Electrons
14:43:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:56:ST3_smx:INFO: ----> Checking Analog response
14:43:56:ST3_smx:INFO: ----> Checking broken channels
14:43:56:ST3_smx:INFO: Total # broken ch: 0
14:43:56:ST3_smx:INFO: List FAST: []
14:43:56:ST3_smx:INFO: List SLOW: []
14:43:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:43:56:ST3_smx:INFO: Holes
14:43:56:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:43:59:ST3_smx:INFO: ----> Checking Analog response
14:43:59:ST3_smx:INFO: ----> Checking broken channels
14:43:59:ST3_smx:INFO: Total # broken ch: 0
14:43:59:ST3_smx:INFO: List FAST: []
14:43:59:ST3_smx:INFO: List SLOW: []
14:44:00:ST3_smx:INFO: chip: 7-6 31.389742 C 1206.851500 mV
14:44:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:00:ST3_smx:INFO: Electrons
14:44:00:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:44:03:ST3_smx:INFO: ----> Checking Analog response
14:44:03:ST3_smx:INFO: ----> Checking broken channels
14:44:03:ST3_smx:INFO: Total # broken ch: 0
14:44:03:ST3_smx:INFO: List FAST: []
14:44:03:ST3_smx:INFO: List SLOW: []
14:44:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:03:ST3_smx:INFO: Holes
14:44:03:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:44:05:ST3_smx:INFO: ----> Checking Analog response
14:44:05:ST3_smx:INFO: ----> Checking broken channels
14:44:06:ST3_smx:INFO: Total # broken ch: 0
14:44:06:ST3_smx:INFO: List FAST: []
14:44:06:ST3_smx:INFO: List SLOW: []
14:44:07:ST3_smx:INFO: chip: 14-7 31.389742 C 1195.082160 mV
14:44:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:07:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:07:ST3_smx:INFO: Electrons
14:44:07:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:44:09:ST3_smx:INFO: ----> Checking Analog response
14:44:09:ST3_smx:INFO: ----> Checking broken channels
14:44:09:ST3_smx:INFO: Total # broken ch: 0
14:44:09:ST3_smx:INFO: List FAST: []
14:44:09:ST3_smx:INFO: List SLOW: []
14:44:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:44:09:ST3_smx:INFO: Holes
14:44:09:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:44:12:ST3_smx:INFO: ----> Checking Analog response
14:44:12:ST3_smx:INFO: ----> Checking broken channels
14:44:12:ST3_smx:INFO: Total # broken ch: 0
14:44:12:ST3_smx:INFO: List FAST: []
14:44:12:ST3_smx:INFO: List SLOW: []
14:44:12:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:44:12:febtest:INFO: 08-01 | XA-000-09-004-008-006-011-14 | 47.3 | 1189.2
14:44:12:febtest:INFO: 03-02 | XA-000-09-004-008-003-018-02 | 34.6 | 1265.4
14:44:13:febtest:INFO: 10-03 | XA-000-09-004-008-017-022-13 | 28.2 | 1224.5
14:44:13:febtest:INFO: 05-04 | XA-000-09-004-008-017-019-13 | 25.1 | 1247.9
14:44:13:febtest:INFO: 12-05 | XA-000-09-004-008-011-027-14 | 25.1 | 1242.0
14:44:13:febtest:INFO: 07-06 | XA-000-09-004-008-008-007-07 | 34.6 | 1218.6
14:44:14:febtest:INFO: 14-07 | XA-000-09-004-008-018-017-03 | 34.6 | 1206.9
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_11_19-14_42_52
OPERATOR : Robert V.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1295| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
MODULE_NAMEM3DR4T0000130B2
------------------------------------------------------------
VI_before_Init : ['2.449', '2.4120', '1.850', '1.3060', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.4450', '1.850', '1.9700', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '2.2920', '1.850', '0.4489', '0.000', '0.0000', '0.000', '0.0000']