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FEB_1302 12.12.24 08:34:39
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08:34:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:34:39:ST3_Shared:INFO: FEB-Sensor
08:34:39:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:34:41:ST3_Shared:INFO: STS mode selected
08:34:43:ST3_ModuleSelector:DEBUG: M4UR1T1011311A2
08:34:43:ST3_ModuleSelector:DEBUG: L4UR101131
08:34:43:ST3_ModuleSelector:DEBUG: 15052
08:34:43:ST3_ModuleSelector:DEBUG: 62x42
08:34:43:ST3_ModuleSelector:DEBUG: A
08:34:43:ST3_ModuleSelector:DEBUG: M4UR1T1011311A2
08:34:43:ST3_ModuleSelector:DEBUG: L4UR101131
08:34:43:ST3_ModuleSelector:DEBUG: 15052
08:34:43:ST3_ModuleSelector:DEBUG: 62x42
08:34:43:ST3_ModuleSelector:DEBUG: A
08:34:45:ST3_ModuleSelector:INFO: M4UR1T1011311A2
08:34:45:ST3_ModuleSelector:INFO: 15052
08:34:45:febtest:INFO: Testing FEB with SN 1302
08:34:47:smx_tester:INFO: Scanning setup
08:34:47:elinks:INFO: Disabling clock on downlink 0
08:34:47:elinks:INFO: Disabling clock on downlink 1
08:34:47:elinks:INFO: Disabling clock on downlink 2
08:34:47:elinks:INFO: Disabling clock on downlink 3
08:34:47:elinks:INFO: Disabling clock on downlink 4
08:34:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:34:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:34:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:34:47:elinks:INFO: Disabling clock on downlink 0
08:34:47:elinks:INFO: Disabling clock on downlink 1
08:34:47:elinks:INFO: Disabling clock on downlink 2
08:34:47:elinks:INFO: Disabling clock on downlink 3
08:34:47:elinks:INFO: Disabling clock on downlink 4
08:34:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:34:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:34:47:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:34:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:34:47:elinks:INFO: Disabling clock on downlink 0
08:34:47:elinks:INFO: Disabling clock on downlink 1
08:34:47:elinks:INFO: Disabling clock on downlink 2
08:34:47:elinks:INFO: Disabling clock on downlink 3
08:34:47:elinks:INFO: Disabling clock on downlink 4
08:34:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:34:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:34:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:34:47:elinks:INFO: Disabling clock on downlink 0
08:34:47:elinks:INFO: Disabling clock on downlink 1
08:34:47:elinks:INFO: Disabling clock on downlink 2
08:34:47:elinks:INFO: Disabling clock on downlink 3
08:34:47:elinks:INFO: Disabling clock on downlink 4
08:34:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:34:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:34:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:34:48:elinks:INFO: Disabling clock on downlink 0
08:34:48:elinks:INFO: Disabling clock on downlink 1
08:34:48:elinks:INFO: Disabling clock on downlink 2
08:34:48:elinks:INFO: Disabling clock on downlink 3
08:34:48:elinks:INFO: Disabling clock on downlink 4
08:34:48:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:34:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:34:48:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:34:48:setup_element:INFO: Scanning clock phase
08:34:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:34:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:34:48:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:34:48:setup_element:INFO: Eye window for uplink 0 : XXXXXXXXXXXXXXXXXXXXXXX__________________________________________________XXXXXXX
Clock Delay: 47
08:34:48:setup_element:INFO: Eye window for uplink 1 : XXXXXXXXXXXXXXXXXXXXXXX__________________________________________________XXXXXXX
Clock Delay: 47
08:34:48:setup_element:INFO: Eye window for uplink 2 : XX____________________________________________________________________XXXXXXXXXX
Clock Delay: 35
08:34:48:setup_element:INFO: Eye window for uplink 3 : XX____________________________________________________________________XXXXXXXXXX
Clock Delay: 35
08:34:48:setup_element:INFO: Eye window for uplink 4 : XXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXXXX
Clock Delay: 43
08:34:48:setup_element:INFO: Eye window for uplink 5 : XXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXXXX
Clock Delay: 43
08:34:48:setup_element:INFO: Eye window for uplink 6 : XXXXXXXXXXXXXXXXX________________________________________________________XXXXXXX
Clock Delay: 44
08:34:48:setup_element:INFO: Eye window for uplink 7 : XXXXXXXXXXXXXXXXX________________________________________________________XXXXXXX
Clock Delay: 44
08:34:48:setup_element:INFO: Eye window for uplink 8 : XXXXXXX_______________________________________________________________XXXXXXXXXX
Clock Delay: 38
08:34:48:setup_element:INFO: Eye window for uplink 9 : XXXXXXX_______________________________________________________________XXXXXXXXXX
Clock Delay: 38
08:34:48:setup_element:INFO: Eye window for uplink 10: XXXXXXX_X_____________________________________________________________XXXXXXXXXX
Clock Delay: 39
08:34:48:setup_element:INFO: Eye window for uplink 11: XXXXXXX_X_____________________________________________________________XXXXXXXXXX
Clock Delay: 39
08:34:48:setup_element:INFO: Eye window for uplink 12: XX______________________________________________________________________________
Clock Delay: 40
08:34:48:setup_element:INFO: Eye window for uplink 13: XX______________________________________________________________________________
Clock Delay: 40
08:34:48:setup_element:INFO: Eye window for uplink 14: XX______________________________________________________________________________
Clock Delay: 40
08:34:48:setup_element:INFO: Eye window for uplink 15: XX______________________________________________________________________________
Clock Delay: 40
08:34:48:setup_element:INFO: Setting the clock phase to 46 for group 0, downlink 1
==============================================OOO==============================================
08:34:48:setup_element:INFO: Scanning data phases
08:34:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:34:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:34:54:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:34:54:setup_element:INFO: Eye window for uplink 0 : XXXXXXX______________________________XXX
Data delay found: 21
08:34:54:setup_element:INFO: Eye window for uplink 1 : XX______________________________XXXXXXXX
Data delay found: 16
08:34:54:setup_element:INFO: Eye window for uplink 2 : XX_______XXXXXXXXXXXX_____________XXXXXX
Data delay found: 27
08:34:54:setup_element:INFO: Eye window for uplink 3 : _________XXXXXXXXXXXX__________XXXXXXXX_
Data delay found: 3
08:34:54:setup_element:INFO: Eye window for uplink 4 : _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
08:34:54:setup_element:INFO: Eye window for uplink 5 : _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
08:34:54:setup_element:INFO: Eye window for uplink 6 : _____________________X__XXXXXXXXXX______
Data delay found: 7
08:34:54:setup_element:INFO: Eye window for uplink 7 : ___________________XXXXXXXXXXXX_________
Data delay found: 4
08:34:54:setup_element:INFO: Eye window for uplink 8 : ___________XXXXXXXX_____________________
Data delay found: 34
08:34:54:setup_element:INFO: Eye window for uplink 9 : ________________XXXXXXXX________________
Data delay found: 39
08:34:54:setup_element:INFO: Eye window for uplink 10: _____________XXXXXXXX___________________
Data delay found: 36
08:34:54:setup_element:INFO: Eye window for uplink 11: _________________XXXXXXX________________
Data delay found: 0
08:34:54:setup_element:INFO: Eye window for uplink 12: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 1
08:34:54:setup_element:INFO: Eye window for uplink 13: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 1
08:34:54:setup_element:INFO: Eye window for uplink 14: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
08:34:54:setup_element:INFO: Eye window for uplink 15: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
08:34:54:setup_element:INFO: Setting the data phase to 21 for uplink 0
08:34:54:setup_element:INFO: Setting the data phase to 16 for uplink 1
08:34:54:setup_element:INFO: Setting the data phase to 27 for uplink 2
08:34:54:setup_element:INFO: Setting the data phase to 3 for uplink 3
08:34:54:setup_element:INFO: Setting the data phase to 3 for uplink 4
08:34:54:setup_element:INFO: Setting the data phase to 3 for uplink 5
08:34:54:setup_element:INFO: Setting the data phase to 7 for uplink 6
08:34:54:setup_element:INFO: Setting the data phase to 4 for uplink 7
08:34:54:setup_element:INFO: Setting the data phase to 34 for uplink 8
08:34:54:setup_element:INFO: Setting the data phase to 39 for uplink 9
08:34:54:setup_element:INFO: Setting the data phase to 36 for uplink 10
08:34:54:setup_element:INFO: Setting the data phase to 0 for uplink 11
08:34:54:setup_element:INFO: Setting the data phase to 1 for uplink 12
08:34:54:setup_element:INFO: Setting the data phase to 1 for uplink 13
08:34:54:setup_element:INFO: Setting the data phase to 3 for uplink 14
08:34:54:setup_element:INFO: Setting the data phase to 3 for uplink 15
==============================================OOO==============================================
08:34:54:setup_element:INFO: Beginning SMX ASICs map scan
08:34:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:34:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:34:54:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:34:54:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:34:54:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:34:54:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:34:54:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:34:54:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:34:54:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:34:54:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:34:54:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:34:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:34:55:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:34:55:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:34:55:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:34:55:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:34:55:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:34:55:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:34:55:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:34:55:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:34:55:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:34:57:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 46
Window Length: 47
Eye Windows:
Uplink 0: XXXXXXXXXXXXXXXXXXXXXXX__________________________________________________XXXXXXX
Uplink 1: XXXXXXXXXXXXXXXXXXXXXXX__________________________________________________XXXXXXX
Uplink 2: XX____________________________________________________________________XXXXXXXXXX
Uplink 3: XX____________________________________________________________________XXXXXXXXXX
Uplink 4: XXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXXXX
Uplink 5: XXXXXXXXXXXXXXXXX_____________________________________________________XXXXXXXXXX
Uplink 6: XXXXXXXXXXXXXXXXX________________________________________________________XXXXXXX
Uplink 7: XXXXXXXXXXXXXXXXX________________________________________________________XXXXXXX
Uplink 8: XXXXXXX_______________________________________________________________XXXXXXXXXX
Uplink 9: XXXXXXX_______________________________________________________________XXXXXXXXXX
Uplink 10: XXXXXXX_X_____________________________________________________________XXXXXXXXXX
Uplink 11: XXXXXXX_X_____________________________________________________________XXXXXXXXXX
Uplink 12: XX______________________________________________________________________________
Uplink 13: XX______________________________________________________________________________
Uplink 14: XX______________________________________________________________________________
Uplink 15: XX______________________________________________________________________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 21
Window Length: 30
Eye Window: XXXXXXX______________________________XXX
Uplink 1:
Optimal Phase: 16
Window Length: 30
Eye Window: XX______________________________XXXXXXXX
Uplink 2:
Optimal Phase: 27
Window Length: 13
Eye Window: XX_______XXXXXXXXXXXX_____________XXXXXX
Uplink 3:
Optimal Phase: 3
Window Length: 10
Eye Window: _________XXXXXXXXXXXX__________XXXXXXXX_
Uplink 4:
Optimal Phase: 3
Window Length: 7
Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 5:
Optimal Phase: 3
Window Length: 7
Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 6:
Optimal Phase: 7
Window Length: 27
Eye Window: _____________________X__XXXXXXXXXX______
Uplink 7:
Optimal Phase: 4
Window Length: 28
Eye Window: ___________________XXXXXXXXXXXX_________
Uplink 8:
Optimal Phase: 34
Window Length: 32
Eye Window: ___________XXXXXXXX_____________________
Uplink 9:
Optimal Phase: 39
Window Length: 32
Eye Window: ________________XXXXXXXX________________
Uplink 10:
Optimal Phase: 36
Window Length: 32
Eye Window: _____________XXXXXXXX___________________
Uplink 11:
Optimal Phase: 0
Window Length: 33
Eye Window: _________________XXXXXXX________________
Uplink 12:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 13:
Optimal Phase: 1
Window Length: 4
Eye Window: ____XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 14:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 15:
Optimal Phase: 3
Window Length: 8
Eye Window: ________XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
==============================================OOO==============================================
08:34:57:setup_element:INFO: Performing Elink synchronization
08:34:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:34:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:34:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:34:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
08:34:57:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:34:57:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
08:34:58:febtest:INFO: Init all SMX (CSA): 30
08:35:11:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:35:11:febtest:INFO: 01-00 | XA-000-09-004-012-006-011-05 | 31.4 | 1153.7
08:35:12:febtest:INFO: 08-01 | XA-000-09-004-012-003-021-09 | 28.2 | 1159.7
08:35:12:febtest:INFO: 03-02 | XA-000-09-004-012-009-014-01 | 31.4 | 1159.7
08:35:12:febtest:INFO: 10-03 | XA-000-09-004-012-008-019-11 | 50.4 | 1088.3
08:35:12:febtest:INFO: 05-04 | XA-000-09-004-012-009-013-01 | 37.7 | 1141.9
08:35:13:febtest:INFO: 12-05 | XA-000-09-004-012-005-012-11 | 18.7 | 1201.0
08:35:13:febtest:INFO: 07-06 | XA-000-09-004-012-004-011-06 | 21.9 | 1195.1
08:35:13:febtest:INFO: 14-07 | XA-000-09-004-012-008-020-11 | 28.2 | 1171.5
08:35:14:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:35:16:ST3_smx:INFO: chip: 1-0 34.556970 C 1165.571835 mV
08:35:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:16:ST3_smx:INFO: Electrons
08:35:16:ST3_smx:INFO: # loops 0
08:35:18:ST3_smx:INFO: # loops 1
08:35:20:ST3_smx:INFO: # loops 2
08:35:21:ST3_smx:INFO: # loops 3
08:35:23:ST3_smx:INFO: # loops 4
08:35:24:ST3_smx:INFO: Total # of broken channels: 0
08:35:24:ST3_smx:INFO: List of broken channels: []
08:35:24:ST3_smx:INFO: Total # of broken channels: 0
08:35:24:ST3_smx:INFO: List of broken channels: []
08:35:26:ST3_smx:INFO: chip: 8-1 28.225000 C 1177.390875 mV
08:35:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:26:ST3_smx:INFO: Electrons
08:35:26:ST3_smx:INFO: # loops 0
08:35:28:ST3_smx:INFO: # loops 1
08:35:29:ST3_smx:INFO: # loops 2
08:35:31:ST3_smx:INFO: # loops 3
08:35:32:ST3_smx:INFO: # loops 4
08:35:34:ST3_smx:INFO: Total # of broken channels: 0
08:35:34:ST3_smx:INFO: List of broken channels: []
08:35:34:ST3_smx:INFO: Total # of broken channels: 1
08:35:34:ST3_smx:INFO: List of broken channels: [96]
08:35:35:ST3_smx:INFO: chip: 3-2 34.556970 C 1171.483840 mV
08:35:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:35:ST3_smx:INFO: Electrons
08:35:35:ST3_smx:INFO: # loops 0
08:35:37:ST3_smx:INFO: # loops 1
08:35:39:ST3_smx:INFO: # loops 2
08:35:40:ST3_smx:INFO: # loops 3
08:35:42:ST3_smx:INFO: # loops 4
08:35:43:ST3_smx:INFO: Total # of broken channels: 0
08:35:43:ST3_smx:INFO: List of broken channels: []
08:35:43:ST3_smx:INFO: Total # of broken channels: 0
08:35:43:ST3_smx:INFO: List of broken channels: []
08:35:45:ST3_smx:INFO: chip: 10-3 50.430383 C 1100.211760 mV
08:35:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:45:ST3_smx:INFO: Electrons
08:35:45:ST3_smx:INFO: # loops 0
08:35:46:ST3_smx:INFO: # loops 1
08:35:48:ST3_smx:INFO: # loops 2
08:35:49:ST3_smx:INFO: # loops 3
08:35:51:ST3_smx:INFO: # loops 4
08:35:52:ST3_smx:INFO: Total # of broken channels: 0
08:35:52:ST3_smx:INFO: List of broken channels: []
08:35:52:ST3_smx:INFO: Total # of broken channels: 0
08:35:52:ST3_smx:INFO: List of broken channels: []
08:35:54:ST3_smx:INFO: chip: 5-4 37.726682 C 1153.732915 mV
08:35:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:54:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:35:54:ST3_smx:INFO: Electrons
08:35:54:ST3_smx:INFO: # loops 0
08:35:56:ST3_smx:INFO: # loops 1
08:35:57:ST3_smx:INFO: # loops 2
08:35:59:ST3_smx:INFO: # loops 3
08:36:01:ST3_smx:INFO: # loops 4
08:36:02:ST3_smx:INFO: Total # of broken channels: 0
08:36:02:ST3_smx:INFO: List of broken channels: []
08:36:02:ST3_smx:INFO: Total # of broken channels: 1
08:36:02:ST3_smx:INFO: List of broken channels: [111]
08:36:04:ST3_smx:INFO: chip: 12-5 18.745682 C 1212.728715 mV
08:36:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:04:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:04:ST3_smx:INFO: Electrons
08:36:04:ST3_smx:INFO: # loops 0
08:36:06:ST3_smx:INFO: # loops 1
08:36:07:ST3_smx:INFO: # loops 2
08:36:09:ST3_smx:INFO: # loops 3
08:36:10:ST3_smx:INFO: # loops 4
08:36:12:ST3_smx:INFO: Total # of broken channels: 0
08:36:12:ST3_smx:INFO: List of broken channels: []
08:36:12:ST3_smx:INFO: Total # of broken channels: 0
08:36:12:ST3_smx:INFO: List of broken channels: []
08:36:14:ST3_smx:INFO: chip: 7-6 21.902970 C 1200.969315 mV
08:36:14:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:14:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:14:ST3_smx:INFO: Electrons
08:36:14:ST3_smx:INFO: # loops 0
08:36:15:ST3_smx:INFO: # loops 1
08:36:17:ST3_smx:INFO: # loops 2
08:36:18:ST3_smx:INFO: # loops 3
08:36:20:ST3_smx:INFO: # loops 4
08:36:21:ST3_smx:INFO: Total # of broken channels: 0
08:36:21:ST3_smx:INFO: List of broken channels: []
08:36:21:ST3_smx:INFO: Total # of broken channels: 0
08:36:21:ST3_smx:INFO: List of broken channels: []
08:36:23:ST3_smx:INFO: chip: 14-7 28.225000 C 1189.190035 mV
08:36:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:36:23:ST3_smx:INFO: Electrons
08:36:23:ST3_smx:INFO: # loops 0
08:36:25:ST3_smx:INFO: # loops 1
08:36:27:ST3_smx:INFO: # loops 2
08:36:28:ST3_smx:INFO: # loops 3
08:36:30:ST3_smx:INFO: # loops 4
08:36:31:ST3_smx:INFO: Total # of broken channels: 0
08:36:31:ST3_smx:INFO: List of broken channels: []
08:36:31:ST3_smx:INFO: Total # of broken channels: 0
08:36:31:ST3_smx:INFO: List of broken channels: []
08:36:32:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:36:32:febtest:INFO: 01-00 | XA-000-09-004-012-006-011-05 | 34.6 | 1189.2
08:36:32:febtest:INFO: 08-01 | XA-000-09-004-012-003-021-09 | 28.2 | 1195.1
08:36:32:febtest:INFO: 03-02 | XA-000-09-004-012-009-014-01 | 34.6 | 1195.1
08:36:33:febtest:INFO: 10-03 | XA-000-09-004-012-008-019-11 | 50.4 | 1124.0
08:36:33:febtest:INFO: 05-04 | XA-000-09-004-012-009-013-01 | 37.7 | 1171.5
08:36:33:febtest:INFO: 12-05 | XA-000-09-004-012-005-012-11 | 18.7 | 1230.3
08:36:33:febtest:INFO: 07-06 | XA-000-09-004-012-004-011-06 | 21.9 | 1224.5
08:36:34:febtest:INFO: 14-07 | XA-000-09-004-012-008-020-11 | 28.2 | 1206.9
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_12_12-08_34_39
OPERATOR : Kerstin S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1302| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 15052 | SIZE: 62x42 | GRADE: A
MODULE_NAME: M4UR1T1011311A2
LADDER_NAME: L4UR101131
------------------------------------------------------------
VI_before_Init : ['2.449', '2.0320', '1.849', '2.0200', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0460', '1.850', '2.4060', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9830', '1.850', '0.5328', '0.000', '0.0000', '0.000', '0.0000']