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FEB_1307 04.12.24 08:23:19
Info
08:23:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:23:19:ST3_Shared:INFO: FEB-Sensor
08:23:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:23:44:ST3_Shared:INFO: STS mode selected
08:24:39:ST3_ModuleSelector:DEBUG: M3DR4B0000130A2
08:24:39:ST3_ModuleSelector:DEBUG: L3DR400013
08:24:39:ST3_ModuleSelector:DEBUG: 25442
08:24:39:ST3_ModuleSelector:DEBUG: 62x42
08:24:39:ST3_ModuleSelector:DEBUG: C
08:24:39:ST3_ModuleSelector:DEBUG: M3DR4B0000130A2
08:24:39:ST3_ModuleSelector:DEBUG: L3DR400013
08:24:39:ST3_ModuleSelector:DEBUG: 25442
08:24:39:ST3_ModuleSelector:DEBUG: 62x42
08:24:39:ST3_ModuleSelector:DEBUG: C
08:24:44:ST3_ModuleSelector:INFO: M3DR4B0000130A2
08:24:44:ST3_ModuleSelector:INFO: 25442
08:24:44:febtest:INFO: Testing FEB with SN 1307
08:24:46:smx_tester:INFO: Scanning setup
08:24:46:elinks:INFO: Disabling clock on downlink 0
08:24:46:elinks:INFO: Disabling clock on downlink 1
08:24:46:elinks:INFO: Disabling clock on downlink 2
08:24:46:elinks:INFO: Disabling clock on downlink 3
08:24:46:elinks:INFO: Disabling clock on downlink 4
08:24:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:24:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:24:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:24:46:elinks:INFO: Disabling clock on downlink 0
08:24:46:elinks:INFO: Disabling clock on downlink 1
08:24:46:elinks:INFO: Disabling clock on downlink 2
08:24:46:elinks:INFO: Disabling clock on downlink 3
08:24:46:elinks:INFO: Disabling clock on downlink 4
08:24:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:24:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
08:24:46:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
08:24:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:24:46:elinks:INFO: Disabling clock on downlink 0
08:24:46:elinks:INFO: Disabling clock on downlink 1
08:24:46:elinks:INFO: Disabling clock on downlink 2
08:24:46:elinks:INFO: Disabling clock on downlink 3
08:24:46:elinks:INFO: Disabling clock on downlink 4
08:24:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:24:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:24:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:24:46:elinks:INFO: Disabling clock on downlink 0
08:24:46:elinks:INFO: Disabling clock on downlink 1
08:24:46:elinks:INFO: Disabling clock on downlink 2
08:24:46:elinks:INFO: Disabling clock on downlink 3
08:24:46:elinks:INFO: Disabling clock on downlink 4
08:24:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:24:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:24:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:24:46:elinks:INFO: Disabling clock on downlink 0
08:24:46:elinks:INFO: Disabling clock on downlink 1
08:24:46:elinks:INFO: Disabling clock on downlink 2
08:24:46:elinks:INFO: Disabling clock on downlink 3
08:24:46:elinks:INFO: Disabling clock on downlink 4
08:24:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:24:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:24:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:24:46:setup_element:INFO: Scanning clock phase
08:24:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:24:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:24:47:setup_element:INFO: Clock phase scan results for group 0, downlink 1
08:24:47:setup_element:INFO: Eye window for uplink 0 : XX_______________________________________________________________________XXXXXXX
Clock Delay: 37
08:24:47:setup_element:INFO: Eye window for uplink 1 : XX_______________________________________________________________________XXXXXXX
Clock Delay: 37
08:24:47:setup_element:INFO: Eye window for uplink 2 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
08:24:47:setup_element:INFO: Eye window for uplink 3 : X________________________________________________________________________XXXXXXX
Clock Delay: 36
08:24:47:setup_element:INFO: Eye window for uplink 4 : _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
08:24:47:setup_element:INFO: Eye window for uplink 5 : _______________________________________________________________________XXXXXXXXX
Clock Delay: 35
08:24:47:setup_element:INFO: Eye window for uplink 6 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 7 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 8 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 9 : _______________________________________________________________________XXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 10: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 11: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:24:47:setup_element:INFO: Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
08:24:47:setup_element:INFO: Eye window for uplink 14: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Eye window for uplink 15: ______________________________________________________________________XXXXXXXXX_
Clock Delay: 34
08:24:47:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
==============================================OOO==============================================
08:24:47:setup_element:INFO: Scanning data phases
08:24:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:24:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:24:52:setup_element:INFO: Data phase scan results for group 0, downlink 1
08:24:52:setup_element:INFO: Eye window for uplink 0 : _____________XXXXXXXXX__________________
Data delay found: 37
08:24:52:setup_element:INFO: Eye window for uplink 1 : _________XXXXXXXX_______________________
Data delay found: 32
08:24:52:setup_element:INFO: Eye window for uplink 2 : ________XXXXXXXX________________________
Data delay found: 31
08:24:52:setup_element:INFO: Eye window for uplink 3 : ______XXXXXXXX__________________________
Data delay found: 29
08:24:52:setup_element:INFO: Eye window for uplink 4 : ______XXXXXXX___________________________
Data delay found: 29
08:24:52:setup_element:INFO: Eye window for uplink 5 : __XXXXXX________________________________
Data delay found: 24
08:24:52:setup_element:INFO: Eye window for uplink 6 : XXXX________________________________XXXX
Data delay found: 19
08:24:52:setup_element:INFO: Eye window for uplink 7 : X_______________________________XXXXXXXX
Data delay found: 16
08:24:52:setup_element:INFO: Eye window for uplink 8 : ___________________________XXXXX________
Data delay found: 9
08:24:52:setup_element:INFO: Eye window for uplink 9 : _______________________________XXXXXXXX_
Data delay found: 14
08:24:52:setup_element:INFO: Eye window for uplink 10: ________________________XXXXXXXXXX______
Data delay found: 8
08:24:52:setup_element:INFO: Eye window for uplink 11: ____________________________XXXXXXXXX___
Data delay found: 12
08:24:52:setup_element:INFO: Eye window for uplink 12: __________________________XXXXXXXX______
Data delay found: 9
08:24:52:setup_element:INFO: Eye window for uplink 13: ______________________________XXXXXXX___
Data delay found: 13
08:24:52:setup_element:INFO: Eye window for uplink 14: ____________________________XXXXXXXX____
Data delay found: 11
08:24:52:setup_element:INFO: Eye window for uplink 15: ______________________________XXXXXXXX__
Data delay found: 13
08:24:52:setup_element:INFO: Setting the data phase to 37 for uplink 0
08:24:52:setup_element:INFO: Setting the data phase to 32 for uplink 1
08:24:52:setup_element:INFO: Setting the data phase to 31 for uplink 2
08:24:52:setup_element:INFO: Setting the data phase to 29 for uplink 3
08:24:52:setup_element:INFO: Setting the data phase to 29 for uplink 4
08:24:52:setup_element:INFO: Setting the data phase to 24 for uplink 5
08:24:52:setup_element:INFO: Setting the data phase to 19 for uplink 6
08:24:52:setup_element:INFO: Setting the data phase to 16 for uplink 7
08:24:53:setup_element:INFO: Setting the data phase to 9 for uplink 8
08:24:53:setup_element:INFO: Setting the data phase to 14 for uplink 9
08:24:53:setup_element:INFO: Setting the data phase to 8 for uplink 10
08:24:53:setup_element:INFO: Setting the data phase to 12 for uplink 11
08:24:53:setup_element:INFO: Setting the data phase to 9 for uplink 12
08:24:53:setup_element:INFO: Setting the data phase to 13 for uplink 13
08:24:53:setup_element:INFO: Setting the data phase to 11 for uplink 14
08:24:53:setup_element:INFO: Setting the data phase to 13 for uplink 15
==============================================OOO==============================================
08:24:53:setup_element:INFO: Beginning SMX ASICs map scan
08:24:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:24:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:24:53:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:24:53:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
08:24:53:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
08:24:53:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
08:24:53:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
08:24:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
08:24:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
08:24:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
08:24:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
08:24:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
08:24:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
08:24:53:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
08:24:53:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
08:24:53:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
08:24:54:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
08:24:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
08:24:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
08:24:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
08:24:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
08:24:55:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 68
Eye Windows:
Uplink 0: XX_______________________________________________________________________XXXXXXX
Uplink 1: XX_______________________________________________________________________XXXXXXX
Uplink 2: X________________________________________________________________________XXXXXXX
Uplink 3: X________________________________________________________________________XXXXXXX
Uplink 4: _______________________________________________________________________XXXXXXXXX
Uplink 5: _______________________________________________________________________XXXXXXXXX
Uplink 6: _______________________________________________________________________XXXXXXXX_
Uplink 7: _______________________________________________________________________XXXXXXXX_
Uplink 8: _______________________________________________________________________XXXXXXXX_
Uplink 9: _______________________________________________________________________XXXXXXXX_
Uplink 10: ______________________________________________________________________XXXXXXXXX_
Uplink 11: ______________________________________________________________________XXXXXXXXX_
Uplink 12: ______________________________________________________________________XXXXXXXX__
Uplink 13: ______________________________________________________________________XXXXXXXX__
Uplink 14: ______________________________________________________________________XXXXXXXXX_
Uplink 15: ______________________________________________________________________XXXXXXXXX_
Data phase characteristics:
Uplink 0:
Optimal Phase: 37
Window Length: 31
Eye Window: _____________XXXXXXXXX__________________
Uplink 1:
Optimal Phase: 32
Window Length: 32
Eye Window: _________XXXXXXXX_______________________
Uplink 2:
Optimal Phase: 31
Window Length: 32
Eye Window: ________XXXXXXXX________________________
Uplink 3:
Optimal Phase: 29
Window Length: 32
Eye Window: ______XXXXXXXX__________________________
Uplink 4:
Optimal Phase: 29
Window Length: 33
Eye Window: ______XXXXXXX___________________________
Uplink 5:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 6:
Optimal Phase: 19
Window Length: 32
Eye Window: XXXX________________________________XXXX
Uplink 7:
Optimal Phase: 16
Window Length: 31
Eye Window: X_______________________________XXXXXXXX
Uplink 8:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 9:
Optimal Phase: 14
Window Length: 32
Eye Window: _______________________________XXXXXXXX_
Uplink 10:
Optimal Phase: 8
Window Length: 30
Eye Window: ________________________XXXXXXXXXX______
Uplink 11:
Optimal Phase: 12
Window Length: 31
Eye Window: ____________________________XXXXXXXXX___
Uplink 12:
Optimal Phase: 9
Window Length: 32
Eye Window: __________________________XXXXXXXX______
Uplink 13:
Optimal Phase: 13
Window Length: 33
Eye Window: ______________________________XXXXXXX___
Uplink 14:
Optimal Phase: 11
Window Length: 32
Eye Window: ____________________________XXXXXXXX____
Uplink 15:
Optimal Phase: 13
Window Length: 32
Eye Window: ______________________________XXXXXXXX__
==============================================OOO==============================================
08:24:55:setup_element:INFO: Performing Elink synchronization
08:24:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:24:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
08:24:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
08:24:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
08:24:55:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
08:24:55:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
08:24:56:febtest:INFO: Init all SMX (CSA): 30
08:25:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:25:11:febtest:INFO: 01-00 | XA-000-09-004-007-014-026-00 | 21.9 | 1177.4
08:25:11:febtest:INFO: 08-01 | XA-000-09-004-007-015-025-13 | 15.6 | 1201.0
08:25:11:febtest:INFO: 03-02 | XA-000-09-004-007-013-026-14 | 37.7 | 1124.0
08:25:11:febtest:INFO: 10-03 | XA-000-09-004-007-015-024-13 | 18.7 | 1189.2
08:25:11:febtest:INFO: 05-04 | XA-000-09-004-007-013-025-14 | 15.6 | 1201.0
08:25:12:febtest:INFO: 12-05 | XA-000-09-004-007-013-023-14 | 25.1 | 1165.6
08:25:12:febtest:INFO: 07-06 | XA-000-09-004-007-014-024-00 | 3.0 | 1242.0
08:25:12:febtest:INFO: 14-07 | XA-000-09-004-007-014-023-00 | 18.7 | 1177.4
08:25:13:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
08:25:15:ST3_smx:INFO: chip: 1-0 21.902970 C 1189.190035 mV
08:25:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:15:ST3_smx:INFO: Electrons
08:25:15:ST3_smx:INFO: # loops 0
08:25:17:ST3_smx:INFO: # loops 1
08:25:18:ST3_smx:INFO: # loops 2
08:25:20:ST3_smx:INFO: # loops 3
08:25:22:ST3_smx:INFO: # loops 4
08:25:23:ST3_smx:INFO: Total # of broken channels: 0
08:25:23:ST3_smx:INFO: List of broken channels: []
08:25:23:ST3_smx:INFO: Total # of broken channels: 0
08:25:23:ST3_smx:INFO: List of broken channels: []
08:25:25:ST3_smx:INFO: chip: 8-1 15.590880 C 1218.600960 mV
08:25:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:25:ST3_smx:INFO: Electrons
08:25:25:ST3_smx:INFO: # loops 0
08:25:27:ST3_smx:INFO: # loops 1
08:25:28:ST3_smx:INFO: # loops 2
08:25:30:ST3_smx:INFO: # loops 3
08:25:32:ST3_smx:INFO: # loops 4
08:25:33:ST3_smx:INFO: Total # of broken channels: 0
08:25:33:ST3_smx:INFO: List of broken channels: []
08:25:33:ST3_smx:INFO: Total # of broken channels: 2
08:25:33:ST3_smx:INFO: List of broken channels: [124, 126]
08:25:35:ST3_smx:INFO: chip: 3-2 37.726682 C 1135.937260 mV
08:25:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:35:ST3_smx:INFO: Electrons
08:25:35:ST3_smx:INFO: # loops 0
08:25:37:ST3_smx:INFO: # loops 1
08:25:38:ST3_smx:INFO: # loops 2
08:25:40:ST3_smx:INFO: # loops 3
08:25:42:ST3_smx:INFO: # loops 4
08:25:43:ST3_smx:INFO: Total # of broken channels: 0
08:25:43:ST3_smx:INFO: List of broken channels: []
08:25:43:ST3_smx:INFO: Total # of broken channels: 0
08:25:43:ST3_smx:INFO: List of broken channels: []
08:25:45:ST3_smx:INFO: chip: 10-3 18.745682 C 1206.851500 mV
08:25:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:45:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:45:ST3_smx:INFO: Electrons
08:25:45:ST3_smx:INFO: # loops 0
08:25:47:ST3_smx:INFO: # loops 1
08:25:48:ST3_smx:INFO: # loops 2
08:25:50:ST3_smx:INFO: # loops 3
08:25:52:ST3_smx:INFO: # loops 4
08:25:53:ST3_smx:INFO: Total # of broken channels: 1
08:25:53:ST3_smx:INFO: List of broken channels: [1]
08:25:53:ST3_smx:INFO: Total # of broken channels: 1
08:25:53:ST3_smx:INFO: List of broken channels: [1]
08:25:55:ST3_smx:INFO: chip: 5-4 12.438562 C 1224.468235 mV
08:25:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:25:55:ST3_smx:INFO: Electrons
08:25:55:ST3_smx:INFO: # loops 0
08:25:57:ST3_smx:INFO: # loops 1
08:25:58:ST3_smx:INFO: # loops 2
08:26:00:ST3_smx:INFO: # loops 3
08:26:02:ST3_smx:INFO: # loops 4
08:26:03:ST3_smx:INFO: Total # of broken channels: 0
08:26:03:ST3_smx:INFO: List of broken channels: []
08:26:03:ST3_smx:INFO: Total # of broken channels: 0
08:26:03:ST3_smx:INFO: List of broken channels: []
08:26:05:ST3_smx:INFO: chip: 12-5 -22.072920 C 1206.851500 mV
08:26:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:26:05:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:26:05:ST3_smx:INFO: Electrons
08:26:05:ST3_smx:INFO: # loops 0
08:26:07:ST3_smx:INFO: # loops 1
08:26:08:ST3_smx:INFO: # loops 2
08:26:10:ST3_smx:INFO: # loops 3
08:26:12:ST3_smx:INFO: # loops 4
08:26:13:ST3_smx:INFO: Total # of broken channels: 0
08:26:13:ST3_smx:INFO: List of broken channels: []
08:26:13:ST3_smx:INFO: Total # of broken channels: 0
08:26:13:ST3_smx:INFO: List of broken channels: []
08:26:15:ST3_smx:INFO: chip: 7-6 -3.285750 C 1277.050060 mV
08:26:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:26:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:26:15:ST3_smx:INFO: Electrons
08:26:15:ST3_smx:INFO: # loops 0
08:26:17:ST3_smx:INFO: # loops 1
08:26:18:ST3_smx:INFO: # loops 2
08:26:20:ST3_smx:INFO: # loops 3
08:26:22:ST3_smx:INFO: # loops 4
08:26:23:ST3_smx:INFO: Total # of broken channels: 0
08:26:23:ST3_smx:INFO: List of broken channels: []
08:26:23:ST3_smx:INFO: Total # of broken channels: 0
08:26:23:ST3_smx:INFO: List of broken channels: []
08:26:25:ST3_smx:INFO: chip: 14-7 12.438562 C 1212.728715 mV
08:26:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:26:25:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:26:25:ST3_smx:INFO: Electrons
08:26:25:ST3_smx:INFO: # loops 0
08:26:27:ST3_smx:INFO: # loops 1
08:26:28:ST3_smx:INFO: # loops 2
08:26:30:ST3_smx:INFO: # loops 3
08:26:31:ST3_smx:INFO: # loops 4
08:26:33:ST3_smx:INFO: Total # of broken channels: 0
08:26:33:ST3_smx:INFO: List of broken channels: []
08:26:33:ST3_smx:INFO: Total # of broken channels: 2
08:26:33:ST3_smx:INFO: List of broken channels: [1, 15]
08:26:33:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:26:34:febtest:INFO: 01-00 | XA-000-09-004-007-014-026-00 | 12.4 | 1242.0
08:26:34:febtest:INFO: 08-01 | XA-000-09-004-007-015-025-13 | 6.1 | 1265.4
08:26:34:febtest:INFO: 03-02 | XA-000-09-004-007-013-026-14 | 28.2 | 1189.2
08:26:34:febtest:INFO: 10-03 | XA-000-09-004-007-015-024-13 | 9.3 | 1253.7
08:26:34:febtest:INFO: 05-04 | XA-000-09-004-007-013-025-14 | 6.1 | 1265.4
08:26:35:febtest:INFO: 12-05 | XA-000-09-004-007-013-023-14 | 18.7 | 1236.2
08:26:35:febtest:INFO: 07-06 | XA-000-09-004-007-014-024-00 | -6.4 | 1306.1
08:26:35:febtest:INFO: 14-07 | XA-000-09-004-007-014-023-00 | 12.4 | 1242.0
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_12_04-08_23_19
OPERATOR : Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1307| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 25442 | SIZE: 62x42 | GRADE: C
MODULE_NAME: M3DR4B0000130A2
LADDER_NAME: L3DR400013
------------------------------------------------------------
VI_before_Init : ['2.449', '1.4060', '1.849', '2.0510', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9740', '1.850', '2.2420', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.8430', '1.850', '0.5005', '0.000', '0.0000', '0.000', '0.0000']