FEB_1314    04.12.24 12:47:58

TextEdit.txt
            12:47:58:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:47:58:ST3_Shared:INFO:	                       FEB-Microcable                       
12:47:58:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:47:59:ST3_Shared:INFO:	STS mode selected
12:47:59:febtest:INFO:	Testing FEB with SN 1314
12:48:01:smx_tester:INFO:	Scanning setup
12:48:01:elinks:INFO:	Disabling clock on downlink 0
12:48:01:elinks:INFO:	Disabling clock on downlink 1
12:48:01:elinks:INFO:	Disabling clock on downlink 2
12:48:01:elinks:INFO:	Disabling clock on downlink 3
12:48:01:elinks:INFO:	Disabling clock on downlink 4
12:48:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
12:48:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:01:elinks:INFO:	Disabling clock on downlink 0
12:48:01:elinks:INFO:	Disabling clock on downlink 1
12:48:01:elinks:INFO:	Disabling clock on downlink 2
12:48:01:elinks:INFO:	Disabling clock on downlink 3
12:48:01:elinks:INFO:	Disabling clock on downlink 4
12:48:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
12:48:01:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
12:48:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:01:elinks:INFO:	Disabling clock on downlink 0
12:48:01:elinks:INFO:	Disabling clock on downlink 1
12:48:01:elinks:INFO:	Disabling clock on downlink 2
12:48:01:elinks:INFO:	Disabling clock on downlink 3
12:48:01:elinks:INFO:	Disabling clock on downlink 4
12:48:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:48:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:01:elinks:INFO:	Disabling clock on downlink 0
12:48:01:elinks:INFO:	Disabling clock on downlink 1
12:48:01:elinks:INFO:	Disabling clock on downlink 2
12:48:01:elinks:INFO:	Disabling clock on downlink 3
12:48:01:elinks:INFO:	Disabling clock on downlink 4
12:48:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:48:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:01:elinks:INFO:	Disabling clock on downlink 0
12:48:01:elinks:INFO:	Disabling clock on downlink 1
12:48:01:elinks:INFO:	Disabling clock on downlink 2
12:48:01:elinks:INFO:	Disabling clock on downlink 3
12:48:01:elinks:INFO:	Disabling clock on downlink 4
12:48:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
12:48:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
12:48:02:setup_element:INFO:	Scanning clock phase
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:48:02:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:48:02:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
12:48:02:setup_element:INFO:	Eye window for uplink 0 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 1 : ________________________________________________________________________XXXXXXXX
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 2 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 3 : ________________________________________________________________________XXXXXXX_
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 4 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 5 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 6 : _________________________________________________________________________XXXXX__
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 7 : _________________________________________________________________________XXXXX__
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 8 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
12:48:02:setup_element:INFO:	Eye window for uplink 9 : ______________________________________________________________________XXXXXXX___
Clock Delay: 33
12:48:02:setup_element:INFO:	Eye window for uplink 10: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:48:02:setup_element:INFO:	Eye window for uplink 11: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:48:02:setup_element:INFO:	Eye window for uplink 12: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:48:02:setup_element:INFO:	Eye window for uplink 13: ______________________________________________________________________XXXXXXXX__
Clock Delay: 33
12:48:02:setup_element:INFO:	Eye window for uplink 14: _________________________________________________________________________XXXXXX_
Clock Delay: 35
12:48:02:setup_element:INFO:	Eye window for uplink 15: _________________________________________________________________________XXXXXX_
Clock Delay: 35
12:48:02:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 1
==============================================OOO==============================================
12:48:02:setup_element:INFO:	Scanning data phases
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:48:02:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:48:07:setup_element:INFO:	Data phase scan results for group 0, downlink 1
12:48:07:setup_element:INFO:	Eye window for uplink 0 : ____________XXXXXXX_____________________
Data delay found: 35
12:48:07:setup_element:INFO:	Eye window for uplink 1 : _______XXXXXXX__________________________
Data delay found: 30
12:48:07:setup_element:INFO:	Eye window for uplink 2 : ______XXXXXXXX__________________________
Data delay found: 29
12:48:07:setup_element:INFO:	Eye window for uplink 3 : ____XXXXXXX_____________________________
Data delay found: 27
12:48:07:setup_element:INFO:	Eye window for uplink 4 : ______XXXXXXX___________________________
Data delay found: 29
12:48:07:setup_element:INFO:	Eye window for uplink 5 : __XXXXXXX_______________________________
Data delay found: 25
12:48:07:setup_element:INFO:	Eye window for uplink 6 : XXXX____________________________X_XXXXXX
Data delay found: 17
12:48:07:setup_element:INFO:	Eye window for uplink 7 : X____________________________XXXXXXXXXX_
Data delay found: 14
12:48:07:setup_element:INFO:	Eye window for uplink 8 : ______________________XXXXXXX___________
Data delay found: 5
12:48:07:setup_element:INFO:	Eye window for uplink 9 : ____________________________XXXXXX______
Data delay found: 10
12:48:07:setup_element:INFO:	Eye window for uplink 10: ________________________XXXXXXX_________
Data delay found: 7
12:48:07:setup_element:INFO:	Eye window for uplink 11: __________________________XXXXXXXXX_____
Data delay found: 10
12:48:07:setup_element:INFO:	Eye window for uplink 12: _____________XXXXXXX_____XXXXXXX________
Data delay found: 2
12:48:07:setup_element:INFO:	Eye window for uplink 13: _____________XXXXXXX_______XXXXXXXXX____
Data delay found: 4
12:48:07:setup_element:INFO:	Eye window for uplink 14: ___________________________XXXXXXXXX____
Data delay found: 11
12:48:07:setup_element:INFO:	Eye window for uplink 15: _____________________________XXXXXXXX___
Data delay found: 12
12:48:07:setup_element:INFO:	Setting the data phase to 35 for uplink 0
12:48:07:setup_element:INFO:	Setting the data phase to 30 for uplink 1
12:48:07:setup_element:INFO:	Setting the data phase to 29 for uplink 2
12:48:07:setup_element:INFO:	Setting the data phase to 27 for uplink 3
12:48:07:setup_element:INFO:	Setting the data phase to 29 for uplink 4
12:48:07:setup_element:INFO:	Setting the data phase to 25 for uplink 5
12:48:07:setup_element:INFO:	Setting the data phase to 17 for uplink 6
12:48:07:setup_element:INFO:	Setting the data phase to 14 for uplink 7
12:48:07:setup_element:INFO:	Setting the data phase to 5 for uplink 8
12:48:07:setup_element:INFO:	Setting the data phase to 10 for uplink 9
12:48:07:setup_element:INFO:	Setting the data phase to 7 for uplink 10
12:48:07:setup_element:INFO:	Setting the data phase to 10 for uplink 11
12:48:08:setup_element:INFO:	Setting the data phase to 2 for uplink 12
12:48:08:setup_element:INFO:	Setting the data phase to 4 for uplink 13
12:48:08:setup_element:INFO:	Setting the data phase to 11 for uplink 14
12:48:08:setup_element:INFO:	Setting the data phase to 12 for uplink 15
==============================================OOO==============================================
12:48:08:setup_element:INFO:	Beginning SMX ASICs map scan
12:48:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:48:08:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:48:08:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
12:48:08:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
12:48:08:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
12:48:08:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
12:48:08:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
12:48:08:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
12:48:08:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
12:48:08:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
12:48:08:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
12:48:08:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
12:48:08:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
12:48:08:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
12:48:08:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
12:48:08:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
12:48:09:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
12:48:09:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
12:48:09:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
12:48:09:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
12:48:09:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
12:48:10:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 69
    Eye Windows:
      Uplink  0: ________________________________________________________________________XXXXXXXX
      Uplink  1: ________________________________________________________________________XXXXXXXX
      Uplink  2: ________________________________________________________________________XXXXXXX_
      Uplink  3: ________________________________________________________________________XXXXXXX_
      Uplink  4: _________________________________________________________________________XXXXXX_
      Uplink  5: _________________________________________________________________________XXXXXX_
      Uplink  6: _________________________________________________________________________XXXXX__
      Uplink  7: _________________________________________________________________________XXXXX__
      Uplink  8: ______________________________________________________________________XXXXXXX___
      Uplink  9: ______________________________________________________________________XXXXXXX___
      Uplink 10: _____________________________________________________________________XXXXXXXX___
      Uplink 11: _____________________________________________________________________XXXXXXXX___
      Uplink 12: ______________________________________________________________________XXXXXXXX__
      Uplink 13: ______________________________________________________________________XXXXXXXX__
      Uplink 14: _________________________________________________________________________XXXXXX_
      Uplink 15: _________________________________________________________________________XXXXXX_
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 35
      Window Length: 33
      Eye Window: ____________XXXXXXX_____________________
    Uplink 1:
      Optimal Phase: 30
      Window Length: 33
      Eye Window: _______XXXXXXX__________________________
    Uplink 2:
      Optimal Phase: 29
      Window Length: 32
      Eye Window: ______XXXXXXXX__________________________
    Uplink 3:
      Optimal Phase: 27
      Window Length: 33
      Eye Window: ____XXXXXXX_____________________________
    Uplink 4:
      Optimal Phase: 29
      Window Length: 33
      Eye Window: ______XXXXXXX___________________________
    Uplink 5:
      Optimal Phase: 25
      Window Length: 33
      Eye Window: __XXXXXXX_______________________________
    Uplink 6:
      Optimal Phase: 17
      Window Length: 28
      Eye Window: XXXX____________________________X_XXXXXX
    Uplink 7:
      Optimal Phase: 14
      Window Length: 28
      Eye Window: X____________________________XXXXXXXXXX_
    Uplink 8:
      Optimal Phase: 5
      Window Length: 33
      Eye Window: ______________________XXXXXXX___________
    Uplink 9:
      Optimal Phase: 10
      Window Length: 34
      Eye Window: ____________________________XXXXXX______
    Uplink 10:
      Optimal Phase: 7
      Window Length: 33
      Eye Window: ________________________XXXXXXX_________
    Uplink 11:
      Optimal Phase: 10
      Window Length: 31
      Eye Window: __________________________XXXXXXXXX_____
    Uplink 12:
      Optimal Phase: 2
      Window Length: 21
      Eye Window: _____________XXXXXXX_____XXXXXXX________
    Uplink 13:
      Optimal Phase: 4
      Window Length: 17
      Eye Window: _____________XXXXXXX_______XXXXXXXXX____
    Uplink 14:
      Optimal Phase: 11
      Window Length: 31
      Eye Window: ___________________________XXXXXXXXX____
    Uplink 15:
      Optimal Phase: 12
      Window Length: 32
      Eye Window: _____________________________XXXXXXXX___

==============================================OOO==============================================
12:48:10:setup_element:INFO:	Performing Elink synchronization
12:48:10:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:48:10:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
12:48:10:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
12:48:10:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
12:48:10:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
12:48:10:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    2    | [(0, 12), (1, 13)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
12:48:11:febtest:INFO:	Init all SMX (CSA): 30
12:48:26:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:48:26:febtest:INFO:	01-00 | XA-000-09-004-007-014-008-07 |  34.6 | 1159.7
12:48:26:febtest:INFO:	08-01 | XA-000-09-004-007-014-003-07 |  53.6 | 1094.2
12:48:27:febtest:INFO:	03-02 | XA-000-09-004-007-013-007-09 |  40.9 | 1135.9
12:48:27:febtest:INFO:	10-03 | XA-000-09-004-012-006-015-05 |  28.2 | 1183.3
12:48:27:febtest:INFO:	05-04 | XA-000-09-004-012-008-025-11 |  44.1 | 1135.9
12:48:27:febtest:INFO:	12-05 | XA-000-09-004-012-005-015-11 |  28.2 | 1177.4
12:48:27:febtest:INFO:	07-06 | XA-000-09-004-012-004-015-06 |  28.2 | 1183.3
12:48:28:febtest:INFO:	14-07 | XA-000-09-004-007-015-007-10 |  31.4 | 1177.4
12:48:29:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
12:48:31:ST3_smx:INFO:	chip: 1-0 	 34.556970 C 	 1171.483840 mV
12:48:31:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:31:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:31:ST3_smx:INFO:		Electrons
12:48:31:ST3_smx:INFO:	# loops 0
12:48:32:ST3_smx:INFO:	# loops 1
12:48:34:ST3_smx:INFO:	# loops 2
12:48:36:ST3_smx:INFO:	Total # of broken channels: 0
12:48:36:ST3_smx:INFO:	List of broken channels: []
12:48:36:ST3_smx:INFO:	Total # of broken channels: 0
12:48:36:ST3_smx:INFO:	List of broken channels: []
12:48:38:ST3_smx:INFO:	chip: 8-1 	 53.612520 C 	 1106.178435 mV
12:48:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:38:ST3_smx:INFO:		Electrons
12:48:38:ST3_smx:INFO:	# loops 0
12:48:39:ST3_smx:INFO:	# loops 1
12:48:41:ST3_smx:INFO:	# loops 2
12:48:43:ST3_smx:INFO:	Total # of broken channels: 0
12:48:43:ST3_smx:INFO:	List of broken channels: []
12:48:43:ST3_smx:INFO:	Total # of broken channels: 0
12:48:43:ST3_smx:INFO:	List of broken channels: []
12:48:44:ST3_smx:INFO:	chip: 3-2 	 40.898880 C 	 1147.806000 mV
12:48:44:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:44:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:45:ST3_smx:INFO:		Electrons
12:48:45:ST3_smx:INFO:	# loops 0
12:48:46:ST3_smx:INFO:	# loops 1
12:48:48:ST3_smx:INFO:	# loops 2
12:48:50:ST3_smx:INFO:	Total # of broken channels: 0
12:48:50:ST3_smx:INFO:	List of broken channels: []
12:48:50:ST3_smx:INFO:	Total # of broken channels: 0
12:48:50:ST3_smx:INFO:	List of broken channels: []
12:48:51:ST3_smx:INFO:	chip: 10-3 	 28.225000 C 	 1195.082160 mV
12:48:51:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:51:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:51:ST3_smx:INFO:		Electrons
12:48:51:ST3_smx:INFO:	# loops 0
12:48:53:ST3_smx:INFO:	# loops 1
12:48:55:ST3_smx:INFO:	# loops 2
12:48:56:ST3_smx:INFO:	Total # of broken channels: 0
12:48:56:ST3_smx:INFO:	List of broken channels: []
12:48:56:ST3_smx:INFO:	Total # of broken channels: 0
12:48:56:ST3_smx:INFO:	List of broken channels: []
12:48:58:ST3_smx:INFO:	chip: 5-4 	 44.073563 C 	 1147.806000 mV
12:48:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:58:ST3_smx:INFO:		Electrons
12:48:58:ST3_smx:INFO:	# loops 0
12:49:00:ST3_smx:INFO:	# loops 1
12:49:01:ST3_smx:INFO:	# loops 2
12:49:03:ST3_smx:INFO:	Total # of broken channels: 0
12:49:03:ST3_smx:INFO:	List of broken channels: []
12:49:03:ST3_smx:INFO:	Total # of broken channels: 0
12:49:03:ST3_smx:INFO:	List of broken channels: []
12:49:05:ST3_smx:INFO:	chip: 12-5 	 28.225000 C 	 1195.082160 mV
12:49:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:49:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:49:05:ST3_smx:INFO:		Electrons
12:49:05:ST3_smx:INFO:	# loops 0
12:49:07:ST3_smx:INFO:	# loops 1
12:49:08:ST3_smx:INFO:	# loops 2
12:49:10:ST3_smx:INFO:	Total # of broken channels: 1
12:49:10:ST3_smx:INFO:	List of broken channels: [3]
12:49:10:ST3_smx:INFO:	Total # of broken channels: 17
12:49:10:ST3_smx:INFO:	List of broken channels: [3, 6, 8, 10, 12, 14, 18, 20, 24, 26, 28, 30, 32, 36, 38, 52, 54]
12:49:12:ST3_smx:INFO:	chip: 7-6 	 28.225000 C 	 1189.190035 mV
12:49:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:49:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:49:12:ST3_smx:INFO:		Electrons
12:49:12:ST3_smx:INFO:	# loops 0
12:49:13:ST3_smx:INFO:	# loops 1
12:49:15:ST3_smx:INFO:	# loops 2
12:49:17:ST3_smx:INFO:	Total # of broken channels: 0
12:49:17:ST3_smx:INFO:	List of broken channels: []
12:49:17:ST3_smx:INFO:	Total # of broken channels: 0
12:49:17:ST3_smx:INFO:	List of broken channels: []
12:49:19:ST3_smx:INFO:	chip: 14-7 	 31.389742 C 	 1189.190035 mV
12:49:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:49:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:49:19:ST3_smx:INFO:		Electrons
12:49:19:ST3_smx:INFO:	# loops 0
12:49:20:ST3_smx:INFO:	# loops 1
12:49:22:ST3_smx:INFO:	# loops 2
12:49:24:ST3_smx:INFO:	Total # of broken channels: 0
12:49:24:ST3_smx:INFO:	List of broken channels: []
12:49:24:ST3_smx:INFO:	Total # of broken channels: 0
12:49:24:ST3_smx:INFO:	List of broken channels: []
12:49:24:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:49:24:febtest:INFO:	01-00 | XA-000-09-004-007-014-008-07 |  34.6 | 1189.2
12:49:24:febtest:INFO:	08-01 | XA-000-09-004-007-014-003-07 |  53.6 | 1130.0
12:49:25:febtest:INFO:	03-02 | XA-000-09-004-007-013-007-09 |  40.9 | 1171.5
12:49:25:febtest:INFO:	10-03 | XA-000-09-004-012-006-015-05 |  28.2 | 1212.7
12:49:25:febtest:INFO:	05-04 | XA-000-09-004-012-008-025-11 |  44.1 | 1165.6
12:49:25:febtest:INFO:	12-05 | XA-000-09-004-012-005-015-11 |  31.4 | 1212.7
12:49:25:febtest:INFO:	07-06 | XA-000-09-004-012-004-015-06 |  31.4 | 1212.7
12:49:26:febtest:INFO:	14-07 | XA-000-09-004-007-015-007-10 |  31.4 | 1206.9
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_12_04-12_47_58
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 1314| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.449', '1.3980', '1.849', '2.5790', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9850', '1.850', '2.3940', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9700', '1.850', '0.5223', '0.000', '0.0000', '0.000', '0.0000']